HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. NO patent licenses are implied.

DA41990615R_1.0 1 1999 Hyundai System IC Division

DESCRIPTION

HV7121B is a highly integrated single chip CMOS color image sensor using Hyundai 0.5um CMOS process

developed for image application to realize high efficiency R/G/B photo sensor. The sensor has 414X314 pixels

total, and 400X300 pixels effective. Each pixel is high photo sensitive, small size active pixel element that

converts photons to analog voltage signal. The sensor has three on-chip 8 bit Digital to Analog Convert (DAC)

and 414 comparators to digitize the pixel output. The three on-chip 8 bit DAC can be used for independent

R/G/B gain control. Hyundai proprietary on-chip CDS circuit can reduce Fixed Pattern Noise (FPN)

dramatically. The whole 8 bit digital color raw data is directly available on the package pins and just few

control signals are needed for whole chip control, so it is very ease to configure a system using the sensor.

FEATURES

400 x 300 pixels resolution

Full function control through standard I

C bus

8um x 8um square pixels

Built-in AGC

High efficiency R/G/B color photo sensors

48Pin CLCC / 20Pin CDIP

Integrated 8-bit ADC for direct digital output

Bayer RGB color pattern

Low power 3.3V operation (5V tolerant I/O)

Anti-blooming circuit

Integrated pan control and window sizing

Flexible exposure time control

Clock speed up to 15MHz

Integrated on-chip timing and drive control

Programmable frame rate and synchronous

format

1/4" optical format

TECHNICAL SPECIFICATION FUNCTIONAL BLOCK DIAGRAM

Pixel resolution

402x302

Pixel size

8x8um

Fill factor

30%

Format

CIF

Sensitivity

TBD

S/R

TBD

Supply voltage for analog

3.3V

Supply voltage for digital

3.3V

Supply voltage for 5V tolerant input

5.0V

Supply current
Operating temperature

0~40 C

Technology

0.5um 3metal CMOS

Pixel

Array

ADC Block

Line Buffer

Control

& Logic

Decoder/Pixel Driver

I2C

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 2 1999 Hyundai System IC Division

ELECTRICAL CHARACTERISTIC

Absolute Maximum Ratings

Supply voltage(Analog, Digital)

3.0 V

3.6 V

Voltage on any input pins

0 V

5.0 V

Operating Temperature

¡ É

Note

: Input pins are 5V tolerant. Stresses exceeding the absolute maximum ratings may induce failure.

DC Operating Conditions

Symbol

Parameter

Units

Min.

Max.

Load[pF]

Notes

Internal operation supply voltage

Volt

3.0

3.6

Input voltage logic "1"

Volt

2.0

6.5

Input voltage logic "0"

Volt

0.8

6.5

Output voltage logic "1"

Volt

2.15

3.6

Output voltage logic "0"

Volt

0.4

Ambient operating temperature

Celsius

AC Operating Conditions

Symbol

Parameter

Max Operation Frequency

Units

Notes

MCLK

Main clock frequency

MHz

SCK

C clock frequency

400

kHz

1. MCLK can be divided according to Clock Divide Register for internal clock.

SCK is driven by host processor. For the detail serial bus timing, refer to I

C Spec.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 3 1999 Hyundai System IC Division

ELECTRO-OPTICAL CHARACTERISTICS

Parameter

Units

Min.

Typical

Max.

Note

Sensitivity

mV / lux sec

TBD

Dark Signal

TBD

Output Saturation Signal

TBD

Blooming

TBD

Dynamic Range

TBD

Shading

TBD

Fixed Pattern Noise

TBD

Note:

1) Measured at 26 [1ux] illumination for exposure time 10 [msec]

2) Measured at zero illumination for exposure time 48 [msec] (T

= 25 C)

3) Measured at V

=3.3V

4) 48dB is limited by 8-bit ADC

5) Variation in individual pixel response over entire sensor area

6) Measured at zero [lux] and 70 [lux] illumination for exposure time 10 [msec] Variation of average

pixel response from column(i) to column(i+2) and from row(i) to raw(i+2) due to Bayer Pattern RGB

sampling.

Remarks : Master Clock = 15MHz

*All values are measured by raw image data from image sensor.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 4 1999 Hyundai System IC Division

INPUT / OUTPUT AC CHARACTERISTICS

All output timing delays are measured with output load 60[pF].

Output delay include the internal clock path delay[6ns] and output driving delay that changes in

respect to the output load, the operating environment, and a board design.

Due to the variable valid time delay of the output, output signals may be latched in the negative

edge of MCLK for the stable data transfer between the image sensor and a host for less than

15MHz operation.

MCLK to HSYNC/VSYNC Timing

T1 : MCLK rising to HSYNC/VSYNC Valid maximum Time : 18ns [output load: 60pF]

T2 : HSYNC/VSYNC Valid Time : minimum 1Clock(subject to T1, T2 timing rule)

MCLK to DATA Timing

T3 : MCLK rising to DATA Valid maximum Time : 18ns [output load: 60pF]
Note) HSYNC signal is high when valid data is on the DATA bus.

MCLK

HSYNC/VSYNC

DATA[7:0]

Valid DATA

MCLK

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 5 1999 Hyundai System IC Division

INPUT / OUTPUT AC CHARACTERISTICS (Continue)

ENB Timing

T4 : ENB Setup Time : 5ns

T5 : ENB Hold Time : 5ns

T6 : ENB Valid Time : minimum 2 Clock

RESET Timing

Must in Valid (active LOW) state at least 8MCLK periods

MCLK

ENB

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 6 1999 Hyundai System IC Division

INPUT / OUTPUT AC CHARACTERISTICS CONTINUE

C Bus (Programming Serial Bus) Timing

C Bus Interface Timing

Parameter

Symbol

Min.

Max.

Unit

SCK clock frequency

sck

400

KHz

Time that I

C bus must be free before a new

transmission can start

buf

1.2

Hold time for a START

1.0

LOW period of SCK

low

1.2

HIGH period of SCK

high

1.0

Setup time for START

1.2

Data hold time

1.3

Data setup time

250

Rise time of both SDA and SCK

250

Fall time of both SDA and SCK

300

Setup time for STOP

1.2

Capacitive load of each bus lines(SDA,SCK)

SDA

SCK

stop

start

tbu f

tlow

thd;sta

thd;dat

thigh

tsu;da t

tsu;sta

tsu;sto

stop

start

thd;sta

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 7 1999 Hyundai System IC Division

PIN CONFIGURATION (48 pin CLCC)

Pin9~16, Pin19~20, Pin33~41 : No Connection

COLOR PATTERN

PIN NO.

NAME

PIN NO.

NAME

SCK

DGND1

DGND

DATA3

ENB

DATA2

DGND

DATA1

MCLK

DATA0

VDD5

DVDD

AVDD

DGND1

AGND

DVDD

AGND

RESET

AVDD

VSYNC

DGND

HSYNC

DATA7

DGND

DATA6

SDA

DATA5

DGND

DATA4

DIE

origin (0,0)

(413, 313)

pixel array

1 0

412

313

312

Read out

start point

413

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 8 1999 Hyundai System IC Division

PIN CONFIGURATION (20 pin CDIP)

COLOR PATTERN

PIN NO.

NAME

PIN NO.

NAME

AGND

DVDD

DATA 7

RESET

DATA 6

VSYNC

DATA 5

HSYNC/DVALID

DATA 4

SDA

DATA 3

SCK

DATA 2

ENB

DATA 1

MCLK

DATA 0

+5V Tolerant

Bias

DGND

AVDD

origin (0,0)

DIE

413 412

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

(413, 313)

active sensing area

313

312

1 0

Read out

Start Point

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 9 1999 Hyundai System IC Division

PIN DESCRIPTION (48 Pin CLCC)

PIN

NAME

I/O

DESCRIPTION

SCK

C Clock ; I

C clock control from IIC master

DGND

Digital Ground

ENB

Sensor Enable Signal ; 'H' enable normal operation
'L' disable sensor by stalling internal clock

DGND

Digital Ground

MCLK

Master Clock (up to 15MHz)
; Global master clock for image sensor internal timing control

VDD5

I/O bias voltage for 5V tolerant *1)

AVDD

Analog Supply Voltage 3.3V

AGND

Analog Ground

9 ~ 16

N.C

No Connection

AGND

Analog Ground

AVDD

Analog Supply Voltage 3.3V

19, 20

Reserved

DGND

Digital Ground

DATA7

Image Data bit 7

DATA6

Image Data bit 6

DATA5

Image Data bit 5

DATA4

Image Data bit 4

DGND

Digital Ground

DATA3

Image Data bit 3

DATA2

Image Data bit 2

DATA1

Image Data bit 1

DATA0

Image Data bit 0

DVDD

Digital Supply Voltage 3.3V

DGND

Digital Ground

33 ~ 41

N.C

No Connection

DVDD

Digital Supply Voltage 3.3V

RESET

Hardware Reset Signal, Active Low

VSYNC

Vertical synchronization signal / Frame start output
; Signal pulse at start of image data frame with programmable
blanking duration

HSYNC

Horizontal synchronization signal / Data valid output

/DVALID

; Data valid when 'H' with programmable blanking duration

DGND

Digital Ground

SDA

I/O

C Data ; I

C standard data I/O port

DGND

Digital Ground

*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 10 1999 Hyundai System IC
Division

PIN DESCRIPTION (20 Pin CDIP)

PIN

NAME

I/O

DESCRIPTION

AGND

Analog Ground

DATA 7

Image data bit 7 ( MSB )

DATA 6

Image data bit 6

DATA 5

Image data bit 5

DATA 4

Image data bit 4

DATA 3

Image data bit 3

DATA 2

Image data bit 2

DATA 1

Image data bit 1

DATA 0

Image data bit 0 ( LSB )

DGND

Digital Ground

DVDD

Digital Supply Voltage, 3.3V

RESET

Hardware Reset Signal, Active Low

VSYNC

Vertical synchronization signal / Frame start output

; Signal pulse at start of image data frame with programmable

blanking duration

HSYNC / DVALID

Horizontal synchronization signal / Data valid output

; Data valid when 'H' with programmable blanking duration

SDA

I/O

C Data ; I

C standard data I/O port

SCK

C Clock ; I

C clock control from IIC master

ENB

Sensor enable signal ; 'H' enable normal operation

'L' disable sensor by stalling internal clock

MCLK

Master Clock(upto 15MHz)

; Global master clock for image sensor internal timing control

+ 5 V

I/O bias voltage for 5V tolerant *1)

AVDD

Analog Supply Voltage 3.3V

*1) Tie to DVDD for 3.3V operation / Tie to 5V for 5V tolerant operation

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 11 1999 Hyundai System IC
Division

Register map

address

Mode A

00h

model_name

rev_num

Mode B

01h

oper_mode

data_type

hs_out

scr_size

shot

int_sel

Mode C

02h

reserved

sw_enb

pwr_dn

color

reserved

Row Start Address High

10h

reserved

r_ad[8]

Row Start Address Low

11h

r_ad[7:0]

Column Start Address High

12h

reserved

c_ad[8]

Column Start Address Low

13h

c_ad[7:0]

Window Height Address High

14h

reserved

h_ad[8]

Window Height Address Low

15h

h_ad[7:0]

Window Width Address High

16h

reserved

w_ad[8]

Window Width Address Low

17h

w_ad[7:0]

HSYNC Blanking Time High

20h

h_blank[15:8]

HSYNC Blanking Time Low

21h

h_blank[7:0]

VSYNC Blanking Time High

22h

v_blank[15:8]

VSYNC Blanking Time Low

23h

v_blank[7:0]

Integration Time High

25h

int_time[23:16]

Integration Time Middle

26h

int_time[15:8]

Integration Time Low

27h

int_time[7:0]

Master Clock Divider

28h

reserved

clk_div[3:0]

Reset Level Control

30h

rst_level[5:0]

Red Color Gain

31h

reserved

red_color[5:0]

Green Color Gain

32h

reserved

green_color[5:0]

Blue Color Gain

33h

reserved

blue_color[5:0]

Pixel Bias Voltage

34h

reserved

pixel_bias[3:0]

Red Offset Gain Control

50h

reserved

red_offset[6:0]

Green Offset Gain Control

51h

reserved

green_offset[6:0]

Blue Offset Gain Control

52h

reserved

blue_offset[6:0]

Low Reference Number High

57h

low_ref_no[15:8]

Low Reference Number Low

58h

low_ref_no[7:0]

High Reference Number High

59h

high_ref_no[15:8]

High Reference Number Low

5Ah

high_ref_no[7:0]

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 12 1999 Hyundai System IC
Division

Register Set Descriptions

All register access can though the I

C multi-byte read and write.

(1) Mode A Register (Address 00h, RO)

This register consist of a model name and revision number. Currently Hyundai has three types of CMOS image

sensor chip, 400*300, 640*480 and 800*600 resolution each. The upper 4 bits is

model_name [3:0] and the lower

4 bits is

rev_num[3:0]. For example it' s value 12h, this mean 400*300 resolution and revision2.0 chip.

< model_name > < rev_num >

400*300 : 0001b Rev. 2.0 : 0010b

(2) Mode B Register (Address 01h, default : 04h, R/W)

This register defines major operation mode of the chip.

Mode B[7:6] :

oper_mode(operating mode) <default value : 00b>

Define operating modes between normal operation and optical and function test operation.

Test operation mode is used for optical and function test. Except for default value, these bits are

reserved for manufacturer.

Bit

operating mode

Normal operation

Reserved

Mode B [5:4] :

data_type(data types) <default value : 00b>

These bits define output pixel data types. For Correlated Double Sampling(CDS), every the pixel of image sensor

are measured twice, reference and data respectively, and reference values or data values can be read out through

pixel data pins selectively using these control bits. To remove the noise caused by circuit, i.e. Fixed Pattern

Noise,

the image sensor performs the CDS in default value. Three output data types are supported as follows.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 13 1999 Hyundai System IC
Division

Bit

Output data type

Data level - Reference level

Reference level

Data level

Reserved

Mode B[3] :

hs_out(HSYNC output configuration) <default value : 0b>

This bit offers two types output style about HSYNC signal. HSYNC only mode and HSYNC & internal

clock mode. If the

hs_out is set to one, HSYNC output signal is ANDed signal of internal pixel clock

and data valid. Otherwise HSYNC output pin keep data high state during valid output period. When

HSYNC & internal clock mode is set, HSYNC output can be used as a pixel data output clock.

data valid

MUX HSYNC

pixel clock

Mode B[3]

Mode B[2] :

scr_size(screen size select) <default value : 1b>

Flexible screen size is very useful for customer. If the

scr_size is set to high, i.e. window mode, only

pixels in windowed area defined by register 10h ~ 17h can be read . But

scr_size is set to low state, i.e.

full screen mode, all pixels in the sensor are read out regardless the values of register 10h ~ 17h. We

can select window mode or full screen mode with this bit. Full screen size is only for chip test.

- window start point :

x : row start address (register 10h, 11h)

y : column start address (register 12h, 13h)

- window end point :

x : row start address + window width address (register 14h, 15h) - 1

y : column start address + window height address (register 16h, 17h) -1

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 14 1999 Hyundai System IC
Division

Mode B

[1] : shot(shot mode) <default value : 0b>

User can select continuous frame mode or snapshot mode according to application.

At the continuous frame mode, pixel data output is updated every VSYNC period. In order to set

snapshot mode, it this bit to ` 1' . In that case, just single frame of pixel data will be read out, then the

sensor stops operation. Snapshot mode can be used for the digital still camera applications.

Mode B[0] :

int_sel(integration time unit select) <default value : 0b>

This bit defines integration time unit i.e. line base or pixel clock base.

Default mode is line unit integration but at the bright condition or if you need precise exposure time

control, pixel mode is recommended. This bit related to integration time register 25h, 26h, and 27h.

Note : Actual integration time can be calculated using three integration time registers and pixel clock

period.

In pixel mode, integration time = (25h, 26h, 27h) * number of pixel period.

In line mode, integration time = (26h, 27h) * number of pixel per line * pixel period.

(cf) number of pixel per line = 414 + HSYNC duration value

(3)

Mode C Register (Address 02h, default : 08h, R/W)

This register controls power down and color select.

Mode C[3] :

sw_enb (software enable : active low)

(400*300 CMOS image sensor only) <

default value : 1b>

This bit is only exist in 400*300 CMOS image sensor chip to enable image sensor operation by

software. This bit has same function as ENB pin control.

It' s very useful for the applications that is needed want to reduce interface pin count to CMOS image

sensor. In that case, cannot ENB pin to VDD line and control the sensor using this bit.

Mode C[2] :

pwr_dn(A/D converter power down) <default value : 0b>

This bit controls power down of A/D converter when sleep mode(idle state) is set by ENB pin is low or

sw_enb(Mode C[3]) is high. When set to high, A/D converter is turned on whenever ENB is low or

sw_enb is high. When set to low, A/D converter is turned off always regardless ENB pin state or

sw_enb state . But digital block goes to power down mode always when ENB is low regardless this bit.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 15 1999 Hyundai System IC
Division

Mode C[1] :

color(color select) <default value : 0b>

This bit selects color mode or monochrome mode. Default value means color image sensor and all

three ADCs are used for Bayer RGB color pattern respectively, then RGB gains are controlled

independently. But when set this to one, i.e. monochrome mode, just single ADC is used for all pixels

regardless RGB color.

At the monochrome mode all pixels are controlled by ` G' gain only. ` R' and ` B' gain are not used. In case

of monochrome image sensor, this bit should be set to ` 1' get the good image and to simplify the sensor

control.

(4) Row start address Register

(Higher byte : Address 10h, default : 00h, R/W)

(Lower byte : Address 11h, default : 06h, R/W)

Define window start position row start address of display window. Should be programmed with value between

6 and 306.

(5) Column start address Register

(Higher byte : Address 12h, default : 00h, R/W)

(Lower byte : Address 13h, default : 06h, R/W)

Define window start position column address of display window. Should be programmed with value between

6 and 406.

(6) Window Height address Register

(Higher byte : Address 14h, default : 01h, R/W)

(Lower byte : Address 15h, default : 2Eh, R/W)

Define display window height. If you need smaller display window height, decrease the value.

Window end position row address = row start address + window height address 1

(7) Window width address Register

(Higher byte : Address 16h, default : 01h, R/W)

(Lower byte : Address 17h, default : 92h, R/W)

Define display window width. If you need smaller display window width, decrease the value.

Window end position column address = column start address + window width address -1

Note : Display window programming.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 16 1999 Hyundai System IC
Division

< Display Window Programming >

The 400*300 resolution chip can read any user specific window area within active window area. This is

called panning function. For this function, ` row start' , ` column start' , ` width' , and ` height' can be

programmed with four sets of register pair.

FRS : Frame Row Start

FCS : Frame Column Start

FWH : Frame

window Height

FWW : Frame Window Width

Panning window can be programmed as below.

(413,313) manufacturer area (0, 313)

(407,307)

{FWHU,FWHL}

{FRSU,FRSL}

(6,6)

(413,0) (0,0)

{FWWU,FWWL}

{FCSU,FCSL}

active window area

Note 1) Accessible pixel array size is 402*302.

The edge of accessible pixel array may be commonly dedicated for just color interpolation.

In the case of a color image sensor the interpolation is needed to get all R,G,B color value for each pixel

from a Bayer color image.

So one more extra pixel line is needed at the edge of pixel array that you want to be

displayed. That is, to make

400*300 effective window, 402*302 pixel array necessary.

You have to consider this interpolation line when you program the ` Frame register' .

For example, if you want to get 300*250 image size, you have to program 302*252 to frame register.

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 17 1999 Hyundai System IC
Division

FRSU, FRSL 6 FWHU, FWHL 402

FCSU, FCSL 6 FWWU, FWWL 302

< Pixel Array Structure >

(8) HSYNC Blanking Time Register

(Higher byte : Address 20h, default : 00h, R/W)

(Lower byte : Address 21h, default : 03h, R/W)

The HSYNC blanking time defines HSYNC low duration between data valid HSYNC high, pixel unit . HSYNC

low duration is HSYNC blanking time plus twelve in pixel unit for example, default HSYNC low duration is 15

pixels because register value is 3.

It' s used to change duration between current line end and next line start.

+1 : dummy area

+1 : interpolation area

+3 : margin for metal 3 slope

+2 : optical block zone

+1 : dummy zone for set of color pattern

pixel array : 400 * 300

Total pixel : 416 * 316

- - - -

Active window area (402 * 302)

Accessible address range(414 * 314)

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CMOS IMAGE SENSOR

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DA41990615R_1.0 18 1999 Hyundai System IC
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(9) VSYNC Blanking Time Register

(Higher byte : Address 22h, default : 00h, R/W)

(Lower byte : Address 23h, default : 03h, R/W)

The VSYNC blank, and time defines VSYNC active duration in pixel unit .

Note : HSYNC blanking, VSYNC blank are used to fit the CMOS sensor display timing to external timing

requirements.

(10) Integration time Register

(High byte : Address 25h, default : 00h, R/W)

(Middle byte : Address 26h, default : 01h, R/W)

(Low byte : Address 27h, default : f4h, R/W)

Each pixel has a photo diode in which the incoming photons are converted to electrons. Integration time mean

exposure time so these registers defines exposure time.

According to settings

int_sel of Mode B register, the integration time is controlled with line or pixel unit.

Small value means short exposure time and large value means long exposure time for bright condition.

The value should be large for dark condition. Default value setting 500 lines, this value is useful for normal

office condition. If you stay in outdoor condition, this value should be decreased. But under dark condition, this

value should be increased to get a good image quality. Increasing value may decrease frame rate. Finally,

integration time is very important for frame rate and image quality.

For line mode exposure, register 26h and 27h are used. For pixel mode exposure, all three register 25h ~ 27h

are used. To control exposure time precisely, the pixel mode should be used. This register may be used for

Auto Exposure control.

(11) Operating Clock Divider (Address 28h, default:00h, R/W)

This register generates divided digital clock depending on the settings

clk_div [3:0], digital block can divide

MCLK down by 1 through 2048 as shown in Table 1.

clk_div

[3:0]

units

clk_div[3:0] units

0000

no division

0101

MCLK/64

0001

MCLK/2

0111

MCLK/128

0010

MCLK/4

1000

MCLK/256

0011

MCLK/8

1001

MCLK/512

0100

MCLK/16

1010

MCLK/1024

0101

MCLK/32

1011

MCLK/2048

Table 1. Operating Clock Control Register

HV7121B

Electronics Industries Co., Ltd.

CMOS IMAGE SENSOR

System IC Division

With 8-bit ADC

DA41990615R_1.0 19 1999 Hyundai System IC
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(12) Reset Level Control Register (Address 30h, default:38h, R/W)

This register controls reference voltage level for start point of data reading. If the register value is too large or

too small, the vertical Fixed Pattern Noise(FPN) can be occurred. To Get rid of FPN, this register must have a

suitable value. Optimum reset revel can be found using Low reference number registers 57h ~ 58h and High

reference number registers 59h ~ 5ah. If there is some large value in Low reference number registers, the

value of Reset Level control register should be increased. If there is some large value in High reference

number registers, the value of register should be decrease. Optimum reset revel is achieved when value of

Low reference level number registers and value of High reference number registers is minimized.

(13) Color Gain Register

Red Color Gain Register : (Address 31h, default:1Eh, R/W)

Green Color Gain Register : (Address 32h, default:h1Eh, R/W)

Blue Color Gain Register : (Address 33h, default:h1Eh, R/W)

These registers are used to amplify the analog pixel output. If the gain register value is decreased, the

amplification is increased. Therefore under the dark light source condition, the pixel output have to be amplified

by decreasing gain value to get good image. There are three Gain registers to control RGB colors

independently. In the case of monochrome image sensor, use only Green Color Gain Register. Available

program range is 0 ~ 63 but too small value can cause FPN. The register value have to chosen within the range

that doesn' t cause FPN. Recommended range is 20 ~63. These register can be used for Auto White Balance

control and Auto Exposure control.

(14) Pixel Bias Voltage Register (Address 34h, default:02h, R/W)

This register controls pixel reference level by controlling bias current of pixel output sensing load transistor. It

controls pixel output level itself, compare with that revel register adjust A/D Converter circuit to calibrate

reference level for data reading. Available program range is 0 ~ 7. The larger register value causes the higher

bias current and low pixel output reference level. This register is option for manufacturer. Users may use default

setting and don' t changed value.

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(15) Low Reference Number Register(low_ref_no)

High : (Address 57h default:00h, Read Only)

Low : (Address 58h, default:00h, Read Only)

Low Reference Number Registers indicates number of pixels in frame that have a value less then 5. A

reference level values of each pixel is compare with ` 5' , and accumulated to these registers during read state.

This counter value called

low_ref_no, consist of two bytes and it is read only registers. Real number of pixels

that have value less than 5 is the twice of these register value. If

low_ref_no is big value, you must increase

data value of Reset Level Control Register. These registers are updated after every VSYNC signal.

(16) High Reference Number Register (high_ref_no)

High : (Address 59h, default:00h, Read Only)

Low : (Address 5Ah, default:00h, Read Only)

High Reference Number Registers indicates number of pixels in a frame that have a value great then 123.

Reference level values of each pixels is compared with ` 123' , and accumulated to these registers during read

state. This counter value called

high_ref_no, consist of two bytes and it is read only registers. Real number of

pixels that have value great than 123 is the twice of these register value. If

high_ref_no is big value, you must

decrease data value of Reset Level Control Register. These registers are also updated after every VSYNC

signal.

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FRAME TIMING DIAGRAMS

There are two frame timing cases,

Integration Time < EffectiveWindowHeight * Scale

Integration Time > EffectiveWindowHeight * Scale

EffectiveWindowHeight is equal to the number of data lines generated in a frame and is defined to be selected by

if((RowStartAddress + WindowHeight + 1) <= (SensorArrayHeight)

EffectiveWindowHeight = WindowHeight;

else

EffectiveWidnowHeight = (SensorArrayHeight - RowStartAddress - 1);

For example, RowStartAddress = 200 and WindowHeight = 300, EffectiveWindowHeight is 113 and 113 data lines per

a frame are generated.

Note : The above selection logic is somewhat confusing in respect of general counting measure. It' s partly due to the

mixed use of indexing start points, i.e. ` 0' and ` 1' in the design. Therefore in order to avoid the confusion it is

desirable to just follows the equation when you estimate the frame rate.

Scale is selected according to Integration Time Mode by

If(PixelMode)

Scale = SensorArrayWidth; // For400*300 resolution chip, SensorArrayWidth is 414

else

Scale = 1;

When Integration Time > (EffectiveWindowHeight * Scale), next frame VSYNC does not follow immediately after

current frame' s last line has been produced. Instead, one of the following two idle time slots is inserted according to

Integration Time Mode before next frame VSYNC gets active.

SensorArrayHeight

[314]

SensorArrayWidth

[414]

RowStartAddress

[200]

WindowHeight

[300]

EffectiveWindowHeight

[113]

(0,0)

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< Idle Slots >

Line Mode: (Integration Time - EffectiveWindowHeight) * 1024 clocks

Pixel Mode: (Integration Time - EffectiveWindowHeigth * Scale)

= (Integration Time - EffectiveWindowHeigth * SensorArrayWidth) clocks

Each Frame Timing of the above cases may be decomposed into four timing segments

Initial Data Setup Time after ENB gets active

Even Line

Odd Line

Frame Transition

The subsections will describe frame timing diagram for said frame time cases, (Integration Time < Effective Window

Height * Scale) and (Integration Time > Effective Window Height * Scale)

(1) Frame Timing Diagram for Integration Time < (EffectiveWindowHeight * Scale)

Frame timing related registers are programmed to suit for the above condition as follows

RowStartAddress = 6; WindowHeight = 302;

ColumnStartAddress = 6; WindowWidth = 402;

IntegrationTime = 200 [Line Mode];

EffectiveWindowHeight is "302" for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 >

(6 + 302 + 1), is met, and Scale is "1" for integration time is line mode.

Therefore, (Integration Time< EffectiveWindowHeight * Scale), i.e. 200 < 302 * 1, is met.

Overall Frames Sequence

Initial Data Setup Time

Line 0

Line 1

Line 2

Line

300

....

Line

301

VSYNC

Line 0

Line 1

Line 2

Line

300

....

Line

301

VSYNC

Line 0

Line 1

Line 2

Line

300

....

Line

301

VSYNC

....

Frame 1

Frame 2

Frame 0

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MCLK

ENB

VSYNC

Delay

Slots

Fig. 1 Initial Data Setup Time after ENB gets active

MCLK

HSYNC

DATA

Time

Slot

Clock

Ruler

Fig.2 Even Line Data Timing

IMAGE RAW DATA

Window Width

402 clocks

B G

ENB+

Deglitch

2 clocks

Sensor Reset

SensorArrayHeight clocks

[314 clocks]

One Line Time Delay
(SensorArrayWidth +

HBLANK) clocks

[417 clocks]

VSYNC
3 clocks

Integration Time * Scale

clocks

[200 * 414 clocks]

Line Head

Blank

6 clocks

HBLANK

3 clocks

B G

B G B G B G

Line Tail

Blank

6 clocks

SensorArrayWidth (414)

HBLANK(3)

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MCLK

HSYNC

DATA

Time

Slot

Clock

Ruler

Fig.3 Odd Line Data Timing

MCLK

HSYNC

VSYNC

DATA

Time

Slot

Integration Time < EffectiveWindowHeight * Scale

Fig.4 Frame Transition Timing

G R

Line Head

Blank

6 clocks

Line Tail

Blank

6 clocks

IMAGE RAW DATA

Window Width

402 clocks

IMAGE RAW DATA

Window Width

402 clocks

HBLANK

3 clocks

G R G R

G R G R G R

Line Tail

Blank

6 clocks

Line Head

Blank

6 clocks

SensorArrayWidth (414)

HBLANK(3)

IMAGE RAW DATA

Window Width

402 clocks

VSYNC
3 clocks

HBLANK

3 clocks

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(2) Frame Timing Diagram for Integration Time > (EffectiveWindowHeight * Scale)

Frame timing related registers are programmed to suit for the above condition as follows

RowStartAddress = 6; WindowHeight = 302;

ColumnStartAddress = 6; WindowWidth = 402;

IntegrationTime = 600 [Line Mode];

EffectiveWindowHeight is "302" for (SensorArrayHeight > (RowStartAddress + WindowHeight + 1)), i.e. 314 > (6

+ 302 + 1), is met, and Scale is " 1" for integration time is line mode. Therefore, (Integration Time <

EffectiveWindowHeight * Scale), i.e. 600 > 302 * 1, is met, and Idle Slot of Line Mode, i.e. (600 - 302) * 1024

clocks idle slot, is inserted before the next frame initiation.

Overall Frames Sequence

MCLK

ENB

VSYNC

Delay

Slots

Fig. 5 Initial Data Setup Time after ENB gets active

Line

301

ENB

Deglitch

2 clocks

Sensor Reset

SensorArrayHeight clocks

[314 clocks]

One Line Time Delay
(SensorArrayWidth +

HBLANK) clocks

[417 clocks]

VSYNC
3 clocks

Integration Time * Scale

clocks

[600 * 414 clocks]

Initial Data Setup Time

Line 0

Line 1

Line 2

Line

300

....

Line

301

VSYNC

Line 0

Line 1

Line 2

Line

300

....

VSYNC

Line 0

Line 1

Line 2

Line

300

....

Line

301

VSYNC

Idle

Time

Idle

Time

Idle

Time

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MCLK

HSYNC

DATA

Time

Slot

Clock

Ruler

Fig.6 Even Line Data Timing

MCLK

HSYNC

DATA

Time

Slot

Clock

Ruler

Fig.7 Odd Line Data Timing

IMAGE RAW DATA

Window Width

402 clocks

Line Head

Blank

6 clocks

Line Head

Blank

6 clocks

IMAGE RAW DATA

Window Width

402 clocks

HBLANK

3 clocks

HBLANK

3 clocks

R G

Line Tail

Blank

6 clocks

Line Tail

Blank

6 clocks

SensorArrayWidth (414)

HBLANK(3)

G R

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MCLK

HSYNC

VSYNC

DATA

Time

Slot

Integration Time > EffectiveWindowHeight * Scale

Fig.8 Frame Transition Timing

G R G R

Line Tail

Blank

6 clocks

IMAGE RAW DATA

Window Width

402 clocks

Line Head

Blank

6 clocks

IMAGE RAW DATA

Window Width

402 clocks

VSYNC
3 clocks

Idle Slot

(Integration Time -

EffectiveWindowHeig

ht) * 1024

= (600 - 482) * 1024

HBLANK

3 clocks

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MEMO

Hyundai Electronics Industries Co., Ltd

System IC Division

Headquarter & Factory

San 136-1,Ami-Ri,Bubal-Eub,Ichon-Si,Kyoungki-Do,Korea 467-860

Tel : 82-336-630-2042/2484, Fax : 82-336-639-1412, E-mail : wkkim@hei.co.kr

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