KEY FEATURES
n
5 Volt Read, Program, and Erase
Minimizes system-level power requirements
n
High Performance
Access times as fast as 45 ns
n
Low Power Consumption
20 mA typical active read current in byte
mode, 28 mA typical in word mode
30 mA typical program/erase current
5 A maximum CMOS standby current
n
Compatible with JEDEC Standards
Package, pinout and command-set
compatible with the single-supply Flash
device standard
Provides superior inadvertent write
protection
n
Sector Erase Architecture
Boot sector architecture with top and
bottom boot block options available
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and seven 64 Kbyte sectors in byte mode
One 8 Kword, two 4 Kword, one 16 Kword
and seven 32 Kword sectors in word mode
A command can erase any combination of
sectors
Supports full chip erase
n
Erase Suspend/Resume
Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
n
Sector Protection
Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n
Temporary Sector Unprotect
Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
Byte programming time: 7 s typical
Sector erase time: 1.0 sec typical
Chip erase time: 11 sec typical
n
Data# Polling and Toggle Status Bits
Provide software confirmation of
completion of program or erase
operations
n
Ready/Busy# Output (RY/BY#)
Provides hardware confirmation of
completion of program and erase
operations
n
100,000 Program/Erase Cycles Minimum
n
Space Efficient Packaging
Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
Revision 5.2, May 2001
GENERAL DESCRIPTION
The HY29F400 is a 4 Megabit, 5 volt only CMOS
Flash memory organized as 524,288 (512K) bytes
or 262,144 (256K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F400 can be programmed and erased
in-system with a single 5-volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55 ns over
the full operating voltage range of 5.0 volts 10%
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-
A[17:0]
18
C E #
O E #
R E S E T #
B Y T E #
W E #
8
7
DQ[7:0]
DQ[14:8]
DQ[15]/A-1
R Y / B Y #
LOGIC DIAGRAM
HY29F400
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
2
Rev. 5.2/May 01
HY29F400
cessors. A 55 ns version operating over 5.0 volts
5% is also available. To eliminate bus conten-
tion, the HY29F400 has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte or word
at a time by executing the four-cycle Program com-
mand. This initiates an internal algorithm that au-
tomatically times the program pulse widths and
verifies proper cell margin.
The HY29F400's sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
device while it is in the system (e.g., by a virus),
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en-
abled in a PROM programmer. Temporary Sec-
tor Unprotect, which requires a high voltage, al-
lows in-system erasure and code changes in pre-
viously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V
CC
detector
that automatically inhibits write operations during
power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
BLOCK DIAGRAM
STATE
C O N T R O L
W E #
C E #
OE#
BYTE#
C O M M A N D
R E G I S T E R
DQ[15:0]
A[17:0], A-1
V
C C
D E T E C T O R
T I M E R
E R A S E V O L T A G E
G E N E R A T O R A N D
S E C T O R S W I T C H E S
P R O G R A M
V O L T A G E
G E N E R A T O R
ADDRESS LATCH
X - D E C O D E R
Y - D E C O D E R
4 Mb FLASH
M E M O R Y
A R R A Y
Y-GATING
D A T A L A T C H
I/O BUFFERS
I/O CONTROL
R E S E T #
DQ[15:0]
A[17:0], A-1
RY/BY#
3
Rev. 5.2/May 01
HY29F400
PIN CONFIGURATIONS
Standard
TSOP48
D Q 7
D Q 1 4
44
43
D Q 6
D Q 1 3
42
41
D Q 5
D Q 1 2
40
39
D Q 4
V
CC
38
37
D Q 1 1
D Q 3
36
35
D Q 1 0
D Q 2
34
33
D Q 9
D Q 1
32
31
D Q 8
D Q 0
30
29
A16
BYTE#
48
47
V
SS
DQ15/A-1
46
45
O E #
V
SS
28
27
C E #
A0
26
25
A11
A10
5
6
A9
A8
7
8
N C
N C
9
10
W E #
R E S E T #
11
12
N C
N C
13
14
RY/BY#
N C
15
16
A17
A7
17
18
A6
A5
19
20
A15
A14
1
2
A13
A12
3
4
A4
A3
21
22
A2
A1
23
24
Reverse
TSOP48
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
48
47
46
45
28
27
26
25
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
21
22
23
24
A11
A10
A9
A8
N C
N C
W E #
R E S E T #
N C
N C
RY/BY#
N C
A17
A7
A6
A5
A15
A14
A13
A12
A4
A3
A2
A1
D Q 7
D Q 1 4
D Q 6
D Q 1 3
D Q 5
D Q 1 2
D Q 4
V
CC
D Q 1 1
D Q 3
D Q 1 0
D Q 2
D Q 9
D Q 1
D Q 8
D Q 0
A16
BYTE#
V
SS
DQ15/A-1
O E #
V
SS
C E #
A0
A6
A5
5
6
A4
A3
7
8
A2
A1
9
10
A0
C E #
11
12
V
SS
O E #
13
14
D Q 0
D Q 8
15
16
D Q 1
D Q 9
17
18
D Q 2
D Q 1 0
19
20
D Q 3
D Q 1 1
21
22
N C
RY/BY#
1
2
A17
A7
3
4
A10
A11
40
39
A12
A13
38
37
A14
A15
36
35
A16
BYTE#
34
33
V
SS
DQ15/A-1
32
31
D Q 7
D Q 1 4
30
29
D Q 6
D Q 1 3
28
27
D Q 5
D Q 1 2
26
25
D Q 4
V
CC
24
23
R E S E T #
W E #
44
43
A8
A9
42
41
PSOP44
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A `#' symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
4
Rev. 5.2/May 01
HY29F400
SIGNAL DESCRIPTIONS
e
m
a
N
e
p
y
T
n
o
i
t
p
i
r
c
s
e
D
]
0
:
7
1
[
A
s
t
u
p
n
I
.
h
g
i
H
e
v
i
t
c
a
,
s
s
e
r
d
d
A
4
4
1
,
2
6
2
f
o
e
n
o
t
c
e
l
e
s
s
t
u
p
n
i
8
1
e
s
e
h
t
,
e
d
o
m
d
r
o
W
n
I
e
s
e
h
t
,
e
d
o
m
e
t
y
B
n
I
.
s
n
o
i
t
a
r
e
p
o
e
t
i
r
w
r
o
d
a
e
r
r
o
f
y
a
r
r
a
e
h
t
n
i
h
t
i
w
s
d
r
o
w
)
K
6
5
2
(
8
8
2
,
4
2
5
f
o
e
n
o
t
c
e
l
e
s
o
t
)
B
S
L
(
t
u
p
n
i
1
-
A
/
5
1
Q
D
e
h
t
h
t
i
w
d
e
n
i
b
m
o
c
e
r
a
s
t
u
p
n
i
.
s
n
o
i
t
a
r
e
p
o
e
t
i
r
w
r
o
d
a
e
r
r
o
f
y
a
r
r
a
e
h
t
n
i
h
t
i
w
s
e
t
y
b
)
K
2
1
5
(
,
]
1
-
[
A
/
]
5
1
[
Q
D
]
0
:
4
1
[
Q
D
s
t
u
p
t
u
O
/
s
t
u
p
n
I
e
t
a
t
s
-
i
r
T
h
g
i
H
e
v
i
t
c
a
,
s
u
B
a
t
a
D
h
t
a
p
a
t
a
d
t
i
b
-
6
1
a
e
d
i
v
o
r
p
s
n
i
p
e
s
e
h
t
,
e
d
o
m
d
r
o
W
n
I
.
h
t
a
p
a
t
a
d
t
i
b
-
8
n
a
e
d
i
v
o
r
p
]
0
:
7
[
Q
D
,
e
d
o
m
e
t
y
B
n
I
.
s
n
o
i
t
a
r
e
p
o
e
t
i
r
w
d
n
a
d
a
e
r
r
o
f
]
8
:
4
1
[
Q
D
.
t
u
p
n
i
s
s
e
r
d
d
a
e
t
y
b
t
i
b
-
9
1
e
h
t
f
o
B
S
L
e
h
t
s
a
d
e
s
u
s
i
]
1
-
[
A
/
]
5
1
[
Q
D
d
n
a
.
e
d
o
m
e
t
y
B
n
i
d
e
t
a
t
s
-
i
r
t
n
i
a
m
e
r
d
n
a
d
e
s
u
n
u
e
r
a
#
E
T
Y
B
t
u
p
n
I
.
w
o
L
e
v
i
t
c
a
,
e
d
o
M
e
t
y
B
.
e
c
i
v
e
d
e
h
t
f
o
n
o
i
t
a
r
u
g
i
f
n
o
c
d
r
o
W
/
e
t
y
B
e
h
t
s
l
o
r
t
n
o
C
.
e
d
o
m
d
r
o
W
s
t
c
e
l
e
s
h
g
i
H
,
e
d
o
m
e
t
y
B
s
t
c
e
l
e
s
w
o
L
#
E
C
t
u
p
n
I
.
w
o
L
e
v
i
t
c
a
,
e
l
b
a
n
E
p
i
h
C
r
o
m
o
r
f
a
t
a
d
d
a
e
r
o
t
d
e
t
r
e
s
s
a
e
b
t
s
u
m
t
u
p
n
i
s
i
h
T
e
c
i
v
e
d
e
h
t
d
n
a
d
e
t
a
t
s
-
i
r
t
s
i
s
u
b
a
t
a
d
e
h
t
,
h
g
i
H
n
e
h
W
.
0
0
4
F
9
2
Y
H
e
h
t
o
t
a
t
a
d
e
t
i
r
w
.
e
d
o
m
y
b
d
n
a
t
S
e
h
t
n
i
d
e
c
a
l
p
s
i
#
E
O
t
u
p
n
I
w
o
L
e
v
i
t
c
a
,
e
l
b
a
n
E
t
u
p
t
u
O
s
n
o
i
t
a
r
e
p
o
d
a
e
r
r
o
f
d
e
t
r
e
s
s
a
e
b
t
s
u
m
t
u
p
n
i
s
i
h
T
.
d
r
o
w
a
r
o
e
t
y
b
a
r
e
h
t
e
h
w
s
e
n
i
m
r
e
t
e
d
#
E
T
Y
B
.
s
n
o
i
t
a
r
e
p
o
e
t
i
r
w
r
o
f
d
e
t
a
g
e
n
d
n
a
e
r
a
e
c
i
v
e
d
e
h
t
m
o
r
f
s
t
u
p
t
u
o
a
t
a
d
,
h
g
i
H
n
e
h
W
.
n
o
i
t
a
r
e
p
o
d
a
e
r
e
h
t
g
n
i
r
u
d
d
a
e
r
s
i
.
e
t
a
t
s
e
c
n
a
d
e
p
m
i
h
g
i
h
e
h
t
n
i
d
e
c
a
l
p
e
r
a
s
n
i
p
s
u
b
a
t
a
d
e
h
t
d
n
a
d
e
l
b
a
s
i
d
#
E
W
t
u
p
n
I
.
w
o
L
e
v
i
t
c
a
,
e
l
b
a
n
E
e
t
i
r
W
d
n
a
m
m
o
c
r
o
s
d
n
a
m
m
o
c
f
o
g
n
i
t
i
r
w
s
l
o
r
t
n
o
C
A
.
y
a
r
r
a
y
r
o
m
e
m
e
h
t
f
o
s
r
o
t
c
e
s
e
s
a
r
e
r
o
a
t
a
d
m
a
r
g
o
r
p
o
t
r
e
d
r
o
n
i
s
e
c
n
e
u
q
e
s
#
E
O
d
n
a
w
o
L
s
i
#
E
C
e
li
h
w
d
e
t
r
e
s
s
a
s
i
#
E
W
n
e
h
w
e
c
a
l
p
s
e
k
a
t
n
o
i
t
a
r
e
p
o
e
t
i
r
w
e
t
i
r
w
e
h
t
g
n
i
r
u
d
n
e
t
t
i
r
w
s
i
d
r
o
w
a
r
o
e
t
y
b
a
r
e
h
t
e
h
w
s
e
n
i
m
r
e
t
e
d
#
E
T
Y
B
.
h
g
i
H
s
i
.
n
o
i
t
a
r
e
p
o
#
T
E
S
E
R
t
u
p
n
I
.
w
o
L
e
v
i
t
c
a
,
t
e
s
e
R
e
r
a
w
d
r
a
H
e
h
t
g
n
i
t
t
e
s
e
r
f
o
d
o
h
t
e
m
e
r
a
w
d
r
a
h
a
s
e
d
i
v
o
r
P
y
l
e
t
a
i
d
e
m
m
i
t
i
,
t
e
s
e
r
s
i
e
c
i
v
e
d
e
h
t
n
e
h
W
.
e
t
a
t
s
y
a
r
r
a
d
a
e
r
e
h
t
o
t
0
0
4
F
9
2
Y
H
e
t
i
r
w
/
d
a
e
r
ll
a
d
n
a
d
e
t
a
t
s
-
i
r
t
s
i
s
u
b
a
t
a
d
e
h
T
.
s
s
e
r
g
o
r
p
n
i
n
o
i
t
a
r
e
p
o
y
n
a
s
e
t
a
n
i
m
r
e
t
,
d
e
t
r
e
s
s
a
s
i
#
T
E
S
E
R
e
li
h
W
.
d
e
t
r
e
s
s
a
s
i
t
u
p
n
i
e
h
t
e
li
h
w
d
e
r
o
n
g
i
e
r
a
s
d
n
a
m
m
o
c
.
e
d
o
m
y
b
d
n
a
t
S
e
h
t
n
i
e
b
ll
i
w
e
c
i
v
e
d
e
h
t
#
Y
B
/
Y
R
t
u
p
t
u
O
n
i
a
r
D
n
e
p
O
.
s
u
t
a
t
S
y
s
u
B
/
y
d
a
e
R
n
i
s
i
d
n
a
m
m
o
c
e
s
a
r
e
r
o
e
t
i
r
w
a
r
e
h
t
e
h
w
s
e
t
a
c
i
d
n
I
e
h
t
f
o
e
g
d
e
g
n
i
s
i
r
e
h
t
r
e
t
f
a
d
il
a
v
s
i
#
Y
B
/
Y
R
.
d
e
t
e
l
p
m
o
c
n
e
e
b
s
a
h
r
o
s
s
e
r
g
o
r
p
s
i
e
c
i
v
e
d
e
h
t
e
li
h
w
w
o
L
s
n
i
a
m
e
r
t
I
.
e
c
n
e
u
q
e
s
d
n
a
m
m
o
c
a
f
o
e
s
l
u
p
#
E
W
l
a
n
i
f
d
a
e
r
o
t
y
d
a
e
r
s
i
t
i
n
e
h
w
h
g
i
H
s
e
o
g
d
n
a
,
g
n
i
s
a
r
e
r
o
a
t
a
d
g
n
i
m
m
a
r
g
o
r
p
y
l
e
v
i
t
c
a
.
a
t
a
d
y
a
r
r
a
V
C
C
-
-
.
y
l
p
p
u
s
r
e
w
o
p
t
l
o
v
-
5
V
S
S
-
-
.
d
n
u
o
r
g
l
a
n
g
i
s
d
n
a
r
e
w
o
P
5
Rev. 5.2/May 01
HY29F400
MEMORY ARRAY ORGANIZATION
The 4 Mbit Flash memory array is organized into
11 blocks called sectors (S0, S1, . . . , S10). A
sector is the smallest unit that can be erased and
which can be protected to prevent accidental or
unauthorized erasure. See the `Bus Operations'
and `Command Definitions' sections of this docu-
ment for additional information on these functions.
In the HY29F400, four of the sectors, which com-
prise the boot block, vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining
seven sectors are uniformly sized at 64 Kbytes
(32 Kwords). The boot block can be located at
the bottom of the address range (HY29F400B) or
at the top of the address range (HY29F400T).
Table 1. HY29F400 Memory Array Organization
Notes:
1. X indicates Don't Care.
2. Address in Byte Mode is A[17:-1].
3. Address in Word Mode is A[17:0].
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
HY29F400T - Top Boot Block
HY29F400B - Bottom Boot Block
e
c
i
v
e
D
r
o
t
c
e
S
e
z
i
S
)
W
K
/
B
K
(
s
s
e
r
d
d
A
r
o
t
c
e
S
e
d
o
M
e
t
y
B
e
g
n
a
R
s
s
e
r
d
d
A
2
e
d
o
M
d
r
o
W
e
g
n
a
R
s
s
e
r
d
d
A
3
]
7
1
[
A
]
6
1
[
A
]
5
1
[
A
]
4
1
[
A
]
3
1
[
A
]
2
1
[
A
0
S
2
3
/
4
6
0
0
0
X
X
X
F
F
F
F
0
x
0
-
0
0
0
0
0
x
0
F
F
F
7
0
x
0
-
0
0
0
0
0
x
0
1
S
2
3
/
4
6
0
0
1
X
X
X
F
F
F
F
1
x
0
-
0
0
0
0
1
x
0
F
F
F
F
0
x
0
-
0
0
0
8
0
x
0
2
S
2
3
/
4
6
0
1
0
X
X
X
F
F
F
F
2
x
0
-
0
0
0
0
2
x
0
F
F
F
7
1
x
0
-
0
0
0
0
1
x
0
3
S
2
3
/
4
6
0
1
1
X
X
X
F
F
F
F
3
x
0
-
0
0
0
0
3
x
0
F
F
F
F
1
x
0
-
0
0
0
8
1
x
0
4
S
2
3
/
4
6
1
0
0
X
X
X
F
F
F
F
4
x
0
-
0
0
0
0
4
x
0
F
F
F
7
2
x
0
-
0
0
0
0
2
x
0
5
S
2
3
/
4
6
1
0
1
X
X
X
F
F
F
F
5
x
0
-
0
0
0
0
5
x
0
F
F
F
F
2
x
0
-
0
0
0
8
2
x
0
6
S
2
3
/
4
6
1
1
0
X
X
X
F
F
F
F
6
x
0
-
0
0
0
0
6
x
0
F
F
F
7
3
x
0
-
0
0
0
0
3
x
0
7
S
6
1
/
2
3
1
1
1
0
X
X
F
F
F
7
7
x
0
-
0
0
0
0
7
x
0
F
F
F
B
3
x
0
-
0
0
0
8
3
x
0
8
S
4
/
8
1
1
1
1
0
0
F
F
F
9
7
x
0
-
0
0
0
8
7
x
0
F
F
F
C
3
x
0
-
0
0
0
C
3
x
0
9
S
4
/
8
1
1
1
1
0
1
F
F
F
B
7
x
0
-
0
0
0
A
7
x
0
F
F
F
D
3
x
0
-
0
0
0
D
3
x
0
0
1
S
8
/
6
1
1
1
1
1
1
X
F
F
F
F
7
x
0
-
0
0
0
C
7
x
0
F
F
F
F
3
x
0
-
0
0
0
E
3
x
0
0
S
8
/
6
1
0
0
0
0
0
X
F
F
F
3
0
x
0
-
0
0
0
0
0
x
0
F
F
F
1
0
x
0
-
0
0
0
0
0
x
0
1
S
4
/
8
0
0
0
0
1
0
F
F
F
5
0
x
0
-
0
0
0
4
0
x
0
F
F
F
2
0
x
0
-
0
0
0
2
0
x
0
2
S
4
/
8
0
0
0
0
1
1
F
F
F
7
0
x
0
-
0
0
0
6
0
x
0
F
F
F
3
0
x
0
-
0
0
0
3
0
x
0
3
S
6
1
/
2
3
0
0
0
1
X
X
F
F
F
F
0
x
0
-
0
0
0
8
0
x
0
F
F
F
7
0
x
0
-
0
0
0
4
0
x
0
4
S
2
3
/
4
6
0
0
1
X
X
X
F
F
F
F
1
x
0
-
0
0
0
0
1
x
0
F
F
F
F
0
x
0
-
0
0
0
8
0
x
0
5
S
2
3
/
4
6
0
1
0
X
X
X
F
F
F
F
2
x
0
-
0
0
0
0
2
x
0
F
F
F
7
1
x
0
-
0
0
0
0
1
x
0
6
S
2
3
/
4
6
0
1
1
X
X
X
F
F
F
F
3
x
0
-
0
0
0
0
3
x
0
F
F
F
F
1
x
0
-
0
0
0
8
1
x
0
7
S
2
3
/
4
6
1
0
0
X
X
X
F
F
F
F
4
x
0
-
0
0
0
0
4
x
0
F
F
F
7
2
x
0
-
0
0
0
0
2
x
0
8
S
2
3
/
4
6
1
0
1
X
X
X
F
F
F
F
5
x
0
-
0
0
0
0
5
x
0
F
F
F
F
2
x
0
-
0
0
0
8
2
x
0
9
S
2
3
/
4
6
1
1
0
X
X
X
F
F
F
F
6
x
0
-
0
0
0
0
6
x
0
F
F
F
7
3
x
0
-
0
0
0
0
3
x
0
0
1
S
2
3
/
4
6
1
1
1
X
X
X
F
F
F
F
7
x
0
-
0
0
0
0
7
x
0
F
F
F
F
3
x
0
-
0
0
0
8
3
x
0
Table 1 defines the sector addresses and corre-
sponding address ranges for the top and bottom
boot block versions of the HY29F400.
6
Rev. 5.2/May 01
HY29F400
Table 2. HY29F400 Normal Bus Operations
1
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care, D
OUT
= Data Out, D
IN
= Data In. See DC Characteristics for voltage levels.
2. Address is A[17:-1] in Byte Mode and A[17:0] in Word Mode.
3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
the inputs and control levels they require, and the
resulting outputs. Certain bus operations require
a high voltage on one or more device pins. Those
are described in Table 3.
Read Operation
Data is read from the HY29F400 by using stan-
dard microprocessor read cycles while placing the
address of the byte or word to be read on the
device's address inputs, A[17:0] in Word mode
(BYTE# = H) or A[17:-1] in Byte mode (BYTE# =
L) . As shown in Table 2, the host system must
drive the CE# and OE# inputs Low and drive WE#
High for a valid read operation to take place. The
device outputs the specified array data on DQ[7:0]
in Byte mode and on DQ[15:0] in Word mode.
Note that DQ[15] serves as address input A[-1]
when the device is operating in Byte mode.
The HY29F400 is automatically set for reading
array data after device power-up and after a hard-
ware reset to ensure that no spurious alteration of
the memory content occurs during the power tran-
sition. No command is necessary in this mode to
obtain array data, and the device remains enabled
for read accesses until the command register con-
tents are altered.
This device features an Erase Suspend mode.
While in this mode, the host may read the array
data from any sector of memory that is not marked
for erasure. If the host attempts to read from an
address within an erase-suspended sector, or
while the device is performing an erase or byte/
n
o
i
t
a
r
e
p
O
#
E
C
#
E
O
#
E
W
#
T
E
S
E
R
s
s
e
r
d
d
A
2
]
0
:
7
[
Q
D
]
8
:
5
1
[
Q
D
3
H
=
#
E
T
Y
B
L
=
#
E
T
Y
B
d
a
e
R
L
L
H
H
A
N
I
D
T
U
O
D
T
U
O
Z
-
h
g
i
H
e
t
i
r
W
L
H
L
H
A
N
I
D
N
I
D
N
I
Z
-
h
g
i
H
e
l
b
a
s
i
D
t
u
p
t
u
O
L
H
H
H
X
Z
-
h
g
i
H
Z
-
h
g
i
H
Z
-
h
g
i
H
y
b
d
n
a
t
S
L
T
T
#
E
C
H
X
X
H
X
Z
-
h
g
i
H
Z
-
h
g
i
H
Z
-
h
g
i
H
y
b
d
n
a
t
S
S
O
M
C
#
E
C
V
C
C
V
5
.
0
X
X
V
C
C
V
5
.
0
X
Z
-
h
g
i
H
Z
-
h
g
i
H
Z
-
h
g
i
H
t
e
s
e
R
e
r
a
w
d
r
a
H
)
y
b
d
n
a
t
S
L
T
T
(
X
X
X
L
X
Z
-
h
g
i
H
Z
-
h
g
i
H
Z
-
h
g
i
H
t
e
s
e
R
e
r
a
w
d
r
a
H
)
y
b
d
n
a
t
S
S
O
M
C
(
X
X
X
V
S
S
V
5
.
0
X
Z
-
h
g
i
H
Z
-
h
g
i
H
Z
-
h
g
i
H
word program operation, the device outputs sta-
tus data instead of array data. After completing a
programming operation in the Erase Suspend
mode, the system may once again read array data
with the same exceptions noted above. After com-
pleting an internal program or internal erase algo-
rithm, the HY29F400 automatically returns to the
Read Array Data mode.
The host must issue a hardware reset or the soft-
ware reset command (see Command Definitions)
to return a sector to the read array data mode if
DQ[5] goes high during a program or erase cycle,
or to return the device to the Read Array Data
mode while it is in the Electronic ID mode.
Write Operation
Certain operations, including programming data
and erasing sectors of memory, require the host
to write a command or command sequence to the
HY29F400. Writes to the device are performed
by placing the byte or word address on the device's
address inputs while the data to be written is input
on DQ[7:0] in Byte mode (BYTE# = L) and on
DQ[15:0] in Word mode (BYTE# = H). The host
system must drive the CE# and WE# pins Low
and drive OE# High for a valid write operation to
take place. All addresses are latched on the fall-
ing edge of WE# or CE#, whichever happens later.
All data is latched on the rising edge of WE# or
CE#, whichever happens first.
7
Rev. 5.2/May 01
HY29F400
Table 3. HY29F400 Bus Operations Requiring High Voltage
1, 2
Notes:
1. L = V
IL
, H = V
IH
, X = Don't Care. See DC Characteristics for voltage levels.
2. Address bits not specified are Don't Care.
3. See text for additional information.
4. SA = sector address. See Table 1.
5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
The `Device Commands' section of this document
provides details on the specific device commands
implemented in the HY29F400.
Output Disable Operation
When the OE# input is at V
IH
, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F400, it can place the device in the
Standby mode. In this mode, current consump-
tion is greatly reduced, and the data bus outputs
are placed in the high impedance state, indepen-
dent of the OE# input. The Standby mode can be
invoked using two methods.
The device enters the CE# CMOS Standby mode
if the CE# and RESET# pins are both held at V
CC
0.5V. Note that this is a more restricted voltage
range than V
IH
. If both CE# and RESET# are held
High, but not within V
CC
0.5V, the device will be
in the CE# TTL Standby mode, but the standby
current will be greater.
The device enters the RESET# CMOS Standby
mode when the RESET# pin is held at V
SS
0.5V.
If RESET# is held Low but not within V
SS
0.5V,
the HY29F400 will be in the RESET# TTL Standby
mode, but the standby current will be greater. See
Hardware Reset Operation section for additional
information on the reset operation.
The device requires standard access time (t
CE
) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or pro-
gramming, it continues to draw active current until
the operation is completed.
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately termi-
nates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as-
sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation sec-
tion above.
n
o
i
t
a
r
e
p
O
3
#
E
C
#
E
O
#
E
W
#
T
E
S
E
R
]
2
1
:
7
1
[
A
]
9
[
A
]
6
[
A
]
1
[
A
]
0
[
A
]
0
:
7
[
Q
D
]
8
:
5
1
[
Q
D
#
E
T
Y
B
H
=
#
E
T
Y
B
L
=
5
t
c
e
t
o
r
P
r
o
t
c
e
S
L
V
D
I
X
H
A
S
4
V
D
I
X
X
X
X
X
Z
-
h
g
i
H
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
V
D
I
V
D
I
X
H
X
V
D
I
X
X
X
X
X
Z
-
h
g
i
H
r
o
t
c
e
S
y
r
a
r
o
p
m
e
T
t
c
e
t
o
r
p
n
U
X
X
X
V
D
I
X
X
X
X
X
D
N
I
D
N
I
Z
-
h
g
i
H
e
d
o
C
r
e
r
u
t
c
a
f
u
n
a
M
L
L
H
H
X
V
D
I
L
L
L
D
A
x
0
X
Z
-
h
g
i
H
e
c
i
v
e
D
e
d
o
C
B
0
0
4
F
9
2
Y
H
L
L
H
H
X
V
D
I
L
L
H
B
A
x
0
2
2
x
0
Z
-
h
g
i
H
T
0
0
4
F
9
2
Y
H
3
2
x
0
p
u
o
r
G
r
o
t
c
e
S
n
o
i
t
c
e
t
o
r
P
n
o
i
t
a
c
i
f
i
r
e
V
L
L
H
H
A
S
4
V
D
I
L
H
L
=
0
0
x
0
d
e
t
c
e
t
o
r
p
n
U
X
Z
-
h
g
i
H
=
1
0
x
0
d
e
t
c
e
t
o
r
P
8
Rev. 5.2/May 01
HY29F400
Figure 1. Sector Protect Procedure
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains Low (busy) until
the internal reset operation is complete, which re-
quires a time of t
READY
(during Automatic Algo-
rithms). The system can thus monitor RY/BY# to
determine when the reset operation completes,
and can perform a read or write operation t
RB
after
RY/BY# goes High. If RESET# is asserted when
a program or erase operation is not executing (RY/
BY# pin is High), the reset operation is completed
within a time of t
RP
. In this case, the host can per-
form a read or write operation t
RH
after the RE-
SET# pin returns High .
The RESET# pin may be tied to the system reset
signal. Thus, a system reset would also reset the
device, enabling the system to read the boot-up
firmware from the Flash memory.
Sector Protect/Unprotect Operations
Hardware sector protection can be invoked to dis-
able program and erase operations in any single
sector or combination of sectors. This function is
typically used to protect data in the device from
unauthorized or accidental attempts to program
or erase the device while it is in the system (e.g.,
by a virus) and is implemented using program-
ming equipment. Sector unprotection re-enables
the program and erase operations in previously
protected sectors.
Table 1 identifies the eleven sectors and the ad-
dress range that each covers for both versions of
the device. The device is shipped with all sectors
unprotected.
The sector protect/unprotect operations require a
high voltage (V
ID
) on address pin A[9] and the CE#
and/or OE# control pins, as detailed in Table 3.
When implementing these operations, note that
V
CC
must be applied to the device before applying
V
ID
, and that V
ID
should be removed before remov-
ing V
CC
from the device.
The flow chart in Figure 1 illustrates the proce-
dure for protecting sectors, and timing specifica-
tions and waveforms are shown in the specifica-
tions section of this document. Verification of pro-
tection is accomplished as described in the Elec-
tronic ID Mode section and shown in the flow chart.
START
S e t T R Y C N T = 1
Set A[9] = OE# = V
ID
Set Address:
A[17:12] = Sector to Protect
C E # = V
IL
R E S E T # = V
IH
W E # = V
IL
Wait t
W P P 1
A[9] = V
ID
A[17:12] = Sector to Protect
O E # = C E # = V
IL
A[6] = A[0] = V
IL
, A[1] = V
IH
R e a d D a t a
Data = 0x01?
Protect Another
Sector?
Y E S
T R Y C N T = 2 5 ?
N O
I n c r e m e n t T R Y C N T
N O
Y E S
DEVICE FAILURE
Y E S
N O
R e m o v e V
ID
from A[9]
S E C T O R P R O T E C T
C O M P L E T E
A P P L Y V
C C
W E # = V
IH
9
Rev. 5.2/May 01
HY29F400
The procedure for sector unprotection is illustrated
in the flow chart in Figure 2, and timing specifica-
tions and waveforms are given at the end of this
document. Note that to unprotect any sector, all
unprotected sectors must first be protected prior
to the first unprotect write cycle.
Sectors can also be temporarily unprotected as
described in the next section.
Temporary Sector Unprotect Operation
This feature allows temporary unprotection of pre-
viously protected sectors to allow changing the
data in-system. Temporary Sector Unprotect
mode is activated by setting the RESET# pin to
V
ID
. While in this mode, formerly protected sec-
tors can be programmed or erased by invoking
the appropriate commands (see Device Com-
mands section). Once V
ID
is removed from RE-
SET#, all the previously protected sectors are pro-
tected again. Figure 3 illustrates the algorithm.
START
NOTE: All sectors must be
previously protected.
Set: TRYCNT = 1
Set: A[9] = CE# = OE# = V
ID
Set: R E S E T # = V
IH
W E # = V
IL
Wait t
W P P 2
Set:
A[9] = V
ID
OE# = CE# = V
IL
Read Data
Data = 0x00?
NSEC = 10?
Y E S
T R Y C N T = 1 0 0 0 ?
N O
Increment TRYCNT
N O
Y E S
DEVICE FAILURE
N O
Y E S
R e m o v e V
ID
from A[9]
S E C T O R U N P R O T E C T
C O M P L E T E
A P P L Y V
C C
Set Sector Address:
A[17:12] = Sector NSEC
A[0] = A[6] = V
IL
A[1] = V
IH
N S E C = N S E C + 1
Set: NSEC = 0
W E # = V
IH
Figure 2. Sector Unprotect Procedure
START
R E S E T # = V
ID
(All protected sector groups
b e c o m e u n p r o t e c t e d )
P e r f o r m P r o g r a m o r E r a s e
O p e r a t i o n s
R E S E T # = V
IH
(All previously protected
sector groups return to
protected state)
TEMPORARY SECTOR
UNPROTECT COMPLETE
Figure 3. Temporary Sector Unprotect
10
Rev. 5.2/May 01
HY29F400
d
n
a
m
m
o
C
e
c
n
e
u
q
e
S
s
e
l
c
y
C
s
u
B
f
o
r
e
b
m
u
N
k
c
o
l
n
U
d
n
a
m
m
o
C
a
t
a
D
1
t
e
s
e
R
/
d
a
e
R
0
1
1
e
t
o
N
2
t
e
s
e
R
/
d
a
e
R
2
1
1
e
t
o
N
m
a
r
g
o
r
P
e
t
y
B
2
1
1
e
s
a
r
E
p
i
h
C
4
1
1
e
s
a
r
E
r
o
t
c
e
S
4
1
)
2
e
t
o
N
(
1
d
n
e
p
s
u
S
e
s
a
r
E
0
1
0
e
m
u
s
e
R
e
s
a
r
E
0
1
0
D
I
c
i
n
o
r
t
c
e
l
E
2
1
3
e
t
o
N
Notes:
1. Any number of Flash array read cycles are permitted.
2. Additional data cycles may follow. See text.
3. Any number of Electronic ID read cycles are permitted.
DEVICE COMMANDS
Device operations are initiated by writing desig-
nated address and data command sequences into
the device. A command sequence is composed
of one, two or three of the following sub-segments:
an unlock cycle, a command cycle and a data
cycle. Table 4 summarizes the composition of the
valid command sequences implemented in the
HY29F400, and these sequences are fully de-
scribed in Table 5 and in the sections that follow.
Writing incorrect address and data values or writ-
ing them in the improper sequence resets the
HY29F400 to the Read mode.
Read/Reset 1, 2 Commands
The HY29F400 automatically enters the Read
mode after device power-up, after the RESET#
input is asserted and upon the completion of cer-
tain commands. Read/Reset commands are not
required to retrieve data in these cases.
A Read/Reset command must be issued in order
to read array data in the following cases:
n
If the device is in the Electronic ID mode, a
Read/Reset command must be written to re-
turn to the Read mode. If the device was in the
Erase Suspend mode when the device entered
the Electronic ID mode, writing the Read/Re-
set command returns the device to the Erase
Suspend mode.
n
A read cycle at address 0xXXX01 returns the
device code:
- HY29F400T = 0x23 in Byte mode, 0x2223 in
Word mode.
- HY29F400B = 0xAB in Byte mode, 0x22AB
in Word mode.
n
A read cycle containing a sector address (Table
1) in A[17:12] and the address 0x02 in A[7:0]
returns 0x01 if that sector is protected, or 0x00
if it is unprotected.
Table 4. Composition of Command Sequences
Note: When in the Electronic ID bus operation mode,
the device returns to the Read mode when V
ID
is re-
moved from the A[9] pin. The Read/Reset command is
not required in this case.
n
If DQ[5] (Exceeded Time Limit) goes High dur-
ing a program or erase operation, writing the
Read/Reset command returns the sectors to
the Read mode (or to the Erase Suspend mode
if the device was in Erase Suspend).
The Read/Reset command may also be used to
abort certain command sequences:
Electronic ID Mode Operation
The Electronic ID mode provides manufacturer and
device identification and sector protection verifi-
cation through identifier codes output on DQ[7:0]
or DQ[15:0]. This mode is intended primarily for
programming equipment to automatically match
a device to be programmed with its correspond-
ing programming algorithm. The Electronic ID in-
formation can also be obtained by the host through
a command sequence, as described in the De-
vice Commands section.
Operation in the Electronic ID mode requires V
ID
on address pin A[9], with additional requirements
for obtaining specific data items as listed in Table
2:
n
A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
11
Rev. 5.2/May 01
HY29F400
Table 5. HY29F400 Command Sequences
Legend:
X = Don
'
t Care
PA = Address of the data to be programmed
RA = Memory address of data to be read
PD = Data to be programmed at address PA
RD = Data read from location RA during the read operation
SA = Sector address of sector to be erased or verified (see Note 3 and
Table 1).
STATUS = Sector protect status: 0x00 = unprotected, 0x01 = protected.
Notes:
1.
All values are in hexadecimal. DQ[15:8] are don
'
t care for unlock and command cycles.
2.
All bus cycles are write operations unless otherwise noted.
3.
Address is A[10:0] in Word mode and A[10:-1] in Byte mode. A[17:11] are don
'
t care except as follows:
For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.
For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased.
For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified.
4.
The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sect
ors, or enter the
Electronic ID mode, while in the Erase Suspend mode.
5.
The Erase Resume command is valid only during the Erase Suspend mode.
6.
The second bus cycle is a read cycle.
7.
The fourth bus cycle is a read cycle.
8.
Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electron
ic ID command mode or if
DQ[5] goes High during a program or erase operation. It is not required for normal read operations.
Electronic ID
7
s
e
l
c
y
C
s
u
B
3
,
2
,
1
e
c
n
e
u
q
e
S
d
n
a
m
m
o
C
e
t
i
r
W
s
e
l
c
y
C
t
s
r
i
F
d
n
o
c
e
S
d
r
i
h
T
h
t
r
u
o
F
h
t
f
i
F
h
t
x
i
S
d
d
A
a
t
a
D
d
d
A
a
t
a
D
d
d
A
a
t
a
D
d
d
A
a
t
a
D
d
d
A
a
t
a
D
d
d
A
a
t
a
D
1
t
e
s
e
R
/
d
a
e
R
8
,
6
1X
X
X0
FA
RD
R
2
t
e
s
e
R
/
t
e
s
e
R
8
,
7
d
r
o
W
3
5
5
5
A
A
A
A
2
5
5
5
5
5
0
FA
RD
R
e
t
y
BA
A
A5
5
5A
A
A
m
a
r
g
o
r
P
d
r
o
W
4
5
5
5
A
A
A
A
2
5
5
5
5
5
0
AA
PD
P
e
t
y
BA
A
A5
5
5A
A
A
e
s
a
r
E
p
i
h
C
d
r
o
W
6
5
5
5
A
A
A
A
2
5
5
5
5
5
0
8
5
5
5
A
A
A
A
2
5
5
5
5
5
0
1
e
t
y
BA
A
A5
5
5A
A
AA
A
A5
5
5A
A
A
e
s
a
r
E
r
o
t
c
e
S
d
r
o
W
6
5
5
5
A
A
A
A
2
5
5
5
5
5
0
8
5
5
5
A
A
A
A
2
5
5A
S0
3
e
t
y
BA
A
A5
5
5A
A
AA
A
A5
5
5
d
n
e
p
s
u
S
e
s
a
r
E
4
1X
X
X0
B
e
m
u
s
e
R
e
s
a
r
E
5
1X
X
X0
3
e
d
o
C
r
e
r
u
t
c
a
f
u
n
a
M
d
r
o
W
3
5
5
5
A
A
A
A
2
5
5
5
5
5
0
90
0
XD
A
e
t
y
BA
A
A5
5
5A
A
A
e
d
o
C
e
c
i
v
e
D
d
r
o
W
3
5
5
5
A
A
A
A
2
5
5
5
5
5
0
9
1
0
X)
t
o
o
B
m
o
t
t
o
B
(
B
A
2
2
,
)
t
o
o
B
p
o
T
(
3
2
2
2
e
t
y
BA
A
A5
5
5A
A
A2
0
X)
t
o
o
B
m
o
t
t
o
B
(
B
A
,
)
t
o
o
B
p
o
T
(
3
2
y
f
i
r
e
V
t
c
e
t
o
r
P
r
o
t
c
e
S
d
r
o
W
3
5
5
5
A
A
A
A
2
5
5
5
5
5
0
9
2
0
X
)
A
S
(
S
U
T
A
T
S
e
t
y
BA
A
A5
5
5A
A
A
4
0
X
)
A
S
(
12
Rev. 5.2/May 01
HY29F400
sure data integrity, the aborted program command
sequence should be reinitiated once the reset
operation is complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored "0" to a "1".
Thus, a bit cannot be programmed from a "0" back
to a "1". Attempting to do so will set DQ[5] to "1",
and the Data# Polling algorithm will indicate that
the operation was not successful. A Read/Reset
command or a hardware reset is required to exit
this state, and a succeeding read will show that
the data is still "0".
Figure 4 illustrates the procedure for the Byte/Word
Program operation.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
chip erase data cycle. During chip erase, all sec-
tors of the device are erased except protected
sectors. The command sequence starts the Au-
tomatic Erase algorithm, which preprograms
and verifies the entire memory, except for pro-
tected sectors, for an all zero data pattern prior to
electrical erase. The device then provides the
required number of internally generated erase
pulses and verifies cell erasure within the proper
cell margins. The host system is not required to
START
I s s u e P R O G R A M
C o m m a n d S e q u e n c e :
Last cycle contains
p r o g r a m A d d r e s s / D a t a
C h e c k P r o g r a m m i n g S t a t u s
(See Write Operation Status
Section)
Last Word/Byte
D o n e ?
Y E S
N O
P R O G R A M M I N G
C O M P L E T E
GO TO
E R R O R R E C O V E R Y
DQ[5] Error Exit
Normal Exit
Figure 4. Programming Procedure
n
In a Sector Erase or Chip Erase command se-
quence, the Read/Reset command may be
written at any time before erasing actually be-
gins, including, for the Sector Erase command,
between the cycles that specify the sectors to
be erased (see Sector Erase command de-
scription). This aborts the command and re-
sets the device to the Read mode. Once era-
sure begins, however, the device ignores Read/
Reset commands until the operation is com-
plete.
n
In a Program command sequence, the Read/
Reset command may be written between the
sequence cycles before programming actually
begins. This aborts the command and resets
the device to the Read mode, or to the Erase
Suspend mode if the Program command se-
quence is written while the device is in the
Erase Suspend mode. Once programming
begins, however, the device ignores Read/
Reset commands until the operation is com-
plete.
n
The Read/Reset command may be written be-
tween the cycles in an Electronic ID command
sequence to abort that command. As described
above, once in the Electronic ID mode, the
Read/Reset command must be written to re-
turn to the Read mode.
Byte/Word Program Command
The host processor programs the device a byte or
word at a time by issuing the Program command
sequence shown in Table 5. The sequence be-
gins by writing two unlock cycles, followed by the
Program setup command and, lastly, a data cycle
specifying the program address and data. This
initiates the Automatic Programming algorithm,
which provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further con-
trols or timings during this operation. When the
Automatic Programming algorithm is complete, the
device returns to the Read mode. Several meth-
ods are provided to allow the host to determine
the status of the programming operation, as de-
scribed in the Write Operation Status section.
Commands written to the device during execution
of the Automatic Programming algorithm are ig-
nored. Note that a hardware reset immediately
terminates the programming operation. To en-
13
Rev. 5.2/May 01
HY29F400
provide any controls or timings during these op-
erations.
Commands written to the device during execution
of the Automatic Erase algorithm are ignored. Note
that a hardware reset immediately terminates the
erase operation. To ensure data integrity, the
aborted Chip Erase command sequence should
be reissued once the reset operation is complete.
When the Automatic Erase algorithm is finished,
the device returns to the Read mode. Several
methods are provided to allow the host to deter-
mine the status of the erase operation, as de-
scribed in the Write Operation Status section.
Figure 5 illustrates the Chip Erase procedure.
Sector Erase Command
The Sector Erase command sequence consists
of two unlock cycles, followed by the erase com-
mand, two additional unlock cycles and then the
sector erase data cycle, which specifies which
sector is to be erased. As described later in this
section, multiple sectors can be specified for era-
sure with a single command sequence. During
sector erase, all specified sectors are erased se-
quentially. The data in sectors not specified for
erasure, as well as the data in any protected secto-
rs, even if specified for erasure, is not affect-
ed by the sector erase operation.
The Sector Erase command sequence starts the
Automatic Erase algorithm, which preprograms
and verifies the specified unprotected sectors for
an all zero data pattern prior to electrical erase.
The device then provides the required number of
Figure 5. Chip Erase Procedure
START
I s s u e C H I P E R A S E
C o m m a n d S e q u e n c e
Check Erase Status
(See Write Operation Status
Section)
CHIP ERASE COMPLETE
GO TO
E R R O R R E C O V E R Y
DQ[5] Error Exit
Normal Exit
internally generated erase pulses and verifies cell
erasure within the proper cell margins. The host
system is not required to provide any controls or
timings during these operations.
After the sector erase data cycle (the sixth bus
cycle) of the command sequence is issued, a sec-
tor erase time-out of 50 s, measured from the
rising edge of the final WE# pulse in that bus cycle,
begins. During this time, an additional sector erase
data cycle, specifying the sector address of an-
other sector to be erased, may be written into an
internal sector erase buffer. This buffer may be
loaded in any sequence, and the number of sec-
tors specified may be from one sector to all sec-
tors. The only restriction is that the time between
these additional data cycles must be less than 50
s, otherwise erasure may begin before the last
data cycle is accepted. To ensure that all data
cycles are accepted, it is recommended that host
processor interrupts be disabled during the time
that the additional cycles are being issued and then
be re-enabled afterwards.
Note: The device is capable of accepting three ways
of invoking Erase Commands for additional sectors
during the time-out window. The preferred method,
described above, is the sector erase data cycle after
the initial six bus cycle command sequence. However,
the device also accepts the following methods of
specifying additional sectors during the sector erase
time-out:
n
Repeat the entire six-cycle command sequence,
specifying the additional sector in the sixth cycle.
n
Repeat the last three cycles of the six-cycle command
sequence, specifying the additional sector in the third
cycle.
If all sectors scheduled for erasing are protected,
the device returns to reading array data after ap-
proximately 100 s. If at least one scheduled sec-
tor is not protected, the erase operation erases
the unprotected sectors, and ignores the command
for the scheduled sectors that are protected.
The system can monitor DQ[3] to determine if the
50 s sector erase time-out has expired, as de-
scribed in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the time-
out, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
14
Rev. 5.2/May 01
HY29F400
START
YES
Erase An
Additional Sector?
Check Erase Status
(See Write Operation Status
Section)
Setup First (or Next) Sector
Address for Erase Operation
ERASE COMPLETE
Write First Five Cycles of
S E C T O R E R A S E
Command Sequence
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Sector Erase
Time-out (DQ[3])
Expired?
N O
YES
N O
GO TO
E R R O R R E C O V E R Y
DQ[5] Error Exit
Normal Exit
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
Figure 6. Sector Erase Procedure
additional sector erase data cycles. Once the sec-
tor erase operation itself has begun, only the Erase
Suspend command is valid. All other commands
are ignored.
As for the Chip Erase command, note that a hard-
ware reset immediately terminates the erase op-
eration. To ensure data integrity, the aborted Sec-
tor Erase command sequence should be reissued
once the reset operation is complete.
When the Automatic Erase algorithm terminates,
the device returns to the Read mode. Several
methods are provided to allow the host to deter-
mine the status of the erase operation, as de-
scribed in the Write Operation Status section.
Figure 6 illustrates the Sector Erase procedure.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system
to interrupt a sector erase operation to read data
from, or program data to, any sector not being
erased. The command causes the erase opera-
tion to be suspended in all sectors selected for
erasure. This command is valid only during the
sector erase operation, including during the 50 s
time-out period at the end of the initial command
sequence and any subsequent sector erase data
cycles, and is ignored if it is issued during chip
erase or programming operations.
The HY29F400 requires a maximum of 20 s to
suspend the erase operation if the Erase Suspend
command is issued during active sector erasure.
However, if the command is written during the time-
out, the time-out is terminated and the erase op-
eration is suspended immediately. Any subse-
quent attempts to specify additional sectors for
erasure by writing the sector erase data cycle (SA/
0x30) will be interpreted as the Erase Resume
command (XXX/0x30), which will cause the Auto-
matic Erase algorithm to begin its operation. Note
that any other command during the time-out will
reset the device to the Read mode.
Once the erase operation has been suspended,
the system can read array data from or program
data to any sector not selected for erasure. Nor-
mal read and write timings and command defini-
tions apply. Reading at any address within erase-
suspended sectors produces status data on
DQ[7:0]. The host can use DQ[7], or DQ[6] and
DQ[2] together, to determine if a sector is actively
erasing or is erase-suspended. See "Write Op-
eration Status" for information on these status bits.
15
Rev. 5.2/May 01
HY29F400
After an erase-suspended program operation is
complete, the host can initiate another program-
ming operation (or read operation) within non-sus-
pended sectors. The host can determine the sta-
tus of a program operation during the erase-sus-
pended state just as in the standard programming
operation.
The system must write the Erase Resume com-
mand to exit the Erase Suspend mode and con-
tinue the sector erase operation. Further writes of
the Resume command are ignored. Another Erase
Suspend command can be written after the de-
vice has resumed erasing.
The host may also write the Electronic ID com-
mand sequence when the device is in the Erase
Suspend mode. The device allows reading Elec-
tronic ID codes even if the addresses used for the
ID read cycles are within erasing sectors, since
the codes are not stored in the memory array.
When the device exits the Electronic ID mode, the
device reverts to the Erase Suspend mode, and
is ready for another valid operation. See Electronic
ID section for more information.
Electronic ID Command
The Electronic ID operation intended for use in
programming equipment has been described pre-
viously. The host processor can also be obtain
the same data by using the Electronic ID com-
mand sequence shown in Table 5. This method
does not require V
ID
on any pin. The Electronic ID
command sequence may be invoked while the
device is in the Read mode or the Erase Suspend
mode, but is invalid while the device is actively
programming or erasing.
The Electronic ID command sequence is initiated
by writing two unlock cycles, followed by the Elec-
tronic ID command. The device then enters the
Electronic ID mode, and:
n
A read cycle at address 0xXXX00 retrieves the
manufacturer code (Hynix = 0xAD).
n
In Word mode, a read cycle at address
0xXXX01 returns the device code (HY29F400T
= 0x2223, HY29F400B = 0x22AB). In Byte
mode, the same information is retrieved from
address 0xXXX02 (HY29F400T = 0x23,
HY29F400B = 0xAB).
n
In Word mode, a read cycle containing a sec-
tor address in A[17:12] and the address 0x02
in A[7:0] returns 0xXX01 if that sector is pro-
tected, or 0xXX00 if it is unprotected. In Byte
mode, the status information is retrieved using
0x04 in A[6:-1] (0x01 if the sector is protected,
0x00 if the sector is unprotected).
The host system may read at any address any
number of times, without initiating another com-
mand sequence. Thus, for example, the host may
determine the protection status for all sectors by
doing successive reads at the address specified
above while changing the sector address for each
cycle.
The system must write the Reset command to exit
the Electronic ID mode and return to the Read
mode, or to the Erase Suspend mode if the de-
vice was in that mode when the command se-
quence was issued.
WRITE OPERATION STATUS
The HY29F400 provides a number of facilities to
determine the status of a program or erase op-
eration. These are the RY/BY# (Ready/Busy#)
pin and certain bits of a status word which can be
read from the device during the programming and
erase operations. Table 6 summarizes the status
indications and further detail is provided in the
subsections which follow.
RY/BY# - Ready/Busy#
RY/BY# is an open-drain output pin that indicates
whether a programming or erase Automatic Algo-
rithm is in progress or has completed. A pull-up
resistor to V
CC
is required for proper operation. RY/
BY# is valid after the rising edge of the final WE#
pulse in the corresponding command sequence.
If the output is Low (busy), the device is actively
erasing or programming, including programming
while in the Erase Suspend mode. If the output is
High (ready), the device has completed the op-
eration and is ready to read array data in the nor-
mal or Erase Suspend modes, or it is in the standby
mode.
DQ[7] - Data# Polling
The Data# ("Data Bar") Polling bit, DQ[7], indicates
to the host system whether an Automatic Algo-
16
Rev. 5.2/May 01
HY29F400
Table 6. Write and Erase Operation Status Summary
Notes:
1. A valid address is required when reading status information. See text for additional information.
2. DQ[5] status switches to a `1' when a program or erase operation exceeds the maximum timing limit.
3. A `1' during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. DQ[3] is not
applicable to the chip erase operation.
4. Equivalent to `No Toggle' because data is obtained in this state.
5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
rithm is in progress or completed, or whether the
device is in Erase Suspend mode. Data# Polling
is valid after the rising edge of the final WE# pulse
in the Program or Erase command sequence.
The system must do a read at the program ad-
dress to obtain valid programming status informa-
tion on this bit. While a programming operation is
in progress, the device outputs the complement
of the value programmed to DQ[7]. When the pro-
gramming operation is complete, the device out-
puts the value programmed to DQ[7]. If a pro-
gram operation is attempted within a protected
sector, Data# Polling on DQ[7] is active for ap-
proximately 2 s, then the device returns to read-
ing array data.
The host must read at an address within any non-
protected sector scheduled for erasure to obtain
valid erase status information on DQ[7]. During
an erase operation, Data# Polling produces a "0"
on DQ[7]. When the erase operation is complete,
or if the device enters the Erase Suspend mode,
Data# Polling produces a "1" on DQ[7]. If all sec-
tors selected for erasing are protected, Data#
Polling on DQ[7] is active for approximately 100
s, then the device returns to reading array data.
If at least one selected sector is not protected, the
erase operation erases the unprotected sectors,
and ignores the command for the selected sec-
tors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or "0" to "1" for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 7 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be
read at any address, and is valid after the rising
edge of the final WE# pulse in the program or erase
command sequence, including during the sector
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately 2 s after the program command
sequence is written, then returns to reading array
data.
e
d
o
M
n
o
i
t
a
r
e
p
O
]
7
[
Q
D
1
]
6
[
Q
D
]
5
[
Q
D
]
3
[
Q
D
]
2
[
Q
D
1
#
Y
B
/
Y
R
l
a
m
r
o
N
s
s
e
r
g
o
r
p
n
i
g
n
i
m
m
a
r
g
o
r
P
#
]
7
[
Q
D
e
l
g
g
o
T
1
/
0
2
A
/
N
A
/
N
0
d
e
t
e
l
p
m
o
c
g
n
i
m
m
a
r
g
o
r
P
a
t
a
D
a
t
a
D
4
a
t
a
D
a
t
a
D
a
t
a
D
1
s
s
e
r
g
o
r
p
n
i
e
s
a
r
E
0
e
l
g
g
o
T
1
/
0
2
1
3
e
l
g
g
o
T
0
d
e
t
e
l
p
m
o
c
e
s
a
r
E
1
a
t
a
D
4
a
t
a
D
a
t
a
D
a
t
a
D
4
1
e
s
a
r
E
d
n
e
p
s
u
S
d
e
d
n
e
p
s
u
s
e
s
a
r
e
n
i
h
t
i
w
d
a
e
R
r
o
t
c
e
s
1
e
l
g
g
o
t
o
N
0
A
/
N
e
l
g
g
o
T
1
e
s
a
r
e
-
n
o
n
n
i
h
t
i
w
d
a
e
R
r
o
t
c
e
s
d
e
d
n
e
p
s
u
s
a
t
a
D
a
t
a
D
a
t
a
D
a
t
a
D
a
t
a
D
1
s
s
e
r
g
o
r
p
n
i
g
n
i
m
m
a
r
g
o
r
P
5
#
]
7
[
Q
D
e
l
g
g
o
T
1
/
0
2
A
/
N
A
/
N
0
d
e
t
e
l
p
m
o
c
g
n
i
m
m
a
r
g
o
r
P
5
a
t
a
D
a
t
a
D
4
a
t
a
D
a
t
a
D
a
t
a
D
1
17
Rev. 5.2/May 01
HY29F400
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors se-
lected for erasing are protected, DQ[6] toggles for
approximately 100 s, then returns to reading ar-
ray data. If at least one selected sector is not
protected, the Automatic Erase algorithm erases
the unprotected sectors, and ignores the selected
sectors that are protected.
Note: In the current version of the device, unreliable
testing of DQ[6] for erase completion may occur if the
test is done before the Sector Erase Timer (DQ[3]) has
expired. It is recommended that for erase operations
the DQ[6] test be delayed for a minimum of 100 s or
until after DQ[3] switches from a `0' to a `1'. This anomaly
will be corrected in a future revision of the device.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indi-
cates whether a particular sector is actively eras-
ing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
DQ[2] toggles when the host reads at addresses
within sectors that have been selected for erasure,
but cannot distinguish whether the sector is ac-
tively erasing or is erase-suspended. DQ[6], by
comparison, indicates whether the device is ac-
tively erasing or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and
mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
DQ[5] - Exceeded Timing Limits
DQ[5] is set to a `1' when the program or erase
time has exceeded a specified internal pulse count
limit. This is a failure condition that indicates that
the program or erase cycle was not successfully
completed. DQ[5] status is valid only while DQ[7]
or DQ[6] indicate that the Automatic Algorithm is
in progress.
The DQ[5] failure condition will also be signaled if
the host tries to program a `1' to a location that is
previously programmed to `0', since only an erase
operation can change a `0' to a `1'.
For both of these conditions, the host must issue
a Read/Reset command to return the device to
the Read mode.
DQ[3] - Sector Erase Timer
After writing a Sector Erase command sequence,
the host may read DQ[3] to determine whether or
not an erase operation has begun. When the
sector erase time-out expires and the sector erase
operation commences, DQ[3] switches from a `0'
to a `1'. Refer to the "Sector Erase Command"
section for additional information. Note that the
START
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
N O
YES
PROGRAM/ERASE
COMPLETE
DQ[5] = 1?
N O
YES
Test for DQ[7] = 1?
for Erase Operation
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
(Note 2)
N O
YES
Test for DQ[7] = 1?
for Erase Operation
PROGRAM/ERASE
EXCEEDED TIME ERROR
Notes:
1. During programming, the program address.
During sector erase, an address within any non-protected sector
scheduled for erasure.
During chip erase, an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously at the same time
as DQ[5].
Figure 7. Data# Polling Test Algorithm
18
Rev. 5.2/May 01
HY29F400
HARDWARE DATA PROTECTION
The HY29F400 provides several methods of pro-
tection to prevent accidental erasure or program-
ming which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
These methods are described in the sections that
follow.
Command Sequences
Commands that may alter array data require a
sequence of cycles as described in Table 5. This
provides data protection against inadvertent writes.
Low V
CC
Write Inhibit
To protect data during V
CC
power-up and power-
down, the device does not accept write cycles
when V
CC
is less than V
LKO
(typically 3.7 volts). The
command register and all internal program/erase
circuits are disabled, and the device resets to the
Read mode. Writes are ignored until V
CC
is greater
than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional
writes when V
CC
is greater than V
LKO
.
sector erase timer does not apply to the Chip Erase
command.
After the initial Sector Erase command sequence
is issued, the system should read the status on
DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to
ensure that the device has accepted the command
sequence, and then read DQ[3]. If DQ[3] is a `1',
the internally controlled erase cycle has begun and
all further sector erase data cycles or commands
Read DQ[7:0]
at Valid Address (Note 1)
DQ[6] Toggled?
N O
(Note 3)
Y E S
PROGRAM/ERASE
C O M P L E T E
DQ[5] = 1?
N O
Y E S
Read DQ[7:0]
at Valid Address (Note 1)
DQ[6] Toggled?
(Note 2)
N O
Y E S
PROGRAM/ERASE
EXCEEDED TIME ERROR
Notes:
1. During programming, the program address.
During sector erase, an address within any sector scheduled for erasure.
2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1.
3. Use this path if testing for Program/Erase status.
4. Use this path to test whether sector is in Erase Suspend mode.
Read DQ[7:0]
at Valid Address (Note 1)
START
Read DQ[7:0]
DQ[2] Toggled?
N O
SECTOR BEING READ
IS IN ERASE SUSPEND
Read DQ[7:0]
Y E S
N O
(Note 4)
SECTOR BEING READ
IS NOT IN ERASE SUSPEND
Figure 8. Toggle Bit I and II Test Algorithm
(other than Erase Suspend) are ignored until the
erase operation is complete. If DQ[3] is a `0', the
device will accept a sector erase data cycle to mark
an additional sector for erasure. To ensure that
the data cycles have been accepted, the system
software should check the status of DQ[3] prior to
and following each subsequent sector erase data
cycle. If DQ[3] is high on the second status check,
the last data cycle might not have been accepted.
19
Rev. 5.2/May 01
HY29F400
Write Pulse "Glitch" Protection
Noise pulses of less than 5 ns (typical) on OE#,
CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by asserting any one of
the following conditions: OE# = V
IL
, CE# = V
IH
, or
WE# = V
IH
. To initiate a write cycle, CE# and WE#
must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power
up, the device does not accept commands on the
rising edge of WE#. The internal state machine is
automatically reset to the Read mode on power-
up.
Sector Protection
Additional data protection is provided by the
HY29F400's sector protect feature, described pre-
viously, which can be used to protect sensitive
areas of the Flash array from accidental or unau-
thorized attempts to alter the data.
20
Rev. 5.2/May 01
HY29F400
ABSOLUTE MAXIMUM RATINGS
4
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
e
u
l
a
V
t
i
n
U
T
G
T
S
e
r
u
t
a
r
e
p
m
e
T
e
g
a
r
o
t
S
5
2
1
+
o
t
5
6
-
C
T
S
A
I
B
d
e
il
p
p
A
r
e
w
o
P
h
t
i
w
e
r
u
t
a
r
e
p
m
e
T
t
n
e
i
b
m
A
5
2
1
+
o
t
5
5
-
C
V
2
N
I
V
o
t
t
c
e
p
s
e
R
h
t
i
w
n
i
P
n
o
e
g
a
t
l
o
V
S
S
:
V
C
C
1
#
T
E
S
E
R
,
#
E
O
,
]
9
[
A
2
s
n
i
P
r
e
h
t
O
ll
A
1
0
.
7
+
o
t
0
.
2
-
5
.
2
1
+
o
t
0
.
2
-
0
.
7
+
o
t
0
.
2
-
V
V
V
I
S
O
t
n
e
r
r
u
C
t
i
u
c
r
i
C
t
r
o
h
S
t
u
p
t
u
O
3
0
0
2
A
m
Notes:
1. Minimum DC voltage on input or I/O pins is 0.5 V. During voltage transitions, input or I/O pins may undershoot V
SS
to
-2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is V
CC
+ 0.5 V. During voltage
transitions, input or I/O pins may overshoot to V
CC
+2.0 V for periods up to 20 ns. See Figure 10.
2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET#
may undershoot V
SS
to 2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5
V which may overshoot to 13.5 V for periods up to 20 ns.
3. No more than one output at a time may be shorted to V
SS
. Duration of the short circuit should be less than one second.
4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions above those indicated in the
operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
1
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
e
u
l
a
V
t
i
n
U
T
A
e
r
u
t
a
r
e
p
m
e
T
g
n
i
t
a
r
e
p
O
t
n
e
i
b
m
A
0
7
+
o
t
0
C
V
C
C
:
e
g
a
t
l
o
V
y
l
p
p
u
S
g
n
i
t
a
r
e
p
O
s
n
o
i
s
r
e
V
5
4
-
s
n
o
i
s
r
e
V
r
e
h
t
O
ll
A
5
2
.
5
+
o
t
5
7
.
4
+
0
5
.
5
+
o
t
0
5
.
4
+
V
V
Notes:
1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
2.0 V
V
C C
+ 0.5 V
V
C C
+ 2.0 V
20 ns
20 ns
20 ns
Figure 9. Maximum Undershoot Waveform
Figure 10. Maximum Overshoot Waveform
0.8 V
- 0.5 V
- 2.0 V
20 ns
20 ns
20 ns
21
Rev. 5.2/May 01
HY29F400
DC CHARACTERISTICS
TTL/NMOS Compatible
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
p
u
t
e
S
t
s
e
T
n
i
M
p
y
T
x
a
M
t
i
n
U
I
I
L
t
n
e
r
r
u
C
d
a
o
L
t
u
p
n
I
V
N
I
V
=
S
S
V
o
t
C
C
,
V
C
C
V
=
C
C
x
a
M
0
.
1
A
I
T
I
L
t
n
e
r
r
u
C
d
a
o
L
t
u
p
n
I
#
T
E
S
E
R
,
#
E
O
,
]
9
[
A
V
C
C
V
=
C
C
=
]
9
[
A
;
x
a
M
V
5
.
2
1
=
#
T
E
S
E
R
=
#
E
O
0
5
A
I
O
L
t
n
e
r
r
u
C
e
g
a
k
a
e
L
t
u
p
t
u
O
V
T
U
O
V
=
S
S
V
o
t
C
C
,
V
C
C
V
=
C
C
x
a
M
0
.
1
A
I
1
C
C
V
C
C
t
n
e
r
r
u
C
d
a
e
R
e
v
i
t
c
A
2
,
1
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
,
e
d
o
M
e
t
y
B
,
z
H
M
5
=
f
9
1
0
4
A
m
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
,
e
d
o
M
d
r
o
W
,
z
H
M
5
=
f
9
1
0
5
A
m
I
2
C
C
V
C
C
t
n
e
r
r
u
C
e
t
i
r
W
e
v
i
t
c
A
4
,
3
,
2
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
6
3
0
6
A
m
I
3
C
C
V
C
C
d
e
ll
o
r
t
n
o
C
#
E
C
t
n
e
r
r
u
C
y
b
d
n
a
t
S
L
T
T
2
#
T
E
S
E
R
=
#
E
C
=
#
E
O
V
=
H
I
4
.
0
0
.
1
A
m
I
4
C
C
V
C
C
d
e
ll
o
r
t
n
o
C
#
T
E
S
E
R
t
n
e
r
r
u
C
y
b
d
n
a
t
S
L
T
T
2
V
=
#
T
E
S
E
R
L
I
4
.
0
0
.
1
A
m
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
5
.
0
-
8
.
0
V
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
0
.
2
V
C
C
5
.
0
+
V
V
D
I
d
n
a
D
I
c
i
n
o
r
t
c
e
l
E
r
o
f
e
g
a
t
l
o
V
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
y
r
a
r
o
p
m
e
T
V
C
C
V
0
.
5
=
5
.
1
1
5
.
2
1
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
C
C
V
=
C
C
,
n
i
M
I
L
O
A
m
8
.
5
=
5
4
.
0
V
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
C
C
V
=
C
C
,
n
i
M
I
H
O
A
m
5
.
2
-
=
4
.
2
V
V
O
K
L
V
w
o
L
C
C
e
g
a
t
l
o
V
t
u
o
k
c
o
L
4
2
.
3
2
.
4
V
Notes:
1. The I
CC
current is listed is typically less than 2 mA/MHz with OE# at V
IH
.
2. Maximum I
CC
specifications are tested with V
CC
= V
CC
Max.
3. I
CC
active while the Automatic Erase or Automatic Program algorithm is in progress.
4. Not 100% tested.
22
Rev. 5.2/May 01
HY29F400
DC CHARACTERISTICS
CMOS Compatible
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
p
u
t
e
S
t
s
e
T
n
i
M
p
y
T
x
a
M
t
i
n
U
I
I
L
t
n
e
r
r
u
C
d
a
o
L
t
u
p
n
I
V
N
I
V
=
S
S
V
o
t
C
C
,
V
C
C
V
=
C
C
x
a
M
0
.
1
A
I
T
I
L
t
n
e
r
r
u
C
d
a
o
L
t
u
p
n
I
#
T
E
S
E
R
,
#
E
O
,
]
9
[
A
V
C
C
V
=
C
C
=
]
9
[
A
,
x
a
M
V
5
.
2
1
=
#
T
E
S
E
R
=
#
E
O
0
5
A
I
O
L
t
n
e
r
r
u
C
e
g
a
k
a
e
L
t
u
p
t
u
O
V
T
U
O
V
=
S
S
V
o
t
C
C
,
V
C
C
V
=
C
C
x
a
M
0
.
1
A
I
1
C
C
V
C
C
t
n
e
r
r
u
C
d
a
e
R
e
v
i
t
c
A
2
,
1
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
,
e
d
o
M
e
t
y
B
,
z
H
M
5
=
f
0
2
0
4
A
m
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
,
e
d
o
M
d
r
o
W
,
z
H
M
5
=
f
8
2
0
5
A
m
I
2
C
C
V
C
C
t
n
e
r
r
u
C
e
t
i
r
W
e
v
i
t
c
A
4
,
3
,
2
V
=
#
E
C
L
I
V
=
#
E
O
,
H
I
0
3
0
5
A
m
I
3
C
C
V
C
C
d
e
ll
o
r
t
n
o
C
#
E
C
t
n
e
r
r
u
C
y
b
d
n
a
t
S
S
O
M
C
5
,
2
V
C
C
V
=
C
C
=
#
E
C
,
x
a
M
=
#
T
E
S
E
R
V
C
C
V
5
.
0
3
.
0
5
A
I
4
C
C
V
C
C
d
e
ll
o
r
t
n
o
C
#
T
E
S
E
R
t
n
e
r
r
u
C
y
b
d
n
a
t
S
S
O
M
C
5
,
2
V
C
C
V
=
C
C
,
x
a
M
=
#
T
E
S
E
R
V
S
S
V
5
.
0
3
.
0
5
A
V
L
I
e
g
a
t
l
o
V
w
o
L
t
u
p
n
I
5
.
0
-
8
.
0
V
V
H
I
e
g
a
t
l
o
V
h
g
i
H
t
u
p
n
I
V
x
7
.
0
C
C
V
C
C
3
.
0
+
V
V
D
I
d
n
a
D
I
c
i
n
o
r
t
c
e
l
E
r
o
f
e
g
a
t
l
o
V
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
y
r
a
r
o
p
m
e
T
V
C
C
V
0
.
5
=
5
.
1
1
5
.
2
1
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
V
C
C
V
=
C
C
,
n
i
M
I
L
O
A
m
8
.
5
=
5
4
.
0
V
V
H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
V
C
C
V
=
C
C
,
n
i
M
I
H
O
A
m
5
.
2
-
=
V
x
5
8
.
0
C
C
V
V
C
C
V
=
C
C
,
n
i
M
I
H
O
0
0
1
-
=
A
V
C
C
4
.
0
-
V
V
O
K
L
V
w
o
L
C
C
e
g
a
t
l
o
V
t
u
o
k
c
o
L
3
2
.
3
2
.
4
V
Notes:
1. The I
CC
current is listed is typically less than 2 mA/MHz with OE# at V
IH
.
2. Maximum I
CC
specifications are tested with V
CC
= V
CC
Max.
3. I
CC
active while the Automatic Erase or Automatic Program algorithm is in progress.
4. Not 100% tested.
5. I
CC3
= 20 A maximum for industrial and extended temperature versions.
23
Rev. 5.2/May 01
HY29F400
TEST CONDITIONS
Table 7. Test Specifications
Figure 11. Test Setup
Measurement Level
1.5 V Output
Input 1.5 V
0.0 V
3.0 V
HY29F400-45 Version
Measurement
Levels
Output
Input
0.45 V
2.4 V
0.8 V
2.0 V
0.8 V
2.0 V
HY29F400-55, -70, -90 Versions
Figure 12. Input Waveforms and Measurement Levels
M
R
O
F
E
V
A
W
S
T
U
P
N
I
S
T
U
P
T
U
O
y
d
a
e
t
S
L
o
t
H
m
o
r
f
g
n
i
g
n
a
h
C
H
o
t
L
m
o
r
f
g
n
i
g
n
a
h
C
d
e
t
t
i
m
r
e
P
e
g
n
a
h
C
y
n
A
,
e
r
a
C
t
'
n
o
D
n
w
o
n
k
n
U
e
t
a
t
S
,
g
n
i
g
n
a
h
C
y
l
p
p
A
t
o
N
s
e
o
D
e
t
a
t
S
e
c
n
a
d
e
p
m
I
h
g
i
H
s
i
e
n
il
r
e
t
n
e
C
)
Z
h
g
i
H
(
KEY TO SWITCHING WAVEFORMS
t
s
e
T
n
o
i
t
i
d
n
o
C
5
4
-
5
5
-
0
7
-
0
9
-
t
i
n
U
d
a
o
L
t
u
p
t
u
O
e
t
a
G
L
T
T
1
e
c
n
a
t
i
c
a
p
a
C
d
a
o
L
t
u
p
t
u
O
C
(
L
)
0
3
0
3
0
0
1
F
p
s
e
m
i
T
ll
a
F
d
n
a
e
s
i
R
t
u
p
n
I
5
5
0
2
s
n
l
e
v
e
L
w
o
L
l
a
n
g
i
S
t
u
p
n
I
0
.
0
5
4
.
0
5
4
.
0
V
l
e
v
e
L
h
g
i
H
l
a
n
g
i
S
t
u
p
n
I
0
.
3
4
.
2
4
.
2
V
t
n
e
m
e
r
u
s
a
e
M
g
n
i
m
i
T
w
o
L
l
e
v
e
L
l
a
n
g
i
S
5
.
1
8
.
0
8
.
0
V
t
n
e
m
e
r
u
s
a
e
M
g
n
i
m
i
T
h
g
i
H
l
e
v
e
L
l
a
n
g
i
S
5
.
1
0
.
2
0
.
2
V
6.2
K O h m
C
L
2.7
K O h m
+ 5 V
D E V I C E
U N D E R
T E S T
All diodes
are
1 N 3 0 6 4
or
equivalent
24
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Read Operations
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
Addresses Stable
t
R C
t
A C C
Output Valid
t
O E
t
C E
t
O E H
t
O H
t
D F
RY/BY#
0 V
R E S E T #
Outputs
W E #
O E #
C E #
Addresses
Figure 13. Read Operation Timings
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
p
u
t
e
S
t
s
e
T
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
V
A
V
A
t
C
R
e
m
i
T
e
l
c
y
C
d
a
e
R
1
n
i
M
5
4
5
5
0
7
0
9
s
n
t
V
Q
V
A
t
C
C
A
y
a
l
e
D
t
u
p
t
u
O
o
t
s
s
e
r
d
d
A
V
=
#
E
C
L
I
V
=
#
E
O
L
I
x
a
M
5
4
5
5
0
7
0
9
s
n
t
V
Q
L
E
t
E
C
y
a
l
e
D
t
u
p
t
u
O
o
t
e
l
b
a
n
E
p
i
h
C
V
=
#
E
O
L
I
x
a
M
5
4
5
5
0
7
0
9
s
n
t
Z
Q
H
E
t
F
D
Z
h
g
i
H
t
u
p
t
u
O
o
t
e
l
b
a
n
E
p
i
h
C
1
x
a
M
5
1
5
1
0
2
0
2
s
n
t
V
Q
L
G
t
E
O
y
a
l
e
D
t
u
p
t
u
O
o
t
e
l
b
a
n
E
t
u
p
t
u
O
V
=
#
E
C
L
I
x
a
M
5
2
5
2
0
3
5
3
s
n
t
Z
Q
H
G
t
F
D
Z
h
g
i
H
t
u
p
t
u
O
o
t
e
l
b
a
n
E
t
u
p
t
u
O
1
x
a
M
5
1
5
1
0
2
0
2
s
n
t
H
E
O
e
l
b
a
n
E
t
u
p
t
u
O
e
m
i
T
d
l
o
H
1
d
a
e
R
n
i
M
0
s
n
d
n
a
e
l
g
g
o
T
g
n
il
l
o
P
#
a
t
a
D
n
i
M
0
1
s
n
t
X
Q
X
A
t
H
O
#
E
C
,
s
e
s
s
e
r
d
d
A
m
o
r
f
e
m
i
T
d
l
o
H
t
u
p
t
u
O
t
s
r
i
F
s
r
u
c
c
O
r
e
v
e
h
c
i
h
W
,
#
E
O
r
o
1
n
i
M
0
s
n
25
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Hardware Reset (RESET#)
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test conditions.
Figure 14. RESET# Timings
Reset Timings NOT During Automatic Algorithms
Reset Timings During Automatic Algorithms
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
p
u
t
e
S
t
s
e
T
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
Y
D
A
E
R
c
i
t
a
m
o
t
u
A
g
n
i
r
u
D
(
w
o
L
n
i
P
#
T
E
S
E
R
e
t
i
r
W
r
o
d
a
e
R
o
t
)
s
m
h
t
i
r
o
g
l
A
1
x
a
M
0
2
s
t
Y
D
A
E
R
c
i
t
a
m
o
t
u
A
g
n
i
r
u
D
T
O
N
(
w
o
L
n
i
P
#
T
E
S
E
R
e
t
i
r
W
r
o
d
a
e
R
o
t
)
s
m
h
t
i
r
o
g
l
A
1
x
a
M
0
0
5
s
n
t
P
R
h
t
d
i
W
e
s
l
u
P
#
T
E
S
E
R
n
i
M
0
0
5
s
n
t
H
R
d
a
e
R
e
r
o
f
e
B
e
m
i
T
h
g
i
H
#
T
E
S
E
R
1
n
i
M
0
5
s
n
t
B
R
e
m
i
T
y
r
e
v
o
c
e
R
#
Y
B
/
Y
R
n
i
M
0
s
n
R Y / B Y #
0 V
t
R P
t
Ready
C E # , O E #
R E S E T #
t
R H
R Y / B Y #
t
R P
t
Ready
C E # , O E #
R E S E T #
t
R B
26
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
L
F
L
E
w
o
L
g
n
i
h
c
t
i
w
S
#
E
T
Y
B
o
t
#
E
C
x
a
M
5
s
n
t
H
F
L
E
h
g
i
H
g
n
i
h
c
t
i
w
S
#
E
T
Y
B
o
t
#
E
C
x
a
M
5
s
n
t
Z
Q
L
F
Z
-
h
g
i
H
t
u
p
t
u
O
o
t
w
o
L
g
n
i
h
c
t
i
w
S
#
E
T
Y
B
x
a
M
5
1
5
1
0
2
0
2
s
n
t
V
Q
H
F
e
v
i
t
c
A
t
u
p
t
u
O
o
t
h
g
i
H
g
n
i
h
c
t
i
w
S
#
E
T
Y
B
n
i
M
5
4
5
5
0
7
0
9
s
n
Data Output DQ[14:0]
Data Output DQ[7:0]
Data Output DQ[7:0]
Data Output DQ[14:0]
Output DQ[15]
Address Input A-1
Address Input A-1
Data Output DQ[15]
t
E L F L
t
E L F H
t
F H Q V
t
F L Q Z
C E #
O E #
B Y T E #
DQ[14:0]
DQ[15]/A-1
B Y T E #
DQ[14:0]
DQ[15]/A-1
B Y T E #
switching
from word to
byte mode
B Y T E #
switching
from byte to
word mode
Figure 15. BYTE# Timings for Read Operations
Figure 16. BYTE# Timings for Write Operations
t
S E T
(t
A S
)
t
H O L D
(t
A H
)
Falling edge of the last WE# signal
C E #
W E #
B Y T E #
Note: Refer to the Program/Erase Operations table for t
AS
and t
AH
specifications.
27
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Program and Erase Operations
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 C, V
CC
= 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-
tions of 90 C, V
CC
= 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
V
A
V
A
t
C
W
e
m
i
T
e
l
c
y
C
e
t
i
r
W
1
n
i
M
5
4
5
5
0
7
0
9
s
n
t
L
W
V
A
t
S
A
e
m
i
T
p
u
t
e
S
s
s
e
r
d
d
A
n
i
M
0
s
n
t
X
A
L
W
t
H
A
e
m
i
T
d
l
o
H
s
s
e
r
d
d
A
n
i
M
5
4
5
4
5
4
5
4
s
n
t
H
W
V
D
t
S
D
e
m
i
T
p
u
t
e
S
a
t
a
D
n
i
M
5
2
5
2
0
3
5
4
s
n
t
X
D
H
W
t
H
D
e
m
i
T
d
l
o
H
a
t
a
D
n
i
M
0
s
n
t
L
W
H
G
t
L
W
H
G
e
t
i
r
W
e
r
o
f
e
B
e
m
i
T
y
r
e
v
o
c
e
R
d
a
e
R
n
i
M
0
s
n
t
L
W
L
E
t
S
C
e
m
i
T
p
u
t
e
S
#
E
C
n
i
M
0
s
n
t
H
E
H
W
t
H
C
e
m
i
T
d
l
o
H
#
E
C
n
i
M
0
s
n
t
H
W
L
W
t
P
W
h
t
d
i
W
e
s
l
u
P
e
t
i
r
W
n
i
M
0
3
0
3
5
3
5
4
s
n
t
L
W
H
W
t
H
P
W
h
g
i
H
h
t
d
i
W
e
s
l
u
P
e
t
i
r
W
n
i
M
0
2
s
n
t
1
H
W
H
W
t
1
H
W
H
W
n
o
i
t
a
r
e
p
O
g
n
i
m
m
a
r
g
o
r
P
3
,
2
,
1
e
d
o
M
e
t
y
B
p
y
T
7
s
x
a
M
0
0
3
s
d
r
o
W
e
d
o
M
p
y
T
2
1
s
x
a
M
0
0
5
s
n
o
i
t
a
r
e
p
O
g
n
i
m
m
a
r
g
o
r
P
p
i
h
C
5
,
3
,
2
,
1
e
d
o
M
e
t
y
B
p
y
T
6
.
3
c
e
s
x
a
M
8
.
0
1
c
e
s
d
r
o
W
e
d
o
M
p
y
T
1
.
3
c
e
s
x
a
M
3
.
9
c
e
s
t
2
H
W
H
W
t
2
H
W
H
W
n
o
i
t
a
r
e
p
O
e
s
a
r
E
r
o
t
c
e
S
4
,
2
,
1
p
y
T
1
c
e
s
x
a
M
8
c
e
s
t
3
H
W
H
W
t
3
H
W
H
W
n
o
i
t
a
r
e
p
O
e
s
a
r
E
p
i
h
C
4
,
2
,
1
p
y
T
1
1
c
e
s
x
a
M
8
8
c
e
s
e
c
n
a
r
u
d
n
E
e
l
c
y
C
m
a
r
g
o
r
P
d
n
a
e
s
a
r
E
p
y
T
0
0
0
,
0
0
0
,
1
s
e
l
c
y
c
n
i
M
0
0
0
,
0
0
1
s
e
l
c
y
c
t
S
C
V
V
C
C
e
m
i
T
p
u
t
e
S
n
i
M
0
5
s
t
B
R
#
Y
B
/
Y
R
m
o
r
f
e
m
i
T
y
r
e
v
o
c
e
R
n
i
M
0
s
n
t
Y
S
U
B
y
a
l
e
D
#
Y
B
/
Y
R
o
t
#
E
W
n
i
M
0
3
0
3
0
3
5
3
s
n
28
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Notes:
1. PA = Program Address, PD = Program Data, D
OUT
is the true data at the program address.
2. Commands shown are for Word mode operation.
3. V
CC
shown only to illustrate t
VCS
measurement references. It cannot occur as shown during a valid command sequence.
Figure 17. Program Operation Timings
Addresses
C E #
t
W C
0x555
P A
P A
PA
O E #
t
A S
t
A H
t
W P H
t
W P
t
G H W L
t
C S
W E #
Data
t
D S
t
D H
0xA0
P D
Status
t
W H W H 1
RY/BY#
t
B U S Y
t
R B
t
V C S
V
C C
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
D
O U T
t
C H
29
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Notes:
1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section),
D
OUT
is the true data at the read address.(0xFF after an erase operation).
2. Commands shown are for Word mode operation.
3. V
CC
shown only to illustrate t
VCS
measurement references. It cannot occur as shown during a valid command sequence.
Figure 18. Sector/Chip Erase Operation Timings
Addresses
C E #
t
W C
0 x 2 A A
V A
V A
SA
O E #
t
A S
t
A H
t
W P H
t
W P
t
G H W L
t
C S
t
C H
W E #
Data
t
D S
t
D H
0x55
0x30
Status
D
O U T
t
W H W H 2
or
t
W H W H 3
RY/BY#
t
B U S Y
t
R B
t
V C S
V
C C
Erase Command Sequence (last two cycles)
Read Status Data (last two cycles)
Address = 0x555
for chip erase
Data = 0x10
for chip erase
30
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Notes:
1. VA = Valid Address for reading Toggle Bits (DQ2, DQ6) status data (see Write Operation Status section).
2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 20. Toggle Polling Timings (During Automatic Algorithms)
t
B U S Y
t
C H
t
O E
t
C E
t
R C
C o m p l e m e n t
C o m p l e m e n t
T r u e
Valid Data
Status Data
Status Data
D a t a
Valid Data
RY/BY#
DQ[6:0]
DQ[7]
W E #
O E #
C E #
Addresses
V A
V A
V A
t
A C C
t
O E H
t
O H
t
D F
Notes:
1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section).
2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 19. Data# Polling Timings (During Automatic Algorithms)
t
B U S Y
t
C H
t
O E
t
C E
t
R C
Valid Status
Valid Status
Valid Status
RY/BY#
DQ[6], [2]
W E #
O E #
C E #
Addresses
V A
V A
V A
t
O E H
t
O H
t
D F
V A
(second read)
(first read)
(stops toggling)
Valid Data
t
A C C
31
Rev. 5.2/May 01
HY29F400
Notes:
1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an
erase-suspended sector.
Figure 21. DQ[2] and DQ[6] Operation
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
T
S
e
m
i
T
p
u
t
e
S
e
g
a
t
l
o
V
n
i
M
4
s
t
P
S
R
r
o
f
e
m
i
T
p
u
t
e
S
#
T
E
S
E
R
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
y
r
a
r
o
p
m
e
T
n
i
M
4
s
t
E
C
y
a
l
e
D
t
u
p
t
u
O
o
t
e
l
b
a
n
E
p
i
h
C
x
a
M
5
4
5
5
0
7
0
9
s
n
t
E
O
y
a
l
e
D
t
u
p
t
u
O
o
t
e
l
b
a
n
E
t
u
p
t
u
O
x
a
M
5
2
5
2
0
3
5
3
s
n
t
R
D
I
V
V
D
I
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
y
r
a
r
o
p
m
e
T
r
o
f
e
m
i
T
n
o
i
t
i
s
n
a
r
T
1
n
i
M
0
0
5
s
n
t
T
H
L
V
V
D
I
t
c
e
t
o
r
p
n
U
d
n
a
t
c
e
t
o
r
P
r
o
t
c
e
S
r
o
f
e
m
i
T
n
o
i
t
i
s
n
a
r
T
1
n
i
M
0
0
5
s
n
t
1
P
P
W
t
c
e
t
o
r
P
r
o
t
c
e
S
r
o
f
h
t
d
i
W
e
s
l
u
P
e
t
i
r
W
n
i
M
0
0
1
s
t
2
P
P
W
t
c
e
t
o
r
p
n
U
r
o
t
c
e
S
r
o
f
h
t
d
i
W
e
s
l
u
P
e
t
i
r
W
n
i
M
0
0
1
s
m
t
P
S
E
O
e
v
i
t
c
A
#
E
W
o
t
e
m
i
T
p
u
t
e
S
#
E
O
1
n
i
M
4
s
t
P
S
C
e
v
i
t
c
A
#
E
W
o
t
e
m
i
T
p
u
t
e
S
#
E
C
1
n
i
M
4
s
Sector Protect and Unprotect, Temporary Sector Unprotect
Notes:
1. Not 100% tested.
t
V I D R
RY/BY#
W E #
C E #
R E S E T #
V
ID
0 or 5V
t
R S P
t
V I D R
0 or 5V
Figure 22. Temporary Sector Unprotect Timings
E r a s e
C o m p l e t e
W E #
DQ[6]
DQ[2]
Enter Automatic
E r a s e
E r a s e
E r a s e
S u s p e n d
R e a d
Enter Erase
S u s p e n d
P r o g r a m
E r a s e
S u s p e n d
P r o g r a m
E r a s e
S u s p e n d
R e a d
E r a s e
R e s u m e
E r a s e
E r a s e
S u s p e n d
AC CHARACTERISTICS
32
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Figure 23. Sector Protect Timings
t
S T
V
C C
R E S E T #
Data
C E #
W E #
O E #
A[9]
A[6]
A[1]
A[0]
A[17:12]
V
I D
V
I D
S A
X
S A
Y
0x01
t
V L H T
t
V L H T
t
V L H T
t
W P P 1
t
V L H T
t
S T
Sector Protect Cycle
Protect Verify Cycle
t
S T
t
O E
t
S T
t
O E S P
33
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Figure 24. Sector Unprotect Timings
V
C C
R E S E T #
Data
C E #
W E #
O E #
A[9]
A[6]
A[1]
A[0]
A[17:12]
V
I D
S A
0
S A
1
0x00
t
V L H T
t
O E S P
t
W P P 2
t
S T
t
O E
Sector Unprotect Cycle
Unprotect Verify Cycle
t
V L H T
V
I D
V
I D
t
C E
t
C S P
t
S T
t
S T
34
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Notes:
1. Not 100% tested.
2. Typical program and erase times assume the following conditions: 25 C, V
CC
= 5.0 volts, 100,000 cycles. In addition,
programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case condi-
tions of 90 C, V
CC
= 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles.
3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program
command. See Table 5 for further information on command sequences.
4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes
are programmed to 0x00 before erasure.
5. The typical chip programming time is considerably less than the maximum chip programming time listed since most
bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum
byte program time specified is exceeded. See Write Operation Status section for additional information.
r
e
t
e
m
a
r
a
P
n
o
i
t
p
i
r
c
s
e
D
n
o
i
t
p
O
d
e
e
p
S
t
i
n
U
C
E
D
E
J
d
t
S
5
4
-
5
5
-
0
7
-
0
9
-
t
V
A
V
A
t
C
W
e
m
i
T
e
l
c
y
C
e
t
i
r
W
1
n
i
M
5
4
5
5
0
7
0
9
s
n
t
L
E
V
A
t
S
A
e
m
i
T
p
u
t
e
S
s
s
e
r
d
d
A
n
i
M
0
s
n
t
X
A
L
E
t
H
A
e
m
i
T
d
l
o
H
s
s
e
r
d
d
A
n
i
M
5
4
5
4
5
4
5
4
s
n
t
H
E
V
D
t
S
D
e
m
i
T
p
u
t
e
S
a
t
a
D
n
i
M
5
2
5
2
0
3
5
4
s
n
t
X
D
H
E
t
H
D
e
m
i
T
d
l
o
H
a
t
a
D
n
i
M
0
s
n
t
L
E
H
G
t
L
E
H
G
e
t
i
r
W
e
r
o
f
e
B
e
m
i
T
y
r
e
v
o
c
e
R
d
a
e
R
n
i
M
0
s
n
t
L
E
L
W
t
S
W
e
m
i
T
p
u
t
e
S
#
E
W
n
i
M
0
s
n
t
H
W
H
E
t
H
W
e
m
i
T
d
l
o
H
#
E
W
n
i
M
0
s
n
t
H
E
L
E
t
P
C
h
t
d
i
W
e
s
l
u
P
#
E
C
n
i
M
0
3
0
3
5
3
5
4
s
n
t
L
E
H
E
t
H
P
C
h
g
i
H
h
t
d
i
W
e
s
l
u
P
#
E
C
n
i
M
0
2
s
n
t
1
H
W
H
W
t
1
H
W
H
W
n
o
i
t
a
r
e
p
O
g
n
i
m
m
a
r
g
o
r
P
3
,
2
,
1
e
d
o
M
e
t
y
B
p
y
T
7
s
x
a
M
0
0
3
s
d
r
o
W
e
d
o
M
p
y
T
2
1
s
x
a
M
0
0
5
s
n
o
i
t
a
r
e
p
O
g
n
i
m
m
a
r
g
o
r
P
p
i
h
C
5
,
3
,
2
,
1
e
d
o
M
e
t
y
B
p
y
T
6
.
3
c
e
s
x
a
M
8
.
0
1
c
e
s
d
r
o
W
e
d
o
M
p
y
T
3
1
.
3
c
e
s
x
a
M
3
.
9
c
e
s
t
2
H
W
H
W
t
2
H
W
H
W
n
o
i
t
a
r
e
p
O
e
s
a
r
E
r
o
t
c
e
S
4
,
2
,
1
p
y
T
1
c
e
s
x
a
M
8
c
e
s
t
3
H
W
H
W
t
3
H
W
H
W
n
o
i
t
a
r
e
p
O
e
s
a
r
E
p
i
h
C
4
,
2
,
1
p
y
T
1
1
c
e
s
x
a
M
8
8
c
e
s
e
c
n
a
r
u
d
n
E
e
l
c
y
C
m
a
r
g
o
r
P
d
n
a
e
s
a
r
E
p
y
T
0
0
0
,
0
0
0
,
1
s
e
l
c
y
c
n
i
M
0
0
0
,
0
0
1
s
e
l
c
y
c
t
Y
S
U
B
y
a
l
e
D
#
Y
B
/
Y
R
o
t
#
E
C
n
i
M
0
3
0
3
0
3
5
3
s
n
35
Rev. 5.2/May 01
HY29F400
AC CHARACTERISTICS
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
t
W S
t
R H
t
W H
C E #
O E #
Addresses
t
W C
V A
t
A S
t
A H
W E #
Data
RY/BY#
t
D S
Status
D
O U T
t
B U S Y
t
W H W H 1
or t
W H W H 2
or t
W H W H 3
t
D H
0xA0 for Program
0x55 for Erase
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
R E S E T #
t
C P
t
C P H
t
G H E L
Notes:
1.
PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write
Operation Status section), D
OUT
= array data read at VA.
2.
Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle.
3.
Word mode addressing shown.
4.
RESET# shown only to illustrate t
RH
measurement references. It cannot occur as shown during a valid command
sequence.
Figure 25. Alternate CE# Controlled Write Operation Timings
36
Rev. 5.2/May 01
HY29F400
Latchup Characteristics
Notes:
1. Includes all pins except V
CC
. Test conditions: V
CC
= 5.0V, one pin at a time.
TSOP and PSOP Pin Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions: T
A
= 25 C, f = 1.0 MHz.
n
o
i
t
p
i
r
c
s
e
D
m
u
m
i
n
i
M
m
u
m
i
x
a
M
t
i
n
U
V
o
t
t
c
e
p
s
e
r
h
t
i
w
e
g
a
t
l
o
v
t
u
p
n
I
S
S
s
n
i
p
O
/
I
t
p
e
c
x
e
s
n
i
p
ll
a
n
o
)
#
T
E
S
E
R
d
n
a
#
E
O
,
]
9
[
A
g
n
i
d
u
l
c
n
i
(
0
.
1
-
5
.
2
1
V
V
o
t
t
c
e
p
s
e
r
h
t
i
w
e
g
a
t
l
o
v
t
u
p
n
I
S
S
s
n
i
p
O
/
I
ll
a
n
o
0
.
1
-
V
C
C
0
.
1
+
V
V
C
C
t
n
e
r
r
u
C
0
0
1
-
0
0
1
A
m
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
p
u
t
e
S
t
s
e
T
p
y
T
x
a
M
t
i
n
U
C
N
I
e
c
n
a
t
i
c
a
p
a
C
t
u
p
n
I
V
N
I
0
=
6
5
.
7
F
p
C
T
U
O
e
c
n
a
t
i
c
a
p
a
C
t
u
p
t
u
O
V
T
U
O
0
=
5
.
8
2
1
F
p
C
2
N
I
e
c
n
a
t
i
c
a
p
a
C
n
i
P
l
o
r
t
n
o
C
V
N
I
0
=
5
.
7
9
F
p
Data Retention
r
e
t
e
m
a
r
a
P
s
n
o
i
t
i
d
n
o
C
t
s
e
T
m
u
m
i
n
i
M
t
i
n
U
e
m
i
T
n
o
i
t
n
e
t
e
R
a
t
a
D
n
r
e
t
t
a
P
m
u
m
i
n
i
M
C
0
5
1
0
1
s
r
a
e
Y
C
5
2
1
0
2
s
r
a
e
Y
37
Rev. 5.2/May 01
HY29F400
PACKAGE DRAWINGS
Physical Dimensions
TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)
PSOP44 - 44-pin Plastic Small Outline Package (measurements in millimeters)
18.30
18.50
Pin 1 ID
11.90
12.10
0.25MM (0.0098") BSC
1.20
MAX
1
24
48
25
19.80
20.20
0.50 BSC
0.95
1.05
0.50
0.70
0
5
o
o
0.10
0.21
0.08
0.20
0.05
0.15
44
23
22
13.10
13.50
1.27 NOM.
0.10
0.35
2.17
2.45
SEATING PLANE
0
O
8
O
0.10
0.21
1
2.80
MAX.
28.00
28.40
15.70
16.30
0.35
0.50
0.60
1.00
38
Rev. 5.2/May 01
HY29F400
ORDERING INFORMATION
Hynix products are available in several speeds, packages and operating temperature ranges. The
ordering part number is formed by combining a number of fields, as indicated below. Refer to the `Valid
Combinations' table, which lists the configurations that are planned to be supported in volume. Please
contact your local Hynix representative or distributor to confirm current availability of specific configura-
tions and to determine if additional configurations have been released.
VALID COMBINATIONS
d
e
e
p
S
d
n
a
e
g
a
k
c
a
P
P
O
S
P
P
O
S
T
P
O
S
T
e
s
r
e
v
e
R
e
r
u
t
a
r
e
p
m
e
T
s
n
5
4
s
n
5
5
s
n
0
7
s
n
0
9
s
n
5
4
s
n
5
5
s
n
0
7
s
n
0
9
s
n
5
4
s
n
5
5
s
n
0
7
s
n
0
9
l
a
i
c
r
e
m
m
o
C
5
4
-
G
5
5
-
G
0
7
-
G
0
9
-
G
5
4
-
T
5
5
-
T
0
7
-
T
0
9
-
T
5
4
-
R
5
5
-
R
0
7
-
R
0
9
-
R
Note:
1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table above
to the Device Number. For example, the part number for a 90 ns, Commercial temperature range device in the reverse
TSOP package with the top boot block option is HY29F400TR-90.
0
0
4
F
9
2
Y
H
X
X
-
X
X
X
S
N
O
I
T
C
U
R
T
S
N
I
L
A
I
C
E
P
S
E
G
N
A
R
E
R
U
T
A
R
E
P
M
E
T
=
k
n
a
l
B
)
C
0
7
+
o
t
0
(
l
a
i
c
r
e
m
m
o
C
N
O
I
T
P
O
D
E
E
P
S
=
5
4
=
5
5
=
0
7
=
0
9
s
n
5
4
s
n
5
5
s
n
0
7
s
n
0
9
E
P
Y
T
E
G
A
K
C
A
P
=
G
=
T
=
R
)
P
O
S
P
(
e
g
a
k
c
a
P
e
n
il
t
u
O
ll
a
m
S
c
i
t
s
a
l
P
n
i
P
-
4
4
)
P
O
S
T
(
e
g
a
k
c
a
P
e
n
il
t
u
O
ll
a
m
S
n
i
h
T
n
i
P
-
8
4
h
t
i
w
)
P
O
S
T
(
e
g
a
k
c
a
P
e
n
il
t
u
O
ll
a
m
S
n
i
h
T
n
i
P
-
8
4
t
u
o
n
i
P
e
s
r
e
v
e
R
N
O
I
T
A
C
O
L
K
C
O
L
B
T
O
O
B
=
T
=
B
n
o
i
t
p
O
k
c
o
l
B
t
o
o
B
p
o
T
n
o
i
t
p
O
k
c
o
l
B
t
o
o
B
m
o
t
t
o
B
R
E
B
M
U
N
E
C
I
V
E
D
=
0
0
4
F
9
2
Y
H
y
l
n
O
-
t
l
o
V
5
S
O
M
C
)
6
1
x
K
6
5
2
/
8
x
K
2
1
5
(
t
i
b
a
g
e
M
4
y
r
o
m
e
M
h
s
a
l
F
e
s
a
r
E
r
o
t
c
e
S
39
Rev. 5.2/May 01
HY29F400
40
Rev. 5.2/May 01
HY29F400
Important Notice
2001 by Hynix Semiconductor America. All rights reserved.
No part of this document may be copied or reproduced in any
form or by any means without the prior written consent of Hynix
Semiconductor Inc. or Hynix Semiconductor America (collec-
tively "Hynix").
The information in this document is subject to change without
notice. Hynix shall not be responsible for any errors that may
appear in this document and makes no commitment to update
or keep current the information contained in this document.
Hynix advises its customers to obtain the latest version of the
device specification to verify, before placing orders, that the
information being relied upon by the customer is current.
Devices sold by Hynix are covered by warranty and patent
indemnification provisions appearing in Hynix Terms and Con-
ditions of Sale only. Hynix makes no warranty, express, statu-
tory, implied or by description, regarding the information set
forth herein or regarding the freedom of the described devices
from intellectual property infringement. Hynix makes no war-
ranty of merchantability or fitness for any purpose.
Hynix's products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific writ-
ten agreement pertaining to such intended use is executed
between the customer and Hynix prior to use. Life support
devices or systems are those which are intended for surgical
implantation into the body, or which sustain life whose failure
to perform, when properly used in accordance with instruc-
tions for use provided in the labeling, can be reasonably ex-
pected to result in significant injury to the user.
d
r
o
c
e
R
n
o
i
s
i
v
e
R
.
v
e
R
e
t
a
D
s
l
i
a
t
e
D
2
.
5
1
0
/
5
.
.
t
a
m
r
o
f
x
i
n
y
H
o
t
e
g
n
a
h
C
.
n
o
i
t
c
e
s
s
u
t
a
t
S
n
o
i
t
a
r
e
p
O
e
t
i
r
W
n
i
n
o
i
t
a
r
e
p
o
]
6
[
Q
D
g
n
i
d
r
a
g
e
r
e
t
o
n
d
e
d
d
A
.
s
n
o
i
t
p
o
e
r
u
t
a
r
e
p
m
e
t
d
e
d
n
e
t
x
E
d
n
a
l
a
i
r
t
s
u
d
n
I
d
e
v
o
m
e
R
Memory Sales and Marketing Division
Flash Memory Business Unit
Hynix Semiconductor Inc.
Hynix Semiconductor America Inc.
10 Fl., Hynix Youngdong Building
3101 North First Street
89, Daechi-dong
San Jose, CA 95134
Kangnam-gu
USA
Seoul, Korea
Telephone: (408) 232-8800
Telephone: +82-2-580-5000
Fax: (408) 232-8805
Fax: +82-2-3459-3990
http://www.us.hynix.com
http://www.hynix.com
PDF 
ZIP