HY57V643220C-I Series
4 Banks x 512K x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.6 / Apr. 2003 1
DESCRIPTION
The Hynix HY57V643220C is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and extended temperature range. HY57V643220C is organized as 4banks of
524,288x32.
HY57V643220C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V643220CT-5I
200MHz
Normal
4Banks x 512Kbits
x32
LVTTL
400mil 86pin TSOP II
HY57V643220CT-55I
183MHz
HY57V643220CT-6I
166MHz
HY57V643220CT-7I
143MHz
HY57V643220CT-SI
100MHz
HY57V643220CLT-5I
200MHz
Low-Power
HY57V643220CLT-55I
183MHz
HY57V643220CLT-6I
166MHz
HY57V643220CLT-7I
143MHz
HY57V643220CLT-SI
100MHz
Rev. 0.6 / Apr. 2003 2
HY57V643220C-I
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
D D
D Q 0
V
D D Q
D Q 1
D Q 2
V
S S Q
D Q 3
D Q 4
V
D D Q
D Q 5
D Q 6
V
S S Q
D Q 7
N C
V
D D
D Q M 0
/W E
/C A S
/R A S
/C S
N C
B A 0
B A 1
A 1 0/A P
A 0
A 1
A 2
D Q M 2
V
D D
N C
D Q 16
V
S S Q
D Q 17
D Q 18
V
D D Q
D Q 19
D Q 20
V
S S Q
D Q 21
D Q 22
V
D D Q
D Q 23
V
D D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V
S S
D Q 15
V
S S Q
D Q 14
D Q 13
V
D D Q
D Q 12
D Q 11
V
S S Q
D Q 10
D Q 9
V
D D Q
D Q 8
N C
V
S S
D Q M 1
N C
N C
C LK
C K E
A 9
A 8
A 7
A 6
A 5
A 4
A 3
D Q M 3
V
S S
N C
D Q 31
V
D D Q
D Q 30
D Q 29
V
S S Q
D Q 28
D Q 27
V
D D Q
D Q 26
D Q 25
V
S S Q
D Q 24
V
S S
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
Rev. 0.6 / Apr. 2003 3
HY57V643220C-I
FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Synchronous DRAM
X deco
ders
St
at
e Ma
chin
e
A0
A1
A10
BA0
BA1
A
ddre
ss b
u
f
f
e
rs
Address
Register
M ode Registers
Row
Pre
Decoders
Colum n
Pre
Decoders
Colum n Add
Counter
Row Active
Colum n
Active
Burst
Counter
Data O ut Control
CAS Latency
Internal Row
Counter
DQ 0
DQ 1
DQ 30
DQ 31
Self Refresh Logic
& Tim er
Pipe Line Control
I/
O Bu
ffe
r &
Lo
gic
Bank Select
Sense AMP
& I/O Gate
CLK
CKE
CS
RAS
CAS
W E
DQ M 0
DQ M 1
DQ M 2
DQ M 3
512Kx32 Bank 3
X de
code
rs
X d
e
co
ders
M em ory
Cell
Array
Y decoders
X d
e
c
od
ers
512Kx32 Bank 0
512Kx32 Bank 1
512Kx32 Bank 2
Rev. 0.6 / Apr. 2003
4
HY57V643220C-I
ABSOLUTE MAXIMUM RATINGS
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA= -40 to 85
C
)
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
3ns of duration with no input clamp diodes
3.V
IL
(min) is acceptable -2.0V AC pulse width with
3
ns of duration with no input clamp diodes
AC OPERATING CONDITION
(TA= -40 to 85
C
, 3.0V
V
DD
3.6V, V
SS
=0V - Note1)
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
-40 ~ 85
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
relative to V
SS
V
DD,
V
DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
1
W
Soldering Temperature
Time
T
SOLDER
260
10
C
Sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
1,2
Input high voltage
V
IH
2.0
3.0
V
DDQ
+ 0.3
V
1,3
Input low voltage
V
IL
V
SSQ
- 0.3
0
0.8
V
1,4
Parameter
Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4/0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
tR / tF
1
ns
Output timing measurement reference level
Voutref
1.4
V
Output load capacitance for access time measurement
CL
30
pF
1
Rev. 0.6 / Apr. 2003
5
HY57V643220C-I
CAPACITANCE
(TA=25
C
, f=1MHz, VDD=3.3V)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I
(DC operating conditions unless otherwise noted)
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
C
I1
2.5
4
pF
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI
2
2.5
5
pF
Data input / output capacitance
DQ0 ~ DQ31
C
I/O
4
6.5
pF
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
I
LI
-1
1
uA
1
Output leakage current
I
LO
-1.5
1.5
uA
2
Output high voltage
V
OH
2.4
-
V
I
OH
= -2mA
Output low voltage
V
OL
-
0.4
V
I
OL
= +2mA
Vtt=1.4V
RT=500
30pF
Output
DC Output Load Circuit
AC Output Load Circuit
Vtt=1.4V
RT=50
30pF
Output
Z0 = 50
Rev. 0.6 / Apr. 2003
6
HY57V643220C-I
DC CHARACTERISTICS II
(DC operating conditions unless otherwise noted)
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V643220CT-5I/55I/6I/7I/SI
4.HY57V643220CLT-5I/55I/6I/7I/SI
Parameter
Symbol
Test Condition
Speed
Unit
Note
-5I
-55I
-6I
-7I
-SI
Operating Current
IDD1
Burst Length=1, One bank active
tRAS
tRAS(min), tRP tRP(min),
IOL=0mA
200
190
180
170
150
mA
1
Precharge Standby Current
in power down mode
IDD2P
CKE
VIL(max), tCK = 15ns
2
mA
IDD2PS
CKE
VIL(max), tCK =
2
Precharge Standby Current
in non power down mode
IDD2N
CKE
VIH(min), CS VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
VDD-0.2V or
0.2V
15
mA
IDD2NS
CKE
VIH(min), tCK =
Input signals are stable.
10
Active Standby Current
in power down mode
IDD3P
CKE
VIL(max), tCK = 15ns
3
mA
IDD3PS
CKE
VIL(max), tCK =
3
Active Standby Current
in non power down mode
IDD3N
CKE
VIH(min), CS VIH(min), tCK = 15ns
Input signals are changed one time during
2clks. All other pins
VDD-0.2V or
0.2V
40
mA
IDD3NS
CKE
VIH(min), tCK =
Input signals are stable
25
Burst Mode Operating
Current
IDD4
tCK
tCK(min),
tRAS
tRAS(min), IOL=0mA
All banks active
CL=3
280
260
240
210
160
mA
1
CL=2
-
-
-
160
140
Auto Refresh Current
IDD5
tRRC
tRRC(min), All banks active
250
240
230
220
190
mA
2
Self Refresh Current
IDD6
CKE
0.2V
2
mA
3
1
mA
4
Rev. 0.6 / Apr. 2003
7
HY57V643220C-I
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate, 0.8v to 2.0v
3.Data-out hold time to be measured under 30pF load condition, without Vt termination
Parameter
Symbol
-5I
-55I
-6I
-7I
-SI
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System clock
cycle time
CAS Latency = 3
tCK3
5
1000
5.5
1000
6
1000
7
1000
10
1000
ns
CAS Latency = 2
tCK2
-
-
-
-
-
-
-10
12
ns
Clock high pulse width
tCHW
2
-
2.25
-
2.5
-
3
-
3.5
-
ns
1
Clock low pulse width
tCLW
2
-
2.25
-
2.5
-
3
-
3.5
-
ns
1
Access time from
clock
CAS Latency = 3
tAC3
-
4.5
-
5
-
5.5
-
5.5
-
6
ns
2
CAS Latency = 2
tAC2
-
-
-
-
-
-
-
6
-
6
ns
Data-out hold time
tOH
1.5
-
2
-
2
-
2
-
2
-
ns
3
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.75
-
2.5
-
ns
1
Data-Input hold time
tDH
1
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.75
-
2.5
-
ns
1
Address hold time
tAH
1
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.75
-
2.5
-
ns
1
CKE hold time
tCKH
1
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.75
-
2.5
-
ns
1
Command hold time
tCH
1
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
1
-
1
-
ns
CLK to data output
in high Z-time
CAS Latency = 3
tOHZ3
-
4.5
-
5
-
5.5
-
5.5
-
6
ns
CAS Latency = 2
tOHZ2
-
-
-
-
-
-
-
6
-
6
ns
Rev. 0.6 / Apr. 2003
8
HY57V643220C-I
AC CHARACTERISTICS II
(AC operating conditions unless otherwise noted)
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-5I
-55I
-6I
-7I
-SI
Unit
Not
e
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS cycle time
Operation
tRC
55
-
55
-
60
-
63
-
70
-
ns
Auto Refresh
tRRC
55
-
55
-
60
-
63
-
70
-
ns
RAS to CAS delay
tRCD
15
-
16.5
-
18
-
20
-
20
-
ns
RAS active time
tRAS
38.7
100K
38.7
100K
42
100K
42
100K
50
100K
ns
RAS precharge time
tRP
15
-
16.5
-
18
-
20
-
20
-
ns
RAS to RAS bank active delay
tRRD
2
-
2
-
2
-
2
-
2
-
CLK
CAS to CAS delay
tCCD
1
-
1
-
1
-
1
-
1
-
CLK
Write command to data-in delay
tWTL
0
-
0
-
0
-
0
-
0
-
CLK
Data-in to precharge command
tDPL
2
-
2
-
2
-
2
-
2
-
CLK
Data-in to active command
tDAL
4
-
4
-
5
-
5
-
4
-
ns
DQM to data-out Hi-Z
tDQZ
2
-
2
-
2
-
2
-
2
-
CLK
DQM to data-in mask
tDQM
0
-
0
-
0
-
0
-
0
-
CLK
MRS to new command
tMRD
2
-
2
-
2
-
2
-
2
-
CLK
Precharge to
data output Hi-Z
CAS Latency = 3
tPROZ3
3
-
3
-
3
-
3
-
3
-
CLK
CAS Latency = 2
tPROZ2
-
-
-
-
-
-
2
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
tREF
-
64
-
64
-
64
-
64
-
64
ms
Rev. 0.6 / Apr. 2003
9
HY57V643220C-I
DEVICE OPERATING OPTION TABLE
HY57V643220C(L)T-5I
HY57V643220C(L)T-55I
HY57V643220C(L)T-6I
HY57V643220C(L)T-7I
HY57V643220C(L)T-SI
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
200MHz(5ns)
3CLKs
3CLKs
38.5ns
11CLKs
3CLKs
4.5ns
1.5ns
183MHz(5.5ns)
3CLKs
3CLKs
38.5ns
10CLKs
3CLKs
5ns
2ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
183MHz(5.5ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5ns
2ns
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.5ns
2.0ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.5ns
2.0ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.5ns
2.0ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2.0ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2.0ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
2.5ns
Rev. 0.6 / Apr. 2003
10
HY57V643220C-I
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-READ-Single-WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge
power down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
Rev. 0.6 / Apr. 2003
11
HY57V643220C-I
PACKAGE INFORMATION
400mil 86pin Thin Small Outline Package
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.058(0.3960)
22.327(0.8790)
22.149(0.8720)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
1.194(0.0470)
0.991(0.0390)
Unit : mm(inch)
0.150(0.0059)
0.050(0.0020)
0.50(0.0197)
0.21(0.008)
0.18(0.007)
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