Document Outline
- Revision History
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION (Top View)
- ROW AND COLUMN ADDRESS TABLE
- PIN DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SIMPLIFIED COMMAND TRUTH TABLE
- WRITE MASK TRUTH TABLE
- OPERATION COMMAND TRUTH TABLE - I
- OPERATION COMMAND TRUTH TABLE - II
- OPERATION COMMAND TRUTH TABLE - III
- OPERATION COMMAND TRUTH TABLE - IV
- CKE FUNCTION TRUTH TABLE
- SIMPLIFIED STATE DIAGRAM
- POWER-UP SEQUENCE AND DEVICE INITIALIZATION
- MODE REGISTER SET (MRS)
- BURST DEFINITION
- BURST LENGTH & TYPE
- CAS LATENCY
- DLL RESET
- OUTPUT DRIVER IMPEDANCE CONTROL
- EXTENDED MODE REGISTER SET (EMRS)
- ABSOLUTE MAXIMUM RATINGS
- DC OPERATING CONDITIONS
- DC CHARACTERISTICS I
- DC CHARACTERISTICS II
- AC OPERATING CONDITIONS
- AC OPERATING TEST CONDITIONS
- AC Overshoot/Undershoot specifications for Address and Command pins
- AC Overshoot/Undershoot specifications for Data, Strobe and Mask Pins
- AC CHARACTERISTICS - I
- AC CHARACTERISTICS - II
- CAPACITANCE
- OUTPUT LOAD CIRCUIT
- PACKAGE INFORMATION
HY5DU281622ET
128M(8Mx16) GDDR SDRAM
HY5DU281622ET
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-
sibility for use of circuits described. No patent licenses are implied.
Rev. 0.5 / Jan. 2005 1
Rev. 0.5 / Jan. 2005
2
HY5DU281622ET
Revision History
Revision No.
History
Draft Date
Remark
0.1
Defined target spec.
July 2003
0.2
1) Insert Overshoot/Undershoot Specification
2) Insert tDSS/tDSH Parameter
Oct. 2003
0.3
tPDEX value Change
Mar. 2004
0.4
tRC_APCG changed to 12 clock from 11 clock at 166Mhz speed bin
Oct. 2004
0.5
166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz)
Jan. 2005
Rev. 0.5 / Jan. 2005
3
HY5DU281622ET
DESCRIPTION
The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which require high densities and high bandwidth.
The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
2.8V +/- 0.1V V
DD
and V
DDQ
power supply
supports 400/375/350/333/300MHz
2.5V +/- 5% V
DD
and V
DDQ
power supply
supports 275/250/200/166MHz
All inputs and outputs are compatible with SSTL_2
interface
JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II,
with 0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (UDQS,LDQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (UDM,LDM)
Programmable /CAS Latency 5, 4 and 3 are sup-
ported
Programmable Burst Length 2, 4 and 8 with both
sequential and interleave mode
Internal 4 bank operation with single pulsed /RAS
tRAS Lock-Out function are supported
Auto refresh and self refresh are supported
4096 refresh cycles / 32ms
Full strength, Half strength and Weak Impedance
driver options controlled by EMRS
ORDERING INFORMATION
Part No.
Power
Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU281622ET-25
VDD/VDDQ=2.8V
400MHz
800Mbps/pin
SSTL_2
400 x 875mil
2
66 Pin TSOP II
HY5DU281622ET-26
375MHz
750Mbps/pin
HY5DU281622ET-28
350MHz
700Mbps/pin
HY5DU281622ET-30
333MHz
666Mbps/pin
HY5DU281622ET-33
300MHz
600Mbps/pin
HY5DU281622ET-36
VDD/VDDQ=2.5V
275MHz
550Mbps/pin
HY5DU281622ET-4
250MHz
500Mbps/pin
HY5DU281622ET-5
200MHz
400Mbps/pin
Rev. 0.5 / Jan. 2005
4
HY5DU281622ET
PIN CONFIGURATION
(Top View)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
ROW AND COLUMN ADDRESS TABLE
ITEMS
8Mx16
Organization
2M x 16 x 4banks
Row Address
A0 - A11
Column Address
A0-A8
Bank Address
BA0, BA1
Auto Precharge Flag
A10
Refresh
4K
Rev. 0.5 / Jan. 2005
5
HY5DU281622ET
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry and exit. CKE is asynchronous for output disable. CKE must be main-
tained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and
CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during
SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd
is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
UDM, LDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ
and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data
on DQ8-Q15
UDQS, LDQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. LDQS corresponds to the data on
DQ0-Q7; UDQS corresponds to the data on DQ8-Q15
DQ0 ~ DQ15
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
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