Rev. 0.7 / Jun. 2004

HY5DU283222AF

Revision History

Revision

No.

History

Draft Date

Remark

0.1

Defined target spec.

Nov. 2002

0.11

500MHz speed bin added

Dec. 2002

0.2

Defined IDD specification

Feb. 2003

0.3

1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36
2) Changed VDD_min value of HY5DU283222AF-36 from 2.375V to 2.2V
3) Changed AC parameters value of HY5DU283222AF-28/33
- tRCDRD/tRP : from 6 tCK to 5 tCK
- tDAL : from 9 tCK to 8 tCK
- tRFC : from 19 tCK to 17 tCK
4) Changed IDD2N target specification
5) Changed tCK_max value of HY5DU283222AF-33/36 from 6ns to 10ns

Mar. 2003

0.4

Changed CAS Latency of HY5DU283222AF-28 from CL5 to CL4

June 2003

0.5

Changed tRAS_max Value from 120K to 100K in All Frequency

Aug. 2003

0.6

Insert Overshoot/ Under Specification
Insert tDSS/ tDSH parameter

Sep. 2003

0.7

Added 250MHz/ 200MHz speed bin

Jun. 2004

DESCRIPTION

The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.

The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.

FEATURES

2.5V +/- 5% V

and V

DDQ

power supply

supports 300 / 275 / 250 / 200 MHz

2.8V +/- 5% V

and V

DDQ

power supply

supports 500/450/400/350MHz

All inputs and outputs are compatible with SSTL_2
interface

12mm x 12mm, 144ball FBGA with 0.8mm pin pitch

Fully differential clock inputs (CK, /CK) operation

Double data rate interface

Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)

Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)

Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe

All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock

Write mask byte controls by DM (DM0 ~ DM3)

Programmable /CAS Latency 5, 4 and 3 supported

Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode

Internal 4 bank operations with single pulsed /RAS

tRAS Lock-Out function supported

Auto refresh and self refresh supported

4096 refresh cycles 32ms

Half strength and Matched Impedance driver option
controlled by EMRS

ORDERING INFORMATION

Part No.

Power

Supply

Clock

Frequency

Max Data Rate

interface

Package

HY5DU283222AF-2

2.8V

DDQ

2.8V

500MHz

1000Mbps/pin

SSTL_2

12mm x 12mm

144Ball FBGA

HY5DU283222AF-22

450MHz

900Mbps/pin

HY5DU283222AF-25

400MHz

800Mbps/pin

HY5DU283222AF-28

350MHz

700Mbps/pin

HY5DU283222AF-33

2.5V

DDQ

2.5V

300MHz

600Mbps/pin

HY5DU283222AF-36

275MHz

550Mbps/pin

HY5DU283222AF-4

250MHz

500Mbps/pin

HY5DU283222AF-5

200MHz

400Mbps/pin

HY5DU283222AF

Rev. 0.7 / Jun. 2004 3

Rev. 0.7 / Jun. 2004

HY5DU283222AF

PIN CONFIGURATION

(Top View)

ROW and COLUMN ADDRESS TABLE

Items

4Mx32

Organization

1M x 32 x 4banks

Row Address

A0 ~ A11

Column Address

A0 ~ A7

Bank Address

BA0, BA1

Auto Precharge Flag

Refresh

Note :

1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.

2. Ball L9(NC2) is reserved for A12.

3. Ball M10(NC3) is reserved for BA2.

DQS0

DM0

VSSQ

DQ3

DQ2

DQ0

DQ31

DQ29

DQ28

VSSQ

DM3

DQS3

DQ4

VDDQ

DQ1

VDDQ

DQ30

VDDQ

DQ27

DQ6

DQ5

VSSQ

VDD

VSSQ

DQ26

DQ25

DQ7

VDDQ

VDD

VSS

VSSQ

VSS

VSSQ

VSS

VDD

VDDQ

DQ24

DQ17

DQ16

VDDQ

VSSQ

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSSQ

VDDQ

DQ15

DQ14

DQ19

DQ18

VDDQ

VSSQ

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSSQ

VDDQ

DQ13

DQ12

DQS2

DM2

VSSQ

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSSQ

DM1

DQS1

DQ21

DQ20

VDDQ

VSSQ

VSS

Termal

VSS

Termal

VSS

Termal

VSS

Termal

VSSQ

VDDQ

DQ11

DQ10

DQ22

DQ23

VDDQ

VSSQ

VSS

VSSQ

VDDQ

DQ9

DQ8

/CAS

/W/E

VDD

VSS

A10

VDD

NC2

VSS

VDD

/RAS

BA1

A11

NC3

CLK

/CLK

/CS

BA0

A8/AP

CKE

VREF

Rev. 0.7 / Jun. 2004

HY5DU283222AF

PIN DESCRIPTION

PIN

TYPE

DESCRIPTION

CK, /CK

Input

Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).

CKE

Input

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.

/CS

Input

Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.

A0 ~ A11

Input

Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).

/RAS, /CAS, /WE

Input

Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.

DM0 ~ DM3

Input

Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.

DQS0 ~ DQS3

I/O

Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31

DQ0 ~ DQ31

I/O

Data input / output pin : Data Bus

Supply

Power supply for internal circuits and input buffers.

DDQ

SSQ

Supply

Power supply for output buffers for noise immunity.

REF

Supply

Reference voltage for inputs for SSTL interface.

No connection.

Rev. 0.7 / Jun. 2004

HY5DU283222AF

SIMPLIFIED COMMAND TRUTH TABLE

Command

CKEn-1

CKEn

RAS

CAS

ADDR

A8/

Note

Extended Mode Register Set

OP code

1,2

Mode Register Set

OP code

1,2

Device Deselect

No Operation

Bank Active

Read

Read with Autoprecharge

1,3

Write

Write with Autoprecharge

1,4

Precharge All Banks

1,5

Precharge selected Bank

Read Burst Stop

Auto Refresh

Self Refresh

Entry

Exit

Precharge Power

Down Mode

Entry

Exit

Active Power

Down Mode

Entry

Exit

Note :
1. DM(0~3) states are Don't Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A8/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.

( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

Rev. 0.7 / Jun. 2004

HY5DU283222AF

OPERATION COMMAND TRUTH TABLE - I

Current

State

/CS

/RAS

/CAS

/WE

Address

Command

Action

IDLE

DSEL

NOP or power down

NOP

NOP or power down

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

Row Activation

BA, AP

PRE/PALL

NOP

AREF/SREF

Auto Refresh or Self Refresh

OPCODE

MRS

Mode Register Set

ROW

ACTIVE

DSEL

NOP

BST

ILLEGAL

BA, CA, AP

READ/READAP

Begin read : optional AP

BA, CA, AP

WRITE/WRITEAP

Begin write : optional AP

BA, RA

ACT

ILLEGAL

BA, AP

PRE/PALL

Precharge

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

READ

DSEL

Continue burst to end

NOP

Continue burst to end

BST

Terminate burst

BA, CA, AP

READ/READAP

Term burst, new read:optional AP

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, AP

PRE/PALL

Term burst, precharge

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

WRITE

DSEL

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, AP

READ/READAP

Term burst, new read:optional AP

BA, CA, AP

WRITE/WRITEAP

Term burst, new write:optional AP

Rev. 0.7 / Jun. 2004

HY5DU283222AF

OPERATION COMMAND TRUTH TABLE - II

Current

State

/CS

/RAS

/CAS

/WE

Address

Command

Action

WRITE

BA, RA

ACT

ILLEGAL

BA, AP

PRE/PALL

Term burst, precharge

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

READ

WITH

AUTOPRE-

CHARGE

DSEL

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

4,10

BA, AP

PRE/PALL

ILLEGAL

4,10

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

WRITE

AUTOPRE-

CHARGE

DSEL

Continue burst to end

NOP

Continue burst to end

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

4,10

BA, AP

PRE/PALL

ILLEGAL

4,10

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

PRE-

CHARGE

DSEL

NOP-Enter IDLE after tRP

NOP

NOP-Enter IDLE after tRP

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

4,10

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

4,10

BA, RA

ACT

ILLEGAL

4,10

BA, AP

PRE/PALL

NOP-Enter IDLE after tRP

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

Rev. 0.7 / Jun. 2004

HY5DU283222AF

OPERATION COMMAND TRUTH TABLE - III

Current

State

/CS

/RAS

/CAS

/WE

Address

Command

Action

ROW

ACTIVATING

DSEL

NOP - Enter ROW ACT after tRCD

NOP

NOP - Enter ROW ACT after tRCD

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

4,10

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

4,10

BA, RA

ACT

ILLEGAL

4,9,10

BA, AP

PRE/PALL

ILLEGAL

4,10

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

WRITE

RECOVERING

DSEL

NOP - Enter ROW ACT after tWR

NOP

NOP - Enter ROW ACT after tWR

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

4,10

BA, AP

PRE/PALL

ILLEGAL

4,11

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

WRITE

RECOVERING

WITH

AUTOPRE-

CHARGE

DSEL

NOP - Enter precharge after tDPL

NOP

NOP - Enter precharge after tDPL

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

4,8,10

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

4,10

BA, RA

ACT

ILLEGAL

4,10

BA, AP

PRE/PALL

ILLEGAL

4,11

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

REFRESHING

DSEL

NOP - Enter IDLE after tRC

NOP

NOP - Enter IDLE after tRC

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

Rev. 0.7 / Jun. 2004

HY5DU283222AF

OPERATION COMMAND TRUTH TABLE - IV

Note :
1. H - Logic High Level, L - Logic Low Level, X - Don't Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.

Current

State

/CS

/RAS

/CAS

/WE

Address

Command

Action

WRITE

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, AP

PRE/PALL

ILLEGAL

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

MODE

ACCESSING

DSEL

NOP - Enter IDLE after tMRD

NOP

NOP - Enter IDLE after tMRD

BST

ILLEGAL

BA, CA, AP

READ/READAP

ILLEGAL

BA, CA, AP

WRITE/WRITEAP

ILLEGAL

BA, RA

ACT

ILLEGAL

BA, AP

PRE/PALL

ILLEGAL

AREF/SREF

ILLEGAL

OPCODE

MRS

ILLEGAL

Rev. 0.7 / Jun. 2004

HY5DU283222AF

CKE FUNCTION TRUTH TABLE

Note :
When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.

Current

State

CKEn-

CKEn

/CS

/RAS

/CAS

/WE

/ADD

Action

SELF

REFRESH

INVALID

Exit self refresh, enter idle after tSREX

ILLEGAL

NOP, continue self refresh

POWER
DOWN

INVALID

Exit power down, enter idle

ILLEGAL

NOP, continue power down mode

ALL BANKS

IDLE

See operation command truth table

Enter self refresh

Exit power down

ILLEGAL

NOP

ANY STATE

OTHER

THAN

ABOVE

See operation command truth table

ILLEGAL

INVALID

Rev. 0.7 / Jun. 2004

HY5DU283222AF

POWER-UP SEQUENCE AND DEVICE INITIALIZATION

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS
LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state,
where they will remain until driven in normal operation (by a read access). After all power supply and reference volt-
ages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable com-
mand.

Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Reg-
ister set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting
the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.

1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVC-

MOS low state. (All the other input pins may be undefined.

No power sequencing is specified during power up or power down given the following cirteria :

· VDD and VDDQ are driven from a single power converter output.
· VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation).
· VREF tracks VDDQ/2.
· A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the

input current from the VTT supply into any pin.

If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must
be adhered to during power up :

2. Start clock and maintain stable clock for a minimum of 200usec.

3. After stable power and clock, apply NOP condition and take CKE high.

4. Issue Extended Mode Register Set (EMRS) to enable DLL.

5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200

cycles(tXSRD) of clock are required for locking DLL)

6. Issue Precharge commands for all banks of the device.

Voltage description

Sequencing

Voltage relationship to avoid latch-up

VDDQ

After or with VDD

< VDD + 0.3V

VTT

After or with VDDQ

< VDDQ + 0.3V

VREF

After or with VDDQ

< VDDQ + 0.3V

Rev. 0.7 / Jun. 2004

HY5DU283222AF

Issue 2 or more Auto Refresh commands.

8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.

Power-Up Sequence

CODE

NOP

PRE

MRS

EMRS

PRE

NOP

MRS

AREF

ACT

VDD

VDDQ

VTT

VREF

/CLK

CLK

CKE

CMD

ADDR

A10

BA0, BA1

DQS

DQ'S

LVCMOS Low Level

tIS tIH

tVTD

T=200usec

tRP

tMRD

tRP

tRFC

tMRD

tXSRD*

READ

Non-Read

Command

Power UP

VDD and CK stable

Precharge All

EMRS Set

MRS Set

Reset DLL

(with A8=H)

Precharge All

2 or more

Auto Refresh

MRS Set

(with A8=L)

* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command

tMRD

Rev. 0.7 / Jun. 2004

HY5DU283222AF

MODE REGISTER SET (MRS)

The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low
signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE
must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write
the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.

BA1

BA0

A11

A10

RFU

CAS Latency

Burst Length

Sequential

Interleave

Reserved

Burst Type

Sequential

Interleave

CAS Latency

Reserved

Test Mode

Normal

Vendor

test mode

DLL Reset

Yes

BA0

MRS Type

MRS

EMRS

Rev. 0.7 / Jun. 2004

HY5DU283222AF

BURST DEFINITION

BURST LENGTH & TYPE

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is
set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a
given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both Read and Write bursts.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table

Burst Length

Starting Address (A2,A1,A0)

Sequential

Interleave

XX0

0, 1

XX1

1, 0

X00

0, 1, 2, 3

X01

1, 2, 3, 0

1, 0, 3, 2

X10

2, 3, 0, 1

X11

3, 0, 1, 2

3, 2, 1, 0

000

0, 1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

Rev. 0.7 / Jun. 2004

HY5DU283222AF

CAS LATENCY

The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 3 or 4 or 5 clocks.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident
with clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

DLL RESET

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.

OUTPUT DRIVER IMPEDANCE CONTROL

This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-
point environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2,
Class II, and Matched impedance driver, about 30% of Full drive strength.

Rev. 0.7 / Jun. 2004

HY5DU283222AF

EXTENDED MODE REGISTER SET (EMRS)

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-
tions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits
shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0)
and will retain the stored information until it is programmed again or the device loses power.

The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.

BA1

BA0

A11

A10

RFU*

DLL

DLL enable

Enable

Diable

BA0

MRS Type

MRS

EMRS

Output Driver Impedance Control

RFU*

Half (60%)

RFU*

Weak (40%)

RFU*

Semi Half (50%)

RFU*

Semi Weak (30%)

* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.

Rev. 0.7 / Jun. 2004

HY5DU283222AF

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note : 1. V

DDQ

must not exceed the level of V

2. V

(min) is acceptable -1.5V AC pulse width with

5ns of duration.

3. V

REF

is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same.

Peak to peak noise on V

REF

may not exceed ± 2% of the DC value.

4. Supports 300/275/250/200MHz
5. Supports 500/450/400/350MHz

DC CHARACTERISTICS I

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :

1. V

= 0 to 3.6V, All other pins are not tested under V

=0V. 2. D

OUT

is disabled, V

OUT

=0 to 2.7V

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

Storage Temperature

STG

-55 ~ 125

Voltage on Any Pin relative to V

, V

OUT

-0.5 ~ 3.6

Voltage on V

relative to V

-0.5 ~ 3.6

Voltage on V

DDQ

relative to V

DDQ

-0.5 ~ 3.6

Output Short Circuit Current

Power Dissipation

Soldering Temperature

Time

SOLDER

260

sec

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

2.2

2.5

2.625

1, 4

2.65

2.8

2.95

1, 5

Power Supply Voltage

DDQ

2.2

2.5

2.625

1, 4

2.65

2.8

2.95

1, 5

Input High Voltage

REF

+ 0.15

DDQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Termination Voltage

REF

- 0.04

REF

+ 0.04

Reference Voltage

REF

0.49*V

DDQ

0.5*V

DDQ

0.51*V

DDQ

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

-2

Output Leakage Current

-5

Output High Voltage

+ 0.76

= -15.2mA

Output Low Voltage

- 0.76

= +15.2mA

Rev. 0.7 / Jun. 2004

HY5DU283222AF

DC CHARACTERISTICS II

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :

1. I

DD1, IDD4

and I

DD5

depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of t

RFC

(Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.

Parameter

Symbol

Test Condition

Speed

Unit

Note

Operating Current

DD0

One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
DQ,DM and DQS inputs changing
twice per clock cycle; address and
control inputs changing once per
clock cycle

230

210

190

180

170

160

150

140

Operating Current

DD1

Burst length=4, One bank active
t

(min), I

=0mA

250

230

210

200

190

180

170

160

Precharge Standby
Current in Power
Down Mode

DD2P

CKE

(max), t

=min

Precharge Standby
Current in Non
Power Down Mode

DD2N

CKE

(min), /CS

(min),

= min, Input signals are

changed one time during 2clks

140

130

120

110

100

Active Standby Cur-
rent in Power Down
Mode

DD3P

CKE

(max), t

=min

Active Standby Cur-
rent in Non Power
Down Mode

DD3N

CKE

(min), /CS

(min),

=min, Input signals are

changed one time during 2clks

190

170

150

130

115

110

100

Burst Mode Operat-
ing Current

DD4

(min), I

=0mA

All banks active

750

700

650

590

500

450

370

Auto Refresh Current

DD5

RFC

(min),

All banks active

400

350

300

270

1,2

Self Refresh Current

DD6

CKE

0.2V

Operating Current -
Four Bank Operation

DD7

Four bank interleaving with BL=4,
Refer to the following page for
detailed test condition

1100 1000 900

800

700

600

Rev. 0.7 / Jun. 2004

HY5DU283222AF

AC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS

(TA=0 to 70

C, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

IH(AC)

REF

+ 0.35

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

IL(AC)

REF

- 0.35

Input Differential Voltage, CK and /CK inputs

ID(AC)

0.7

DDQ

+ 0.6

Input Crossing Point Voltage, CK and /CK inputs

IX(AC)

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

Parameter

Value

Unit

Reference Voltage

DDQ

x 0.5

Termination Voltage

DDQ

x 0.5

AC Input High Level Voltage (V

, min)

REF

+ 0.35

AC Input Low Level Voltage (V

, max)

REF

- 0.35

Input Timing Measurement Reference Level Voltage

REF

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

1.5

Input minimum Signal Slew Rate

V/ns

Termination Resistor (R

)

Series Resistor (R

)

Output Load Capacitance for Access Time Measurement (C

)

Rev. 0.7 / Jun. 2004

HY5DU283222AF

AC Overshoot/Undershoot specifications for Address and Command pins

AC Overshoot/Undershoot specifications for Data, Strobe and Mask Pins

Parameter

Specifications

Maximum peak amplitude allowwed for overshoot

1.5 V

Maximum peak amplitude allowwed for undershoot

1.5 V

The area between the overshoot signal and VDD must be less than or equal to(See below Fig)

4.5 V-nS

The area between the overshoot signal and GND must be less than or equal to(See below Fig)

4.5 V-nS

Parameter

Specifications

Maximum peak amplitude allowwed for overshoot

1.2 V

Maximum peak amplitude allowwed for undershoot

1.2 V

The area between the overshoot signal and VDD must be less than or equal to(See below Fig)

2.4 V-nS

The area between the overshoot signal and GND must be less than or equal to(See below Fig)

2.4 V-nS

+ 5

+ 3

+ 2

+ 1

- 1

- 2

- 3

+ 4

Time(nS)

Volt

(v)

Max. area = 4.5v-nS

Max. Amplitude = 1.5v

Ground

+ 5

+ 3

+ 2

+ 1

- 1

- 2

- 3

+ 4

Time(nS)

Volt

(v)

Max. area = 2.4 v-nS

Max. Amplitude = 1.2v

Ground

Rev. 0.7 / Jun. 2004

HY5DU283222AF

AC CHARACTERISTICS - I

(AC operating conditions unless otherwise noted)

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Row Cycle Time

Auto Refresh Row Cycle Time

RFC

Row Active Time

RAS

100K

Row Address to Column Address Delay for Read

RCDRD

Row Address to Column Address Delay for Write

RCDWR

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

Last Data-In to Read Command

DRL

Auto Precharge Write Recovery + Precharge Time

DAL

System Clock Cycle Time

CL=5

2.2

2.5

CL=4

Clock High Level Width

0.45

0.55

0.45

0.55

0.45

0.55

Clock Low Level Width

0.45

0.55

0.45

0.55

0.45

0.55

Data-Out edge to Clock edge Skew

-0.45

0.45

-0.45

0.45

-0.6

0.6

DQS-Out edge to Clock edge Skew

DQSCK

-0.45

0.45

-0.45

0.45

-0.6

0.6

DQS-Out edge to Data-Out edge Skew

DQSQ

0.25

0.35

Data-Out hold time from DQS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

1,6

Clock Half Period

tCH/L

min

tCH/L

min

tCH/L

min

1,5

Data Hold Skew Factor

QHS

0.25

0.35

Input Setup Time

0.6

0.75

Input Hold Time

0.6

0.75

Write DQS High Level Width

DQSH

0.45

0.55

0.4

0.6

0.4

0.6

Write DQS Low Level Width

DQSL

0.45

0.55

0.4

0.6

0.4

0.6

Clock to First Rising edge of DQS-In

DQSS

0.85

1.15

0.85

1.15

0.85

1.15

Data-In Setup Time to DQS-In (DQ & DM)

0.35

Data-In Hold Time to DQS-In (DQ & DM)

0.35

DQS falling edge to CK setup time

tDSS

0.3

Rev. 0.7 / Jun. 2004

HY5DU283222AF

Note :
1.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).

6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and
output pattern effects, and p-channel to n-channel variation of the output drivers.

7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.

DQS falling edge hold time from CK

tDSH

0.3

Read DQS Preamble Time

tRPRE

0.9

1.1

0.9

1.1

0.9

1.1

Read DQS Postamble Time

RPST

0.4

0.6

0.4

0.6

0.4

0.6

Write DQS Preamble Setup Time

WPRES

Write DQS Preamble Hold Time

WPREH

0.35

Write DQS Postamble Time

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Mode Register Set Delay

MRD

Exit Self Refresh to Any Execute Command

XSC

200

Power Down Exit Time

PDEX

2tCK

+ tIS

2tCK

+ tIS

2tCK

+ tIS

Average Periodic Refresh Interval

REFI

7.8

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Rev. 0.7 / Jun. 2004

HY5DU283222AF

AC CHARACTERISTICS - I (continue)

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Row Cycle Time

Auto Refresh Row Cycle
Time

RFC

Row Active Time

RAS

100K

Row Address to Column
Address Delay for Read

RCDRD

Row Address to Column
Address Delay for Write

RCDWR

Row Active to Row Active
Delay

RRD

Column Address to
Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

Last Data-In to Read
Command

DRL

Auto Precharge Write
Recovery + Precharge
Time

DAL

System Clock
Cycle Time

CL=5

CL=4

2.8

3.3

3.6

CL=3

4.5

Clock High Level Width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Clock Low Level Width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Data-Out edge to Clock
edge Skew

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

DQS-Out edge to Clock
edge Skew

DQSCK

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

DQS-Out edge to Data-
Out edge Skew

DQSQ

0.35

0.4

Data-Out hold time from
DQS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

tHPmin

-tQHS

1,6

Clock Half Period

tCH/L

min

tCH/L

min

tCH/L

min

tCH/L

min

tCH/L

min

1,5

Data Hold Skew Factor

QHS

0.35

0.4

Rev. 0.7 / Jun. 2004

HY5DU283222AF

Note :
1.

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

Data latched at both rising and falling edges of Data Strobes(DQS0~DQS3) : DQ, DM(0~3).

Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

Input Setup Time

0.75

Input Hold Time

0.75

Write DQS High Level
Width

DQSH

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Write DQS Low Level
Width

DQSL

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Clock to First Rising edge
of DQS-In

DQSS

0.85

1.15

0.85

1.15

0.85

1.15

0.85

1.15

0.85

1.15

Data-In Setup Time to
DQS-In (DQ & DM)

0.35

0.4

0.45

Data-In Hold Time to
DQS-In (DQ & DM)

0.35

0.4

0.45

DQS falling edge to CK
setup time

tDSS

0.3

DQS falling edge hold
time from CK

tDSH

0.3

Read DQS Preamble Time

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

Read DQS Postamble
Time

RPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Write DQS Preamble
Setup Time

WPRES

Write DQS Preamble Hold
Time

WPREH

0.35

Write DQS Postamble
Time

WPST

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

Mode Register Set Delay

MRD

Exit Self Refresh to Any
Execute Command

XSC

200

Power Down Exit Time

PDEX

2tCK

+ tIS

2tCK

+ tIS

1tCK

+ tIS

1tCK

+ tIS

1tCK

+ tIS

Average Periodic Refresh
Interval

REFI

7.8

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transitions through the DC region must be monotonic.

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