HY5DU283222F
128M(4Mx32) DDR SDRAM
HY5DU283222F
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any respon-
sibility for use of circuits described. No patent licenses are implied.
Rev. 1.2/Sep. 02 1
Rev. 1.2/Sep. 02
2
HY5DU283222F
Revision History
9. Rev.1.2 (Sep. 02)
1) Changed V
DD
/V
DDQ
value
- 350/375MHz : Changed from 2.66V/2.80V/2.94V to 2.76V/2.90V/3.05V (min/typ/max)
2) IDD4 SPEC at 200MHz changed 300mA to 370mA
8. Rev.1.1 (May. 02)
1) Defined tPDEX parameter
2) Added AC CHARACTERISTICS-II table
7. Rev.1.0 (May. 02)
1) Input leakage current changed from +/-5uA to +/-2uA
6. Rev 0.9 (Dec.01)
1) IDD4 SPEC changed 370mA to 300mA
2) 275/300MHz IDD SPEC defined
3) tRC/tRFC/tRAS SPEC. updated
4) Power dissipation SPEC. changed from 1W to 2W
5. Rev 0.8 (Dec.01)
1) 200MHz tCK Max. changed from 7ns to 10ns
2) Device operation and timing diagram removed
3) tRCD/tRP at 275MHz changed from 6clk to 5clk
4) tRC/tRFC SPEC newly defined
5) 375/350MHz AC parameters defined
4. Rev 0.7 (Nov.01)
1) Pin capacitance defined
a) CK, /CK, All other input-only pins : min 1pF, Max 3PF
b) DQ, DQS, DM : min 3pF, Max 5pF
3. Rev 0.6 (Oct.01)
1) 222Mhz speed bin removed
2) IDD Specification of 200/250MHz part defined
3) AC parameters of 275MHz part defined
4) ViH/ViL changed Vref+/- 0.35 into Vref +/- 0.45
5) Part number changed from HY6U22F to HY5DU283222F
2. Rev 0.5 (Jun. 01)
1) tAC/tDQSCK, tRCD/tRP parameters each speed changed as the followings
a) tAC : changed from 0.7ns to 0.9ns at 3.3/4/4.5ns
b) tDQSCK : changed from 0.6ns to 0.7ns at 3.3/4/4.5ns
c) tRCD/tRP : changed from 5clk to 6clk at 3.3ns and 4clk to 5clk at 4/4.5ns
1. Rev 0.4 ( May.01)
1) Part Number changed from HY5DU283222F to HY6U22F
DESCRIPTION
The Hynix HY5DU283222F is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
2.5V +/- 5% V
DD
and V
DDQ
power supply
supported up to 300/275/250/200MHz
2.9V +/- 5% V
DD
and V
DDQ
power supply
supported up to 350/375MHz
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 3 and 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
ORDERING INFORMATION
Part No.
Power Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU283222F-26
V
DD
2.9V
V
DDQ
2.9V
375MHz
750Mbps/pin
SSTL_2
12mm x 12mm
144Ball FBGA
HY5DU283222F-28
350MHz
700Mbps/pin
HY5DU283222F-33
V
DD
2.5V
V
DDQ
2.5V
300MHz
600Mbps/pin
HY5DU283222F-36
275MHz
550Mbps/pin
HY5DU283222F-4
250MHz
500Mbps/pin
HY5DU283222F-5
200MHz
400Mbps/pin
HY5DU283222F
Rev. 1.2/Sep. 02 3
Rev. 1.2/Sep. 02
4
HY5DU283222F
PIN CONFIGURATION
ROW and COLUMN ADDRESS TABLE
Items
4Mx32
Organization
1M x 32 x 4banks
Row Address
A0 ~ A11
Column Address
A0 ~ A7
Bank Address
BA0, BA1
Auto Precharge Flag
A8
Refresh
4K
2
3
4
5
6
7
8
9
10
11
12
13
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
/CAS
/RAS
/CS
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
/W/E
NC
NC
VDDQ
DM0
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
NC
VSSQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
VDDQ
DQ3
VSSQ
VSSQ
VSS
Thermal
A10
A2
A1
DQ1
DQ2
VDD
VSS
VDD
A11
A3
VDDQ
DQ0
VDD
VSS
VDD
A9
A4
VDDQ
DQ31
VSSQ
VSSQ
NC
2
A5
A6
DQ30
DQ29
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
3
A7
VDDQ
DQ28
VSSQ
VDD
VDD
CLK
A8/AP
NC
VSSQ
DQ26
VDDQ
NC
/CLK
CKE
VDDQ
DM3
DQ25
DQ24
NC
MCL,
DSF
VREF
DQ27
DQS3
VDDQ
VDDQ
NC
VDDQ
VDDQ
DQ14
DQ12
DQS1
DQ10
DQ8
DQ15
DQ13
DM1
DQ11
DQ9
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
VSS
VSS
VSS
14
1
P
A
Note :
1. Outer ball, A1~A14, P1~P14, A1~P1, A14~P14 are depopulated.
2. Ball L9(NC2) is reserved for A12.
3. Ball M10(NC3) is reserved for BA2.
Rev. 1.2/Sep. 02
5
HY5DU283222F
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM0 ~ DM3
Input
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
DQS0 ~ DQS3
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data. DQS0 corresponds to the data on
DQ0-Q7; DQS1 corresponds to the data on DQ8-Q15; DQS2 corresponds to the data on
DQ16-Q23; DQS3 corresponds to the data on DQ24-Q31
DQ0 ~ DQ31
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
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