HY5DU283222Q(Rev.1.2).fm
HY5DU283222Q
128M(4Mx32) DDR SDRAM
HY5DU283222Q
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2/Oct. 02 1
Rev. 1.2/Oct. 02
2
HY5DU283222Q
Revision History
9. Revision 1.2 (Oct. 02)
1) Added 200MHz with CL3 at 250/222MHz speed bin
2) 200MHz IDD4 SPEC changed from 300mA to 370mA
8. Revision 1.1 (May. 02)
1) Input leakage current changed from +/-5uA to +/-2uA
7. Revision 1.0 (May. 02)
1) 200/183MHz of tCK max changed from 8ns to 10ns
6. Revision 0.9 (Dec. 01)
1) Power dissipation SPEC. changed from 1W to 2W
2) 200MHz IDD4 SPEC changed from 370mA to 300mA
3) Output Load circuit updated
5. Revision 0.8 (Nov. 01)
1) tRCD/tRP of 3clocks at 183/200MHz at single bank operation defined
2) tCK Max of 200/183MHz part changed from 7ns to 8ns
4. Revision 0.7 (Oct. 01)
1) Changed some AC parameters
a) tQHS : Changed from 0.75ns to 0.45ns at 200/183MHz
b) tDS/tDH : Changed from 0.5ns to 0.45ns
3. Revision 0.6 (Oct. 01)
1) Changed VIH/VIL from Vref +/- 0.35V to Vref +/- 0.45V
2) Change tCK_max from 5.5ns to 6ns at 250/222MHz and from 10ns to 7ns at 200/183MHz
2. Revision 0.5 (Aug. 01)
1) Removed 166MHz part from speed bin
2) Defined IDD specification
3) Defined AC parameters of 250MHz part
4) Changed Pin Capacitance
a) Input Clock capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max)
b) All other Input-only pins capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max)
c) Input/Output capacitance (DQ, DQS, DM) : Changed from 4/5pF to 3.7/4.7pF (min/max)
5) Changed some AC parameters
a) tIS/tIH : Changed from 0.9ns to 1.0ns
b) tDS/tDH : Changed from 0.45ns to 0.5ns
6) Changed VIH/VIL from Vref +/- 0.31V to Vref +/- 0.35V
1. Revision 0.4 (Jun. 01)
1) Changed some AC parameters
a) tAC : Changed from 0.7ns to 0.9ns
b) tDQSCK : Changed from 0.6ns to 0.7ns
c) tRCD/tRP : Changed from 4clks to 5clks at 222MHz and from 3clks to 4clks at 200/183MHz
DESCRIPTION
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for
the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V
5%
All inputs and outputs are compatible with SSTL_2
interface
JEDEC standard 20mm x 14mm 100pin LQFP with
0.65mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 3 and 4 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles / 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
ORDERING INFORMATION
Part No.
Power Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU283222Q-4
V
DD/
V
DDQ
= 2.5V
250MHz
500Mbps/pin
SSTL_2
20mm x 14mm
100pin LQFP
HY5DU283222Q-45
222MHz
444Mbps/pin
HY5DU283222Q-5
200MHz
400Mbps/pin
HY5DU283222Q-55
183MHz
366Mbps/pin
HY5DU283222Q
Rev. 1.2/Oct. 02 3
Rev. 1.2/Oct. 02
4
HY5DU283222Q
PIN CONFIGURATION
ROW and COLUMN ADDRESS TABLE
Items
4Mx32
Organization
1M x 32 x 4banks
Row Address
A0 ~ A11
Column Address
A0 ~ A7
Bank Address
BA0, BA1
Auto Precharge Flag
A8
Refresh
4K
20mm x 14mm
100Pin QFP
0.65mm Pitch
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
/WE
/CAS
/RAS
/CS
BA0
BA1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A0
A1
A2
A3
VDD
A10
A11
NC
NC
NC
NC
NC
NC
NC
A9
VS
S
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CLK
/CLK
CKE
DSF, MCL
A8/AP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQ
2
VS
SQ
DQ
1
DQ
0
VDD
VDDQ
DQ
S
NC
VS
SQ
NC
NC
NC
NC
NC
VDDQ
VS
S
DQ
31
DQ
30
VS
SQ
DQ
29
TOP VIEW
Rev. 1.2/Oct. 02
5
HY5DU283222Q
PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE
must be maintained high throughout READ and WRITE accesses. Input buffers, excluding
CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are
disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW
level after Vdd is applied.
/CS
Input
Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A11
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address
and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A8 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A8 LOW) or all banks (A8
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mode register is loaded during the MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM0 ~ DM3
Input
Input Data Mask: DM(0~3) is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is sam-
pled on both edges of DQS. Although DM pins are input only, the DM loading matches the
DQ and DQS loading. DM0 corresponds to the data on DQ0-Q7; DM1 corresponds to the
data on DQ8-Q15; DM2 corresponds to the data on DQ16-Q23; DM3 corresponds to the
data on DQ24-Q31.
DQS
I/O
Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data.
DQ0 ~ DQ31
I/O
Data input / output pin : Data Bus
V
DD
/V
SS
Supply
Power supply for internal circuits and input buffers.
V
DDQ
/V
SSQ
Supply
Power supply for output buffers for noise immunity.
V
REF
Supply
Reference voltage for inputs for SSTL interface.
NC
NC
No connection.
PDF 
ZIP