This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 12 / Apr.2001 Hynix Semiconductor
HY628100B Series
128Kx8bit CMOS SRAM
Document Title
128K x8 bit 5.0V Low Power CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
10 Initial Revision History Insert Jul.14.2000 Final
11 Marking Information Add Dec.04.2000 Final
Revised
-
E.T (-25~85
C), I.T (-40~85
C) Part Insert
-
AC Test Condition Add : 5pF Test Load
12 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
HY628100B Series
Rev 12 / Apr.2001
2
DESCRIPTION
The HY628100B is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100B uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(L/LL-part)
-. 2.0V(min) data retention
Standard pin configuration
-. 32pin SOP - 525mil
-. 32pin TSOPI - 8X20(Standard)
Product
Voltage
Speed
Operation
Standby Current(uA) Temperature
No
(V)
(ns)
Current/Icc(mA)
L
LL
(
C)
HY628100B
4.5~5.5 50*/55/70/85
10
100
20
0~70
HY628100B-E 4.5~5.5 50*/55/70/85
10
100
30
-25~85
HY628100B-I 4.5~5.5 50*/55/70/85
10
100
30
-40~85
Comment : 50ns is available with 30pF test load.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
/WE
A13
A8
A9
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
CS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
DQ3
DQ2
DQ1
A0
A1
A2
A3
A11
A9
A8
A13
/WE
CS2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4
/CS1
SOP TSOP-I(Standard)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name
Pin Function
/CS1
Chip Select 1
CS2
Chip Select 2
/WE
Write Enable
/OE
Output Enable
A0 ~ A16
Address Inputs
I/O1 ~ I/O8
Data Inputs / Outputs
Vcc
Power(4.5V~5.5V)
Vss
Ground
MEMORY ARRAY
128K x 8
ROW
DECODER
SENSE AMP
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
COLUMN
DECODER
ADD INPUT
BUFFER
A0
A16
CONTROL
LOGIC
/CS1
CS2
/OE
/WE
HY628100B Series
Rev 12 / Apr.2001
2
ORDERING INFORMATION
Part No.
Speed
Power
Temp
Package
HY628100BLG
55/70/85
L-part 0~70
C
SOP
HY628100BLLG
55/70/85
LL-part 0~70
C
SOP
HY628100BLG-E
55/70/85
L-part -25~85
C SOP
HY628100BLLG-E
55/70/85
LL-part -25~85
C SOP
HY628100BLG-I
55/70/85
L-part -40~85
C SOP
HY628100BLLG-I
55/70/85
LL-part -40~85
C SOP
HY628100BLT1
55/70/85
L-part 0~70
C
TSOP-I(Standard)
HY628100BLLT1
55/70/85
LL-part 0~70
C
TSOP-I(Standard)
HY628100BLT1-E
55/70/85
L-part -25~70
C TSOP-I(Standard)
HY628100BLLT1-E
55/70/85
LL-part -25~70
C TSOP-I(Standard)
HY628100BLT1-I
55/70/85
L-part -40~70
C TSOP-I(Standard)
HY628100BLLT1-I
55/70/85
LL-part -40~70
C TSOP-I(Standard)
Comment : 50ns is available with 30pF test load.
ABSOLUTE MAXIMUM RATING (1)
Symbol
Parameter
Rating
Unit
Remark
Vcc, V
IN,
V
OUT
Power Supply, Input/Output Voltage
-0.5 to 7.0
V
T
A
Operating Temperature
0 to 70
C
HY628100B
-25 to 85
C
HY628100B-E
-40 to 85
C
HY628100B-I
T
STG
Storage Temperature
-65 to 125
C
P
D
Power Dissipation
1.0
W
I
OUT
Data Output Current
50
mA
T
SOLDER
Lead Soldering Temperature & Time
260
10
C
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these
or any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
TRUTH TABLE
/CS1 CS2 /WE /OE
Mode
I/O
Power
H
X
X
X
Deselected
High-Z
Standby
X
L
X
X
Deselected
High-Z
Standby
L
H
H
H
Output Disabled
High-Z
Active
L
H
H
L
Read
Data Out
Active
L
H
L
X
Write
Data In
Active
Note :
1. H=V
IH
, L=V
IL
, X=don't care( V
IH or
V
IL )
HY628100B Series
Rev 12 / Apr.2001
3
RECOMMENDED DC OPERATING CONDITION
T
A
= 0
C to 70
C / -25
C to 85
C (E) / -40
to 85
(I), unless otherwise specified
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.5
V
V
IL
Input Low Voltage
-0.5
(1)
-
0.8
V
Note :
1. V
IL
= -1.5V for pulse width less than 30ns and not 100% tested
DC ELECTRICAL CHARACTERISTICS
Vcc = 4.5V~5.5V, T
A
= 0
C to 70
C / -25
C to 85
C (E) / -40
to 85
(I), unless otherwise specified
Symbol
Parameter
Test Condition
Min.
Typ. Max. Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2 = V
IL
or
/
OE
=
V
IH
or /WE = V
IL
-1
-
1
uA
Icc
Operating Power Supply
Current
/CS1 = V
IL
, CS2 = V
IH,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
-
-
10
mA
I
CC1
Average Operating
/CS1 = V
IL
, CS2 = V
IH
,
Current
V
IN
= V
IH
or V
IL
Cycle Time = Min, 100% duty,
I
IO
= 0mA
-
-
50
mA
I
SB
TTL Standby Current
(TTL Input)
/CS1 = V
IH
or CS2 = V
IL
V
IN
= V
IH
or V
IL
-
-
2
mA
I
SB1
Standby
HY628100B
/CS1 > Vcc - 0.2V or L
-
2
100
uA
Current
CS2 < 0.2V ,
LL
-
1
20
uA
(CMOS Input) HY628100B-E/I V
IN
> Vcc - 0.2V or
L
-
2
100
uA
V
IN
< Vss + 0.2V
LL
-
1
30
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1mA
2.4
-
-
V
Note : Typical values are at Vcc = 5.0V, T
A
= 25
C
CAPACITANCE
Temp = 25
C, f= 1.0MHz
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Note : These parameters are sampled and not 100% tested
HY628100B Series
Rev 12 / Apr.2001
4
AC CHARACTERISTICS
Vcc = 4.5V~5.5V, T
A
= 0
C to 70
C / -25
C to 85
C (E) / -40
to 85
(I), unless otherwise specified
-55
-70
-85
Min. Max. Min. Max. Min
Max.
1 tRC
Read Cycle Time
55
-
70
-
85
-
ns
2 tAA*
Address Access Time
-
55
-
70
-
85
ns
3 tACS* Chip Select Access Time
-
55
-
70
-
85
ns
4 tOE
Output Enable to Output Valid
-
25
-
35
-
45
ns
5 tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
ns
6 tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
ns
7 tCHZ
Chip Deselection to Output in High Z
0
20
0
25
0
30
ns
8 tOHZ
Out Disable to Output in High Z
0
20
0
25
0
30
ns
9 tOH
Output Hold from Address Change
10
-
10
-
10
-
ns
10 tWC
Write Cycle Time
55
-
70
-
85
-
ns
11 tCW
Chip Selection to End of Write
45
-
60
-
70
-
ns
12 tAW
Address Valid to End of Write
45
-
60
-
70
-
ns
13 tAS
Address Set-up Time
0
-
0
-
0
-
ns
14 tWP
Write Pulse Width
40
-
50
-
55
-
ns
15 tWR
Write Recovery Time
0
-
0
-
0
-
ns
16 tWHZ Write to Output in High Z
0
20
0
25
0
30
ns
17 tDW
Data to Write Time Overlap
25
-
30
-
40
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
5
-
ns
Comment : tAA* and tACS* can meet 50ns with 30pF test load.
AC TEST CONDITIONS
T
A
= 0
C to 70
C / -25
C to 85
C (E) / -40
to 85
(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW
CL = 5pF + 1TTL Load
Others
CL = 100pF + 1TTL Load
CL* = 30pF + 1TTL Load
Comment
* : Test load is 30pF for 50ns
AC TEST LOADS
CL(1)
TTL
Note : Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
Symbol
Parameter
#
Unit
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