This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.00 / Jan.02 Hynix Semiconductor
HY62KF08802B Series
1Mx8bit full CMOS SRAM
Document Title
1M x 8bit 2.7 ~ 3.6V Super low Power FCMOS Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Draft Jan.19.2002 Preliminary
HY62KF08802B Series
Rev.00 / Jan.02
2
DESCRIPTION
The HY62KF08802B is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
1M words by 8bits. The HY62KF08802B uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
-. 44pin 400mil TSOP-II (Forward)
Standby
Current(uA)
Product No.
Voltage
(V)
Speed (ns)
Operation
Current/Icc(mA)
SL
LL
Temperature
(
C)
HY62KF08802B-I 2.7~3.6
55/70
2
12
30
-40~85
Note 1. I : Industrial
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS1, CS2 Chip Select
A0~A19
Address Inputs
/WE
Write Enable
Vcc
Power (2.7~3.6V)
/OE
Output Enable
Vss
Ground
I/O1~I/O8 Data Inputs/Outputs
NC
No Connection
A5
A6
/OE
CS2
A8
NC
NC
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
NC
NC
A9
A10
A11
A12
A13
A14
A7
A4
A3
A2
A1
A0
/CS1
NC
NC
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
NC
NC
/WE
A19
A18
A17
A16
A15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TSOPII
(Forward)
MEMORY ARRAY
1M x 8
ROW
DECODER
SENSE AMP
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT
BUFFER
A0
A19
/CS1
CS2
/OE
/WE
HY62KF08802B Series
Rev.00 / Jan.02
2
ORDERING INFORMATION
Part No.
Speed
Power Temp
.
Package
HY62KF08802B-SD(I)
55/70
SL-part
I
TSOP-II
HY62KF08802B-DD(I)
55/70
LL-part
I
TSOP-II
Note 1. I : Industrial
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Unit
Remark
V
IN,
V
OUT
Input/Output Voltage
-0.3 to V
CC
+0.3V
V
Vcc
Power Supply
-0.3 to 4.6
V
T
A
Operating Temperature
-40 to 85
C
HY62KF08802B-I
T
STG
Storage Temperature
-55 to 150
C
P
D
Power Dissipation
1.0
W
T
SOLDER
Ball Soldering Temperature & Time
260
10
C
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 CS2 /WE /OE
Mode
I/O Pin (I/O1~I/O8)
Power
H
X
X
X
Deselected
High-Z
X
L
X
X
Deselected
High-Z
Standby
L
H
H
H
Output Disabled
High-Z
Active
L
H
H
L
Read
D
OUT
Active
L
H
L
X
Write
D
IN
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care (V
IL or
V
IH
)
HY62KF08802B Series
Rev.00 / Jan.02
3
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min.
Typ
Max.
Unit
Vcc
Supply Voltage
2.7
3.0 or 3.3
3.6
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
1.
-
0.6
V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
T
A
= -40
C to 85
C
Sym
Parameter
Test Condition
Min Typ
1.
Max Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS1 = V
IH
or
CS2 = V
IL
or
/
OE
=
V
IH
or /WE = V
IL
-1
-
1
uA
Icc
Operating Power Supply Current
/CS1 = V
IL
, CS2 = V
IH
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
4
mA
55ns
25
mA
3.0~
3.6V 70ns
20
mA
55ns
20
mA
/CS1 = V
IL,
CS2 = V
IH
V
IN
= V
IH
or V
IL,
Cycle
Time = Min,
100% Duty, I
I/O =
0mA
2.7~
3.3V 70ns
15
mA
I
CC1
Average Operating Current
/CS1 < 0.2V
,
CS2
> Vcc-0.2V
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
3
mA
I
SB
Standby Current
(TTL Input)
/CS1 = V
IH,
CS2 = V
IL
V
IN
= V
IH
or V
IL
300
uA
SL
0.2
12
uA
3.0~
3.6V
LL
0.2
30
uA
SL
0.2
12
uA
I
SB1
Standby Current
(CMOS Input)
/CS1 > Vcc - 0.2V,
CS2 < Vss + 0.2V
,
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
2.7~
3.3V
LL
0.2
25
uA
V
OL
Output Low
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High
I
OH =
-1.0mA
2.4
-
-
V
Note
1. Typical values are at Vcc = 3.0V T
A
= 25
C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25
C, f= 1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance (Add, /CS1,CS2, /WE, /OE)
V
IN
= 0V
8
pF
C
OUT
Output Capacitance (I/O)
V
I/O
= 0V
10
pF
Note : These parameters are sampled and not 100% tested
HY62KF08802B Series
Rev.00 / Jan.02
4
AC CHARACTERISTICS
T
A
= -40
C to 85
C, unless otherwise specified
55ns
70ns
# Symbol
Parameter
Min. Max. Min. Max.
Unit
1 tRC
Read Cycle Time
55
-
70
-
ns
2 tAA
Address Access Time
-
55
-
70
ns
3 tACS
Chip Select Access Time
-
55
-
70
ns
4 tOE
Output Enable to Output Valid
-
30
-
35
ns
5 tCLZ
Chip Select to Output in Low Z
10
-
10
-
ns
6 tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
7 tCHZ
Chip Deselection to Output in High Z
0
20
0
25
ns
8 tOHZ
Out Disable to Output in High Z
0
20
0
25
ns
9 tOH
Output Hold from Address Change
10
-
10
-
ns
10 tWC
Write Cycle Time
55
-
70
-
ns
11 tCW
Chip Selection to End of Write
50
-
60
-
ns
12 tAW
Address Valid to End of Write
50
-
60
-
ns
13 tAS
Address Set-up Time
0
-
0
-
ns
14 tWP
Write Pulse Width
45
-
50
-
ns
15 tWR
Write Recovery Time
0
-
0
-
ns
16 tWHZ
Write to Output in High Z
0
20
0
20
ns
17 tDW
Data to Write Time Overlap
25
-
30
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
ns
AC TEST CONDITIONS
T
A
= -40
C to 85
C, unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW
CL = 5pF + 1TTL Load
Output Load
Others
CL = 30pF + 1TTL Load
AC TEST LOADS
D
OUT
1728 Ohm
CL(1)
1029 Ohm
V
TM
=2.8V
Note
1. Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
HY62KF08802B Series
Rev.00 / Jan.02
5
TIMING DIAGRAM
READ CYCLE 1 (Note 1,4)
READ CYCLE 2 (Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out
READ CYCLE 3 (Note 1,2,4)
/CS1
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
CS2
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /CS1 and CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/OE
tAA
tACS
tOE
tCLZ
(3)
tOLZ
(3)
tOH
tCHZ
(3)
tOHZ
(3)
HY62KF08802B Series
Rev.00 / Jan.02
6
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2.
2. tWR is measured from the earlier of /CS1or /WE going high or CS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, CS2 high transition occur simultaneously with the /WE low transition or after the /WE
transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active. CS2 in low for the standby, high for active.
Data Valid
ADDR
Data
Out
/
CS1
CS2
/
WE
tWC
tCW
tWR
(2)
tAW
tWP
Data In
High
-
Z
tAS
tWHZ
(3,7)
tDW
tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/
CS1
CS2
/
WE
tWC
tCW
tWR
(2)
tAW
tWP
Data In
tDW
tDH
High
-
Z
High
-
Z
tAS
HY62KF08802B Series
Rev.00 / Jan.02
7
DATA RETENTION ELECTRIC CHARACTERISTIC
T
A
= -40
C to 85
C
Symbol
Parameter
Test Condition
Min Typ
1.
Max Unit
V
DR
Vcc for Data Retention
/CS > Vcc - 0.2V,
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
1.2
-
3.6
V
SL
-
0.1
6
uA
Iccdr
Data Retention Current
Vcc=1.5V,
/CS > Vcc - 0.2V or
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
LL
-
0.1
20
uA
tCDR
Chip Deselect to Data
Retention Time
0
-
-
ns
tR
Operating Recovery Time
See Data Retention Timing Diagram
tRC
-
-
ns
Notes:
1. Typical values are under the condition of T
A
= 25
C.
2. Typical value are sampled and not 100% tested
DATA RETENTION TIMING DIAGRAM 1
/CS1
VDR
CS1>VCC-0.2V
tCDR
tR
VSS
VCC
2.7V
VIH
DATA RETENTION MODE
DATA RETENTION TIMING DIAGRAM 2
0.4V
VDR
tCDR
tR
VSS
VCC
CS2
2.7V
DATA RETENTION MODE
CS2<0.2V
HY62KF08802B Series
Rev.00 / Jan.02
8
PACKAGE INFORMATION
44pin 400mil Thin Small Outline Package Forward (D)
#22
#23
#44
#1
0.016(0.4)
0.012(0.3)
0.0315(0.800)
BSC
0.0059(0.150)
0.002(0.050)
0.047(1.194)
0.039(0.991)
0.721(18.313)
0.729(18.517)
0.10MAX
0.004MAX
0.404(10.262)
0.396(10.058)
0.0235(0.597)
0.0160(0.406)
0.0083(0.21)
0.0047(0.120)
0~5
UNIT : INCH(mm)
0.462(11.735)
0.470(11.938)
Min.
Max.
HY62KF08802B Series
Rev.00 / Jan.02
9
MARKING INFORMATION
h
y
n
i
x
y
y
w
w
H
Y
6
2
K
F
8
8
0
2
B
c
s
s
K
O
R
E
A
TSOP-II
(Forward)
Package
Marking Example
Index
hynix
: hynix Logo
yy
: Year ( ex : 02 = year 2002, 03 = year 2002 )
ww
: Work Week ( ex : 12 = ww12 )
p
: Process Code
HY62KF8802B
: Part Name
c
: Power Consumption
- D
: Low Low Power
- S
: Super Low Power
ss
: Speed
- 55
: 55ns
- 70
: 70ns
t
: Temperature
- I
: Industrial ( -40 ~ 85
C )
KOREA
: Origin Country
Note
- Capital Letter
: Fixed Item
- Small Letter
: Non-fixed Item (Except hynix)
p
t
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