This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev.02 / Jun.01 Hynix Semiconductor
HY62SF16406C Series
256Kx16bit full CMOS SRAM
Document Title
256K x16 bit 1.7 ~ 2.3V Super Low Power FCMOS Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Draft Dec.20.2000 Final
01 Changed Logo Mar.23.2001 Final
02 Changed Isb1 values Jun.07.2001 Final
HY62SF16406C Series
Rev.02 / Jun.01
2
DESCRIPTION
The HY62SF16406C is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62SF16406C uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
-. 48-ball uBGA
Standby
Current(uA)
Product No.
Voltage
(V)
Speed (ns)
Operation
Current/Icc(mA)
LL
SL
Temperature
(
C)
HY62SF16406C-I 1.7~2.3
85
3
10
3
-40~85
Note 1. I : Industrial
2. Current value is max.
PIN CONNECTION BLOCK DIAGRAM
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS1, CS2 Chip Select
I/O1~I/O16
Data Inputs/Outputs
/WE
Write Enable
A0~A17
Address Inputs
/OE
Output Enable
Vcc
Power (1.7~2.3V)
/LB
Lower Byte Control (I/O1~I/O8) Vss
Ground
/UB
Upper Byte Control (I/O9~I/O16) NC
No Connection
MEMORY ARRAY
256K x 16
ROW
DECODER
SENSE AMP
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
I/O9
I/O16
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT
BUFFER
A17
/CS1
/OE
/LB
/UB
/WE
CS2
1
2
3
4
5
6
A
B
C
D
E
F
G
H
FBGA
/LB
IO9
IO10
/OE A0 A1 A2 CS2
/UB A3 A4 /CS1 IO1
IO11 A5 A6 IO2 IO3
Vss IO12 A17 A7 IO4 Vcc
Vcc IO13 NC A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 NC A12 A13 /WE IO8
NC A8 A9 A10 A11 NC
HY62SF16406C Series
Rev.02 / Jun.01
2
ORDERING INFORMATION
Part No.
Speed
Power
Temp
.
Package
HY62SF16406C-DM85I
85
LL-part
I
uBGA
HY62SF16406C-SM85I
85
SL-part
I
uBGA
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Unit
Remark
V
IN,
V
OUT
Input/Output Voltage
-0.3 to 2.6
V
Vcc
Power Supply
-0.3 to 3.6
V
T
A
Operating Temperature
-40 to 85
C
HY62SF16406C-I
T
STG
Storage Temperature
-55 to 150
C
P
D
Power Dissipation
1.0
W
T
SOLDER
Ball Soldering Temperature & Time
260
10
C
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
I/O Pin
/CS1 CS2 /WE /OE /LB /UB
Mode
I/O1~I/O8
I/O9~I/O16
Power
H
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
H
H
Deselected
Hi-Z
Hi-Z
Standby
L
X
L
H
H
H
X
L
Output Disabled
Hi-Z
Hi-Z
Active
L
H
D
OUT
Hi-Z
H
L
Hi-Z
D
OUT
L
H
H
L
L
L
Read
D
OUT
D
OUT
Active
L
H
D
IN
Hi-Z
H
L
Hi-Z
D
IN
L
H
L
X
L
L
Write
D
IN
D
IN
Active
Note:
1. H=V
IH
, L=V
IL
, X=don't care (V
IL or
V
IH
)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8.
When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
HY62SF16406C Series
Rev.02 / Jun.01
3
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min.
Typ
Max.
Unit
Vcc
Supply Voltage
1.7
1.8
2.3
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
1.4
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
1.
-
0.4
V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns
2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
T
A
= -40
C to 85
C
Sym
Parameter
Test Condition
Min Typ
1.
Max Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2=V
IL
or
/
OE
=
V
IH
or /WE = V
IL
or
/
UB
=
V
IH ,
/LB = V
IH
-1
-
1
uA
Icc
Operating Power Supply Current
/CS1 = V
IL
, CS2=V
IH
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
3
mA
/CS1 = V
IL,
CS2 = V
IH
,
V
IN
= V
IH
or V
IL,
Cycle Time = Min,
100% Duty, I
I/O =
0mA
20
mA
I
CC1
Average Operating Current
/CS1 < 0.2V
,
CS2 > Vcc-0.2V,
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
3
mA
I
SB
Standby Current
(TTL Input)
/CS1 = V
IH
or CS2 = V
IL
or
/UB, /LB = V
IH
V
IN
= V
IH
or V
IL
0.3
mA
SL
0.1
3
uA
I
SB1
Standby Current
(CMOS Input)
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
LL
0.1
10
uA
V
OL
Output Low
I
OL
= 0.1mA
-
-
0.2
V
V
OH
Output High
I
OH =
-0.1mA
1.6
-
-
V
Note
1. Typical values are at Vcc = 1.8V T
A
= 25
C
2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25
C, f= 1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
V
IN
= 0V
8
pF
C
OUT
Output Capacitance (I/O)
V
I/O
= 0V
10
pF
Note : These parameters are sampled and not 100% tested
HY62SF16406C Series
Rev.02 / Jun.01
4
AC CHARACTERISTICS
T
A
= -40
C to 85
C, unless otherwise specified
85ns
# Symbol
Parameter
Min. Max.
Unit
1 tRC
Read Cycle Time
85
-
ns
2 tAA
Address Access Time
-
85
ns
3 tACS
Chip Select Access Time
-
85
ns
4 tOE
Output Enable to Output Valid
-
40
ns
5 tBA
/LB, /UB Access Time
-
85
ns
6 tCLZ
Chip Select to Output in Low Z
10
-
ns
7 tOLZ
Output Enable to Output in Low Z
5
-
ns
8 tBLZ
/LB, /UB Enable to Output in Low Z
10
-
ns
9 tCHZ
Chip Deselection to Output in High Z
0
30
ns
10 tOHZ
Out Disable to Output in High Z
0
30
ns
11 tBHZ
/LB, /UB Disable to Output in High Z
0
30
ns
12 tOH
Output Hold from Address Change
10
-
ns
13 tWC
Write Cycle Time
85
-
ns
14 tCW
Chip Selection to End of Write
70
-
ns
15 tAW
Address Valid to End of Write
70
-
ns
16 tBW
/LB, /UB Valid to End of Write
70
-
ns
17 tAS
Address Set-up Time
0
-
ns
18 tWP
Write Pulse Width
60
-
ns
19 tWR
Write Recovery Time
0
-
ns
20 tWHZ
Write to Output in High Z
0
25
ns
21 tDW
Data to Write Time Overlap
35
-
ns
22 tDH
Data Hold from Write Time
0
-
ns
23 tOW
Output Active from End of Write
5
-
ns
AC TEST CONDITIONS
T
A
= -40
C to 85
C, unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 1.6V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
0.9V
tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
CL = 5pF + 1TTL Load
Output Load
Others
CL = 30pF + 1TTL Load
AC TEST LOADS
D
OUT
3273 Ohm
CL(1)
4091 Ohm
V
TM
=1.8V
Note 1. Including jig and scope capacitance:
READ CYCLE
WRITE CYCLE
HY62SF16406C Series
Rev.02 / Jun.01
5
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,2,4)
/CS1
/UB, /LB
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
CS2
Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/UB ,/ LB
/OE
tAA
tACS
tBA
tOE
tCLZ
(3)
tBLZ
(3)
tOLZ
(3)
tOH
tCHZ
(3)
tBHZ
(3)
tOHZ
(3)
HY62SF16406C Series
Rev.02 / Jun.01
6
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR(2)
tBW
tAW
tWP
Data In
High-Z
tAS
tWHZ(3,7)
tDW
tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
HY62SF16406C Series
Rev.02 / Jun.01
7
Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a low /UB and/or /LB .
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the
end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
T
A
= -40
C to 85
C
Symbol
Parameter
Test Condition
Min Typ
1.
Max Unit
V
DR
Vcc for Data Retention
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V,
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
1.2
-
2.3
V
SL
-
0.1
3
uA
Iccdr
Data Retention Current
Vcc=1.5V,
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
LL
-
0.1
10
uA
tCDR
Chip Deselect to Data
Retention Time
0
-
-
ns
tR
Operating Recovery Time
See Data Retention Timing Diagram
tRC
-
-
ns
Notes:
1. Typical values are under the condition of T
A
= 25
C.
2. Typical value are sampled and not 100% tested
HY62SF16406C Series
Rev.02 / Jun.01
8
DATA RETENTION TIMING DIAGRAM 1
/CS1
VDR
CS1>VCC-0.2V
tCDR
tR
VSS
VCC
1.7V
VIH
DATA RETENTION MODE
DATA RETENTION TIMING DIAGRAM 2
0.2V
VDR
tCDR
tR
VSS
VCC
CS2
1.7V
DATA RETENTION MODE
CS2<0.2V
HY62SF16406C Series
Rev.02 / Jun.01
9
PACKAGE INFORMATION
48ball Micro Ball Grid Array Package(M)
BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
3.0 X 5.0 MIN
F
FLAT AREA
G
C1/2
H
B1/2
B1
SIDE VIEW
5
E1
E2
C
E
SEATING PLANE
4
A
r
3 D(DIAMETER)
Symbol
Min.
Typ.
Max.
A
-
0.75
-
B
-
3.75
-
B1
6.7
6.8
6.9
C
-
5.25
-
C1
8.3
8.4
8.5
D
0.3
0.35
0.4
E
0.85
0.9
0.95
E1
0.6
0.65
0.7
E2
0.2
0.25
0.3
R
-
-
0.08
Note
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
HY62SF16406C Series
Rev.02 / Jun.01
10
MARKING INFORMATION
Package
Marking Example
H
Y
S
F
6
4
0
6
C
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
uBGA
Index
HYSF6406C
: Part Name
c
: Power Consumption
- D
: Low Low Power
- S
: Super Low Power
ss
: Speed
- 85
: 85ns
t
: Temperature
- I
: Industrial ( -40 ~ 85
C )
y
: Year (ex : 0 = year 2000, 1= year 2001)
ww
: Work Week ( ex : 12 = work week 12 )
p
: Process Code
xxxxx
: Lot No.
KOR
: Origin Country
Note
- Capital Letter
: Fixed Item
- Small Letter
: Non-fixed Item
Package
Marking Example
H
Y
S
F
6
4
0
6
C
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
uBGA
Index
HYSF6406C
: Part Name
c
: Power Consumption
- D
: Low Low Power
- S
: Super Low Power
ss
: Speed
- 85
: 85ns
t
: Temperature
- I
: Industrial ( -40 ~ 85
C )
y
: Year (ex : 0 = year 2000, 1= year 2001)
ww
: Work Week ( ex : 12 = work week 12 )
p
: Process Code
xxxxx
: Lot No.
KOR
: Origin Country
Note
- Capital Letter
: Fixed Item
- Small Letter
: Non-fixed Item
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