This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev.11 /Jan. 2002 Hynix Semiconductor

HY62SF16804A Series

512Kx16bit full CMOS SRAM

Document Title

512K x16 bit 1.8V Super Low Power Full CMOS slow SRAM

Revision History

Revision No History Draft Date Remark

04 Initial Revision History Insert Jul.02.2000 Preliminary
Revised

- Reliability Spec Deleted

05 Change AC Characteristics Oct.23.2000 Preliminary
- tCLZ : 10/10/20 ---> 10/10/10
- tBLZ : 5/5/5 ---> 10/10/10

06 Part Number is changed Nov.13.2000 Preliminary

- HY62QF16803A --> HY62QF16804A

07 Marking Instruction is inserted Dec.5.2000 Preliminary

08 Test Condition Changed Dec.16.2000 Preliminary
- I

/ I

SB1

/ V

/ I

CCDR

Marking Istruction Inserted

09 Change Logo Apr.28.2001
- Hyundai

Hynix

10 AC Parameter is changed Jul.18.2001
- tCHZ : 30ns --> 20ns

- tBHZ : 30ns --> 20ns
- tOHZ : 30ns --> 20ns

11 Change DC Parameter Jan.28.2002
- Icc1(1us) : 5mA

4mA

Change Data Retention

- IccDR(LL) : 25uA

15uA

Change AC Parameter

- tOE : 40ns

35ns@70ns

HY62SF16804A

Rev.11 /Jan. 2002

DESCRIPTION

The HY62SF16804A is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62SF16804A
uses high performance full CMOS process
technology and is designed for high speed and low
power circuit technology. It is particularly well-
suited for the high density low power system
application. This device has a data retention mode
that guarantees data to remain valid at a minimum
power supply voltage of 1.2V.

FEATURES

Fully static operation and Tri-state output

TTL compatible inputs and outputs

Battery backup(LL/SL-part)

- 1.2V(min) data retention

Standard pin configuration

- 48-uBGA

Product

Voltage

Speed

Operation

Standby Current(uA) Temperature

No.

(V)

(ns)

Current/Icc(mA)

(

HY62SF16804A-C

1.7~2.3 70/85/100

0~70

HY62SF16804A-I

1.7~2.3 70/85/100

-40~85

Note 1. C : Commercial, I : Industrial
2. Current value is max.

PIN CONNECTION

( Top View )

BLOCK DIAGRAM

PIN DESCRIPTION

Pin Name

Pin Function

Pin Name

Pin Function

/CS

Chip Select

I/O1~I/O16

Data Inputs / Outputs

/WE

Write Enable

A0~A18

Address Inputs

/OE

Output Enable

Vcc

Power(1.7V~2.3V)

/LB

Lower Byte Control(I/O1~I/O8)

Vss

Ground

/UB

Upper Byte Control(I/O9~I/O16) NC

No Connection

MEMORY ARRAY

512K x 16

ROW

DECODER

SENSE

AMP

WRITE DRIVER

DAT

A I/O

BUFFER

I/O1

I/O8

I/O9

I/O16

COLUMN

DECODER

BLOCK

DECODER

PRE DECODER

ADD INPUT

BUFFER

ADD INPUT

BUFFER

ADD INPUT

BUFFER

A1,A2

A4,A6~A7

A12

A15~A18

A10

A13

A14

A11

/CS

/OE
/LB
/UB

/WE

IO9

IO10

IO1

IO11

IO2

IO3

Vss IO12

A17

IO4

Vcc

Vcc IO13

Vss A16

IO5

Vss

IO15

IO14

A14

A15

IO6

IO7

IO16

A12

A13

IO8

A18

A10

A11

HY62SF16804A

Rev.11 /Jan. 2002

ORDERING INFORMATION

Part No.

Speed

Power

Package Temp.

HY62SF16804A-DMC

70/85/100

LL-part

uBGA

HY62SF16804A-SMC

70/85/100

SL-part

uBGA

HY62SF16804A-DMI

70/85/100

LL-part

uBGA

HY62SF16804A-SMI

70/85/100

SL-part

uBGA

Note 1. C : Commercial, I : Industrial

ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Parameter

Rating

Unit

Remark

IN,

OUT

Input/Output Voltage

-0.2 to 3.6

Vcc

Power Supply

-0.2 to 4.6

0 to 70

HY62SF16804A-C

Operating Temperature

-40 to 85

HY62SF16804A-I

STG

Storage Temperature

-55 to 150

Power Dissipation

1.0

SOLDER

Ball Soldering Temperature & Time

260

sec

Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.

TRUTH TABLE

I/O

/CS /WE /OE /LB /UB

Mode

I/O1~I/O8 I/O9~I/O16

Power

X Deselected

High-Z

Standby

H Deselected

High-Z

Standby

X Output Disabled

High-Z

Active

L Output Disabled

High-Z

Active

H Read

OUT

High-Z

Active

High-Z

OUT

H Write

High-Z

Active

High-Z

Note:
1. H=V

, L=V

, X=don't care(V

IH or

IL)

2. UB, LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.

HY62SF16804A

Rev.11 /Jan. 2002

RECOMMENDED DC OPERATING CONDITION

Symbol

Parameter

Min. Typ.

Max.

Unit

Vcc

Supply Voltage

1.7

1.8

2.3

Vss

Ground

Input High Voltage

1.4

Vcc+0.3

Input Low Voltage

-0.3

(1)

0.4

Note : 1. VIL = -1.5V for pulse width less than 30ns

DC ELECTRICAL CHARACTERISTICS

Vcc = 1.7V~2.3V, T

= 0

C to 70

C / -40

C to 85

Sym

Parameter

Test Condition

Min. Typ. Max. Unit

Input Leakage Current

Vss < V

< Vcc

-1

Output Leakage Current

Vss < V

OUT

< Vcc, /CS = V

or /WE = V

IL,

/LB = V

-1

Icc

Operating Power Supply
Current

/CS = V

= V

or V

IL,

I/O =

0mA

Cycle Time=Min,100% duty,
I

I/O =

0mA, /CS = V

IL,

= V

or V

Icc1

Average Operating
Current

Cycle time = 1us, 100% duty,
I

I/O =

0mA, /CS < 0.2V,

<0.2V

TTL Standby Current

(TTL Input)

/CS = V

/UB=/LB= V

= V

or V

0.3

SB1

Standby Current
(CMOS Input)

/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V

> Vcc-0.2V or

< Vss+0.2V

Output Low Voltage

= 0.1mA

0.4

Output High Voltage

OH =

-0.1mA

1.4

Note : 1. Typical values are at Vcc = 1.8V, T

= 25

2. Typical values are sampled and not 100% tested

CAPACITANCE

(Temp = 25

C, f = 1.0MHz)

Symbol

Parameter

Condition Max. Unit

Input Capacitance(Add, /CS, /WE, /OE)

= 0V

OUT

Output Capacitance(I/O)

I/O

= 0V

Note : These parameters are sampled and not 100% tested

HY62SF16804A

Rev.11 /Jan. 2002

AC CHARATERISTICS

Vcc = 1.7V~2.3V, T

= 0

C to 70

C / -40

C to 85

-70

-85

-10

Symbol Parameter

Min. Max. Min. Max. Min

Max.

READ CYCLE

1 tRC

Read Cycle Time

100

2 tAA

Address Access Time

100

3 tACS

Chip Select Access Time

100

4 tOE

Output Enable to Output Valid

5 tBA

/LB, /UB Access Time

100

6 tCLZ

Chip Select to Output in Low Z

7 tOLZ

Output Enable to Output in Low Z

8 tBLZ

/LB, /UB Enable to Output in Low Z

9 tCHZ

Chip Deselection to Output in High Z

10 tOHZ

Out Disable to Output in High Z

11 tBHZ

/LB, /UB Disable to Output in High Z

12 tOH

Output Hold from Address Change

WRITE CYCLE

13 tWC

Write Cycle Time

100

14 tCW

Chip Selection to End of Write

15 tAW

Address Valid to End of Write

16 tBW

/LB, /UB Valid to End of Write

17 tAS

Address Set-up Time

18 tWP

Write Pulse Width

19 tWR

Write Recovery Time

20 tWHZ

Write to Output in High Z

21 tDW

Data to Write Time Overlap

22 tDH

Data Hold from Write Time

23 tOW

Output Active from End of Write

AC TEST CONDITIONS

= 0

C to 70

C / -40

C to 85

C, unless otherwise specified

PARAMETER

Value

Input Pulse Level

0.4V to 1.6V

Input Rise and Fall Time

5ns

Input and Output Timing Reference Level

0.9V

tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW

CL = 5pF + 1TTL Load

Output Load

Other

CL = 30pF + 1TTL Load

AC TEST LOADS

O U T

3 2 7 3 O h m

CL(1)

4 0 9 1 O h m

T M

= 1.8V

Note
1. Including jig and scope capacitance

Unit

HY62SF16804A

Rev.11 /Jan. 2002

TIMING DIAGRAM

READ CYCLE 1(Note 1,4)

READ CYCLE 2(Note 1,2,4)

tRC

tAA

Data Valid

Previous Data

tOH

ADDR

Data
Out

READ CYCLE 3(Note 1,2,4)

/CS

/UB, /LB

tACS

Data Valid

tCLZ(3)

tCHZ(3)

Data
Out

Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and /or /LB
2. /OE = V

3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active

ADDR

tRC

/CS

tAA

tACS

tOH

Data Valid

High-Z

Data

Out

/UB ,/ LB

/OE

tBA

tOE

tCLZ

(3)

tBLZ

(3)

tOLZ

(3)

tCHZ

(3)

tBHZ

(3)

tOHZ

(3)

HY62SF16804A

Rev.11 /Jan. 2002

Notes:
1. A write occurs during the overlap of a low / WE, a low /CS1 and low /UB and /or /LB
2. tWR is measured from the earlier of /CS, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active

DATA RETENTION ELECTRIC CHARACTERISTIC

= 0

C to 70

C / -40

C to 85

Symbol

Parameter

Test Condition

Min

Typ Max Unit

Vcc for Data Retention

/CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V

> Vcc-0.2V or

< Vss+0.2V

1.2

2.3

CCDR

Data Retention Current

Vcc=1.5V, /CS > Vcc - 0.2V or
/UB=/LB > Vcc-0.2V,
V

> Vcc-0.2V or

< Vss+0.2V

tCDR

Chip Deselect to Data
Retention Time

Operating Recovery Time

See Data Retention Timing Diagram

tRC

(2)

Notes:
1. Typical values are under the condition of T

= 25

C .

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

/CS or
/UB & /LB

VDR

/CS>Vcc-0.2V or
/UB=/LB > Vcc-0.2V

tCDR

Vss

VCC

1.7V

VIH

DATA RETENTION MODE

HY62SF16804A

Rev.11 /Jan. 2002

PACKAGE INFORMATION

48ball Micro Ball Grid Array Package(M)

BOTTOM VIEW

TOP VIEW

A1 CORNER
INDEX AREA

3.0 X 5.0 MIN

FLAT AREA

C1/2

B1/2

SIDE VIEW

SEATING PLANE

3 D(DIAMETER)

Symbol

Min.

Typ.

Max.

0.75

3.75

7.4

5.25

8.5

0.3

0.35

0.4

0.85

0.9

0.95

0.6

0.65

0.7

0.2

0.25

0.3

0.08

Note

1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.

2. ALL DIMENSIONS ARE MILLIMETERS.

3. DIMENSION " D" IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.

4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.

5. THIS IS A CONTROLLING DIMENSION.

HY62SF16804A

Rev.11 /Jan. 2002

MARKING INSTRUCTION

Package

Marking Example

uBGA

Index

· HYSF6804A

: Part Name

· c

: Power Consumption

- D

: Low Low Power

- S

: Super Low Power

· ss

: Speed

- 55

: 55ns

- 70

: 70ns

- 85

: 85ns

· t

: Temperature

- C

: Commercial ( -0 ~ 70

C )

- I

: Industrial ( -40 ~ 85

C )

· y

: Year (ex : 0 = year 2000, 1= year 2001)

· ww

: Work Week ( ex : 12 = work week 12 )

· p

: Process Code

· xxxxx

: Lot No.

· KOR

: Origin Country

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item

Package

Marking Example

uBGA

Index

· HYSF6804A

: Part Name

· c

: Power Consumption

- D

: Low Low Power

- S

: Super Low Power

· ss

: Speed

- 55

: 55ns

- 70

: 70ns

- 85

: 85ns

· t

: Temperature

- C

: Commercial ( -0 ~ 70

C )

- I

: Industrial ( -40 ~ 85

C )

· y

: Year (ex : 0 = year 2000, 1= year 2001)

· ww

: Work Week ( ex : 12 = work week 12 )

· p

: Process Code

· xxxxx

: Lot No.

· KOR

: Origin Country

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HY62SF16804A-SMC