This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.

Rev 13 / Apr. 2001 Hynix Semiconductor

HY62U8100B Series

128Kx8bit CMOS SRAM

Document Title

128K x8 bit 3.0V Low Power CMOS slow SRAM

Revision History

Revision No History Draft Date Remark

10 Initial Revision History Insert Jul.25.2000 Final
Revised
- Insert 70ns Part

11 Change the Notch Location of sTSOP Sep.04.2000 Final
- Left-Top => Left-Center

12 Marking Information Add Dec.04.2000 Final

Revised

- AC Test Condition Add : 5pF Test Load

13 Changed Logo Apr.30.2001 Final

- HYUNDAI -> hynix
- Marking Information Change

HY62U8100B Series

Rev 13 / Apr. 2001

DESCRIPTION

The HY62U8100B is a high speed, low power and
1M bit CMOS SRAM organized as 131,072 words
by 8bit. The HY62U8100B uses high performance
CMOS process technology and designed for high
speed low power circuit technology. It is
particulary well suited for used in high density low
power system application. This device has a data
retention mode that guarantees data to remain
valid at a minimum power supply voltage of 2.0V.

FEATURES

Fully static operation and Tri-state output

TTL compatible inputs and outputs

Battery backup(LL-part)

-. 2.0V(min) data retention

Standard pin configuration
-. 32 - SOP - 525mil

-. 32 - TSOP-I - 8X20(Standard and Reversed)
-. 32 - sTSOP-I - 8X13.4
(Standard and Reversed)

Product

Voltage

Speed

Operation

Standby Current(uA) Temperature

No.

(V)

(ns)

Current/Icc(mA)

(

HY62U8100B

2.7~3.3 70*/85/100

0~70

HY62U8100B-E 2.7~3.3 70*/85/100

-25~85(E)

HY62U8100B-I 2.7~3.3 70*/85/100

-40~85(I)

Note 1. Blank : Commercial, E : Extended, I : Industrial
2. Current value is max.
* 70ns is available with 30pF test load

PIN CONNECTION

Vcc

A15

/WE

A13

A11

/OE

A10

/CS1

I/O8

I/O7

I/O6

I/O5

I/O4

A16

A14

A12

I/O1

I/O2

I/O3

Vss

CS2

SOP TSOP-I sTSOP-I
( Standard ) (Standard)

PIN DESCRIPTION BLOCK DIAGRAM

Pin Name

Pin Function

/CS1

Chip Select 1

CS2

Chip Select 2

/WE

Write Enable

/OE

Output Enable

A0 ~ A16

Address Inputs

I/O1 ~ I/O8

Data Inputs / Outputs

Vcc

Power(2.7V~3.3V)

Vss

Ground

MEMORY ARRAY

128K x 8

ROW

DECODER

SENSE AMP

WRITE DRIVER

DATA I/O

BUFFER

I/O1

I/O8

COLUMN

DECODER

ADD INPUT

BUFFER

A16

COLUMN

DECODER

/CS1

CS2

/OE

/WE

/OE

A10

DQ8

DQ7

DQ6

DQ5

DQ4

Vss

DQ3

DQ2

DQ1

A11

A13

/WE

CS2

A15

Vcc

A16

A14

A12

/CS1

A11

A13

/WE

CS2

A15

Vcc

A16

A14

A12

A10

/CS1

DQ8

DQ7

DQ6

DQ5

DQ4

Vss

DQ3

DQ2

DQ1

HY62U8100B Series

Rev 13 / Apr. 2001

ORDERING INFORMATION

Part No.

Speed

Power Temp.

Package

HY62U8100BLLG

70*/85/100

LL-part

SOP

HY62U8100BLLT1

70*/85/100

LL-part

TSOP-I(Standard)

HY62U8100BLLR1

70*/85/100

LL-part

TSOP-I(Reversed)

HY62U8100BLLST

70*/85/100

LL-part

smaller TSOP-I(Standard)

HY62U8100BLLSR

70*/85/100

LL-part

smaller TSOP-I(Reversed)

HY62U8100BLLG-E

70*/85/100

LL-part E

SOP

HY62U8100BLLT1-E 70*/85/100

LL-part

TSOP-I(Standard)

HY62U8100BLLR1-E 70*/85/100

LL-part

TSOP-I(Reversed)

HY62U8100BLLST-E 70*/85/100

LL-part

Smaller TSOP-I(Standard)

HY62U8100BLLSR-E 70*/85/100

LL-part

Smaller TSOP-I(Reversed)

HY62U8100BLLG-I

70*/85/100

LL-part I

SOP

HY62U8100BLLT1-I

70*/85/100

LL-part

TSOP-I(Standard)

HY62U8100BLLR1-I

70*/85/100

LL-part

TSOP-I(Reversed)

HY62U8100BLLST-I

70*/85/100

LL-part

Smaller TSOP-I(Standard)

HY62U8100BLLSR-I

70*/85/100

LL-part

Smaller TSOP-I(Reversed)

Note 1. Blank : Commercial, E : Extended, I : Industrial
* 70ns is available with 30pF test load

ABSOLUTE MAXIMUM RATING (1)

Symbol

Parameter

Rating

Unit

Remark

Vcc, V

IN,

OUT

Power Supply, Input/Output Voltage

-0.3 to 4.6

Operating Temperature

0 to 70

HY62U8100B

-25 to 85

HY62U8100B-E

-40 to 85

HY62U8100B-I

STG

Storage Temperature

-65 to 125

Power Dissipation

OUT

Data Output Current

SOLDER

Lead Soldering Temperature & Time

260

sec

Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.

TRUTH TABLE

/CS1 CS2 /WE /OE

Mode

I/O

Power

Deselected

High-Z

Standby

Deselected

High-Z

Standby

Output Disabled

High-Z

Active

Read

Data Out

Active

Write

Data In

Active

Note :
1. H=V

, L=V

, X=don't care( V

IH or

IL )

HY62U8100B Series

Rev 13 / Apr. 2001

RECOMMENDED DC OPERATING CONDITION

Symbol

Parameter

Min.

Typ.

Max.

Unit

Vcc

Supply Voltage

2.7

3.0

3.3

Vss

Ground

Input High Voltage

2.2

Vcc+0.3

Input Low Voltage

-0.3

(1)

0.6

Note :
1. V

= -1.5V for pulse width less than 30ns and not 100% tested

DC ELECTRICAL CHARACTERISTICS

Vcc = 2.7V~3.3V, T

= 0

C to 70

C / -25

C to 85

C (E) / -40

C to 85

C (I), unless otherwise specified

Symbol

Parameter

Test Condition

Min. Typ. Max. Unit

Input Leakage Current

Vss < V

< Vcc

-1

Output Leakage Current

Vss <V

OUT

< Vcc,

/CS1 = V

or CS2 = V

or /WE = V

-1

Icc

Operating Power Supply
Current

/CS1 = V

, CS2 = V

IH,

= V

or V

IL,

I/O =

0mA

CC1

Average Operating

/CS1 = V

, CS2 = V

Current

VIN = V

or V

Cycle Time = Min, 100% duty,

= 0mA

TTL Standby Current
(TTL Input)

/CS1 = V

or CS2 = V

IL ,

VIN = V

or V

0.5

SB1

Standby

HY62U8100B

/CS1 > Vcc - 0.2V or CS2 < 0.2V,

0.5

Current

HY62U8100B-E V

> Vcc - 0.2V or

0.5

(CMOS Input) HY62U8100B-I V

< Vss + 0.2V

0.5

Output Low Voltage

= 2.1mA

0.4

Output High Voltage

OH =

-1.0mA

2.2

Note : Typical values are at Vcc = 3.0V, T

= 25

CAPACITANCE

(Temp = 25

C, f= 10MHz)

Symbol

Parameter

Condition

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

I/O

= 0V

Note : These parameters are sampled and not 100% tested

HY62U8100B Series

Rev 13 / Apr. 2001

AC CHARACTERISTICS

Vcc = 2.7V~3.3V, T

= 0

C to 70

C / -25

C to 85

C (E) / -40

C to 85

C (I), unless otherwise specified

-70*

-85

-10

Min. Max. Min. Max. Min

Max.

1 tRC

Read Cycle Time

100

2 tAA

Address Access Time

100

3 tACS

Chip Select Access Time

100

4 tOE

Output Enable to Output Valid

5 tCLZ

Chip Select to Output in Low Z

6 tOLZ

Output Enable to Output in Low Z

7 tCHZ

Chip Deselection to Output in High Z

8 tOHZ

Out Disable to Output in High Z

9 tOH

Output Hold from Address Change

10 tWC

Write Cycle Time

100

11 tCW

Chip Selection to End of Write

12 tAW

Address Valid to End of Write

13 tAS

Address Set-up Time

14 tWP

Write Pulse Width

15 tWR

Write Recovery Time

16 tWHZ Write to Output in High Z

17 tDW

Data to Write Time Overlap

18 tDH

Data Hold from Write Time

19 tOW

Output Active from End of Write

Note * 70ns is available with 30pF test load

AC TEST CONDITIONS

= 0

C to 70

C / -25

C to 85

C (E) / -40

C to 85

C (I), unless otherwise specified

Parameter

Value

Input Pulse Level

0.4V to 2.2V

Input Rise and Fall Time

5ns

Input and Output Timing Reference Level

1.5V

Output Load

tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW

CL = 5pF + 1TTL Load

Others

CL = 100pF + 1TTL Load

CL = 30pF + 1TTL Load

AC TEST LOADS

CL(1)

TTL

Note : 1 Including jig and scope capacitance

READ CYCLE

Symbol

Parameter

Unit

WRITE CYCLE

HY62U8100B Series

Rev 13 / Apr. 2001

TIMING DIAGRAM

READ CYCLE 1(Note 1,4)

READ CYCLE 2(Note 1,2,4)

tRC

tAA

Data Valid

Previous Data

tOH

ADDR

Data
Out

READ CYCLE 3(Note 1,2,4)

/CS1

tACS

Data Valid

tCLZ

(3)

tCHZ

(3)

Data
Out

CS2

Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and a high CS2.
2. /OE = V

3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active

Data Valid

High-Z

ADDR

Data

Out

tRC

/CS1

CS2

/OE

tAA

tACS

tOE

tCLZ

(3)

tOLZ

(3)

tOH

tCHZ

(3)

tOHZ

(3)

HY62U8100B Series

Rev 13 / Apr. 2001

WRITE CYCLE 1(1,4,5,8) (/WE Controlled)

WRITE CYCLE 2 (Note 1,4,5,8) (/CS1, CS2 Controlled)

Notes:
1. A write occurs during the overlap of a low /WE, a low /CS1 and a high CS2.
2. tWR is measured from the earlier of /CS1 or /WE going high or CS2 going low to the end of
write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the the /CS1 low transition and CS2 high transition occur simultaneously with the /WE low transition
or after the /WE transition, outputs remain in a high impedance state.
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. Transition is measured +200mV from steady state.
This parameter is sampled and not 100% tested.
9. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active

Data Valid

A D D R

Data
O u t

/C S 1

C S 2

/W E

tW C

tCW

tW R

(2)

tAW

tW P

Data In

High-Z

t A S

tW H Z

(3,7)

tDW

t D H

t O W

(

)

(

)

Data Valid

ADDR

Data
Out

/CS1

CS2

/W E

tW C

tCW

tW R

(2)

tAW

tW P

Data In

tDW

tDH

High-Z

tAS

HY62U8100B Series

Rev 13 / Apr. 2001

DATA RETENTION ELECTRIC CHARACTERISTIC

C to 70

C / -25

C to 85

C (E) /-40

C to 85

C (I)

Sym

Parameter

Test Condition

Min

Typ Max Unit

Vcc for Data Retention

/CS1>Vcc-0.2V or CS2<0.2V,

> Vcc - 0.2V or V

<Vss + 0.2V

2.0

CCDR

Data

HY62U8100B

Vcc=3.0V,

0.5

Retention HY62U8100B-E /CS1>Vcc - 0.2V or CS2<0.2V,

0.5

Current

HY62U8100B-I V

> Vcc - 0.2V or V

< Vss + 0.2V

0.5

tCDR Chip Deselect to Data

Retention Time

See Data Retention Timing
Diagram

Operating Recovery Time

tRC

(2)

Notes:
1. Typical values are under the condition of T

= 25

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM 1

CS1

VDR

CS1>VCC-0.2V

tCDR

VSS

VCC

2.7V

2.2V

DATA RETENTION MODE

DATA RETENTION TIMING DIAGRAM 2

0.4V

VDR

tCDR

VSS

VCC

CS2

2.7V

DATA RETENTION MODE

CS2<0.2V

HY62U8100B Series

Rev 13 / Apr. 2001

UNIT : INCH(mm)

0.319(8.103)

0.311(7.900)

0.728(18.491)

0.720(18.288)

0.792(20.117)

0.784(19.914)

0.025(0.64)
0.021(0.54)

0.008(0.21)
0.004(0.10)

0.020(0.50)
BSC

0.011(0.27)

0.041(1.05)
0.037(0.95)

0.006(0.15)

0.002(0.05)

#32

#16

#17

0.007(0.17)

32pin 8x20mm Thin Small Outline Package Reversed(R1)

UNIT : INCH(mm)

0.319(8.103)

0.311(7.900)

0.728(18.491)

0.720(18.288)

0.792(20.117)

0.784(19.914)

0.025(0.64)
0.021(0.54)

0.008(0.21)
0.004(0.1)

0.020(0.50)
BSC

0.007(0.17)

0.041(1.05)
0.037(0.95)

0.006(0.15)

0.002(0.05)

#16

#17

#32

0.011(0.27)

HY62U8100B Series

Rev 13 / Apr. 2001

32pin 8x13.4mm Smaller Thin Small Outline Package Standard(ST)

UNIT : INCH(mm)

0.319(8.1)

0.311(7.9)

0.468(11.9)

0.460(11.7)

0.536(13.6)

0.520(13.2)

0.024(0.6)
0.016(0.4)

0.008(0.2)
0.004(0.1)

0.020(0.50)

0.007(0.17)

0.041(1.05)
0.037(0.95)

0.008(0.20)

0.002(0.05)

#32

#16

#17

0.011(0.27)

32pin 8x13.4mm Thin Small Outline Package Reversed(SR)

UNIT : INCH(mm)

0.319(8.1)

0.311(7.9)

0.468(11.9)

0.460(11.7)

0.536(13.6)

0.520(13.2)

0.024(0.6)
0.016(0.4)

0.008(0.2)
0.004(0.1)

0.020(0.50)

0.007(0.17)

0.041(1.05)
0.037(0.95)

0.008(0.20)

0.002(0.05)

#16

#17

#32

0.011(0.27)

HY62U8100B Series

Rev 13 / Apr. 2001

MARKING INFORMAION

SOP

TSOP-I

Package

Marking Example

Index

· hynix

: hynix Logo

· KOREA / KOR

: Origin Country

· HY62U8100B

: Part Name

· yy

: Year ( ex : 00 = year 2000, 01 = year 2001 )

· ww

: Work Week ( ex : 12 = ww12 )

· p

: Process Code

· cc

: Power Consumption

- L

: Low Power

- LL

: Low Low Power

· G / T1 / ST

: Package Type

- G

: SOP

- T1

: TSOP-I

- ST

: sTSOP

· ss

: Speed

- 85

: 85ns

- 10

: 100ns

· t

: Temperature

- Blank

: Commercial ( 0 ~ 70

C )

- E

: Extended ( -25 ~ 85

C )

- I

: Industrial ( -40 ~ 85

C )

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item (Except hynix)

sTSOP

SOP

TSOP-I

Package

Marking Example

Index

· hynix

: hynix Logo

· KOREA / KOR

: Origin Country

· HY62U8100B

: Part Name

· yy

: Year ( ex : 00 = year 2000, 01 = year 2001 )

· ww

: Work Week ( ex : 12 = ww12 )

· p

: Process Code

· cc

: Power Consumption

- L

: Low Power

- LL

: Low Low Power

· G / T1 / ST

: Package Type

- G

: SOP

- T1

: TSOP-I

- ST

: sTSOP

· ss

: Speed

- 85

: 85ns

- 10

: 100ns

· t

: Temperature

- Blank

: Commercial ( 0 ~ 70

C )

- E

: Extended ( -25 ~ 85

C )

- I

: Industrial ( -40 ~ 85

C )

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item (Except hynix)

sTSOP

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HY62U8100BLLG-I

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HY62U8100BLLG-I