This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.

Rev 07 / Apr. 2001 Hynix Semiconductor

HY62U8400A Series

512Kx8bit CMOS SRAM

Document Title

512K x8 bit 3.0V Low Power CMOS slow SRAM

Revision History

Revision No History Draft Date Remark

04 Revision History Insert Jul.26.2000 Final
Revised
- Insert 70ns Part
- Improved standby current
Isb1 : 30uA

¡ æ

20uA

05 Revised Aug.04.2000 Final
- Change Iccdr Value : 15uA => 20uA

06 Marking Information Add Dec.04.2000 Final

Revised

E.T (-25~85

C), I.T (-40~85

C) Part Insert

AC Test Condition Add : 5pF Test Load

tCLZ Value Change : 15ns/20ns - > 10ns

max : Vcc + 0.2V => Vcc + 0.3V

min : - 0.2V => - 0.3V

07 Changed Logo Apr.30.2001 Final

- HYUNDAI -> hynix
- Marking Information Change

HY62U8400A Series

Rev 07 / Apr. 2001

DESCRIPTION

The HY62U8400A is a high-speed, low power and
4M bits CMOS SRAM organized as 512K words
by 8 bits. The HY62U8400A uses Hynix's high
performance twin tub CMOS process technology
and was designed for high-speed and low power
circuit technology. It is particularly well suited for
use in high-density and low power system
applications. This device has a data retention
mode that guarantees data to remain valid at the
minimum power supply voltage of 2.0V.

FEATURES

Fully static operation and Tri-state outputs

TTL compatible inputs and outputs

Low power consumption

Battery backup(LL-part)

-. 2.0V(min) data retention

Standard pin configuration

-. 32pin 525mil SOP
-. 32pin 400mil TSOP-II
(Standard and Reversed)

Product

Voltage

Speed

Operation

Standby Current(uA) Temperature

No.

(V)

(ns)

Current/Icc(mA)

(

HY62U8400A

2.7~3.3 70*/85/100

0~70

HY62U8400A-E 2.7~3.3 70*/85/100

-25~85

HY62U8400A-I

2.7~3.3 70*/85/100

-40~85

Note 1. Current value is max.
* 70ns is available with 30pF test load

PIN CONNECTION

Vcc

A15

/WE

A13

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A18

A16

A14

A12

I/O1

I/O2

I/O3

Vss

A17

A18

A16

A14

A12

I/O1

I/O2

I/O3

Vss

Vcc

A15

/WE

A13

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A17

Vcc

A15

/WE

A13

A11

/OE

A10

/CS

I/O8

I/O7

I/O6

I/O5

I/O4

A18

A16

A14

A12

I/O1

I/O2

I/O3

Vss

SOP TSOP-II (Standard) TSOP-II (Reversed)

PIN DESCRIPTION BLOCK DIAGRAM

Pin Name

Pin Function

/CS

Chip Select

/WE

Write Enable

/OE

Output Enable

A0 ~ A18

Address Input

I/O1 ~ I/O8

Data Input/Output

Vcc

Power(2.7~3.3V)

Vss

Ground

MEMORY ARRAY

512Kx 8

ROW DECODER

SENSE AMP

WRITE DRIVER

DATA I/O

BUFFER

I/O1

I/O8

COLUMN DECODER

ADD INPUT BUFFER

A18

/CS

/OE

/WE

CONTROL

LOGIC

HY62U8400A Series

Rev 07 / Apr. 2001

ORDERING INFORMATION

Part No.

Speed

Power

Temp

Package

HY62U8400ALLG

70*/85/100

LL-part

0~70

C SOP

HY62U8400ALLG-E

70*/85/100

LL-part -25~85

C SOP

HY62U8400ALLG-I

70*/85/100

LL-part -40~85

C SOP

HY62U8400ALLT2

70*/85/100

LL-part

0~70

C TSOP-II (Standard)

HY62U8400ALLT2-E

70*/85/100

LL-part -25~85

C TSOP-II (Standard)

HY62U8400ALLT2-I

70*/85/100

LL-part -40~85

C TSOP-II (Standard)

HY62U8400ALLR2

70*/85/100

LL-part

0~70

C TSOP-II (Reversed)

HY62U8400ALLR2-E

70*/85/100

LL-part -25~85

C TSOP-II (Reversed)

HY62U8400ALLR2-I

70*/85/100

LL-part -40~85

C TSOP-II (Reversed)

* 70ns is available with 30pF test load

ABSOLUTE MAXIMUM RATING (1)

Symbol

Parameter

Rating

Unit

Vcc, V

IN,

OUT

Power Supply, Input/Output Voltage

-0.5 to 4.0

HY62U8400A

0 to 70

HY62U8400A-E

-25 to 85

Operating Temperature

HY62U8400A-I

-40 to 85

STG

Storage Temperature

-65 to 150

Power Dissipation

1.0

OUT

Data Output Current

SOLDER

Lead Soldering Temperature & Time

260

sec

Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.

TRUTH TABLE

/CS /WE /OE

MODE

I/O OPERATION

Power

Deselected

High-Z

Standby

H Output Disabled

High-Z

Active

Read

Data Out

Active

Write

Data In

Active

Note :
1. H=V

, L=V

, X=don't care (V

or V

)

HY62U8400A Series

Rev 07 / Apr. 2001

RECOMMENDED DC OPERATING CONDITION

= 0

¡ É

to 70

¡ É

(Normal)/-25

C to 85

C (Extended) /-40

C to 85

C (Industrial), unless otherwise specified.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Vcc

Supply Voltage

2.7

3.0

3.3

Vss

Ground

Input High Voltage

2.2

Vcc+0.3

Input Low Voltage

-0.3

(1)

0.4

Note :
1. V

= -1.5V for pulse width less than 30ns and not 100% tested.

DC ELECTRICAL CHARACTERISTICS

= 0

¡ É

to 70

¡ É

(Normal)/-25

C to 85

C (Extended) /-40

C to 85

C (Industrial), unless otherwise specified.

Symbol

Parameter

Test Condition

Min Typ Max Unit

Input Leakage Current

Vss < V

< Vcc

-1

Output Leakage Current

Vss < V

OUT

< Vcc, /CS = V

or /WE = V

-1

Icc

Operating Power Supply
Current

/CS = V

= V

or V

IL,

I/O =

0mA

CC1

Average Operating Current

/CS = V

Min Duty Cycle = 100%,
V

= V

or V

IL,

I/O =

0mA

35 mA

TTL Standby Current
(TTL Input)

/CS = V

= V

or V

0.5 mA

SB1

/CS > Vcc - 0.2V,

Standby Current
(CMOS Input)

> Vcc - 0.2V or

< Vss + 0.2V

LL-E/I

Output Low Voltage

= 2.1mA

0.4

Output High Voltage

OH =

-1mA

2.2

Note : Typical values are at Vcc = 3.0V, T

= 25

CAPACITANCE

Temp = 25

C, f= 1.0MHz

Symbol

Parameter

Condition

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

I/O

= 0V

Note : This parameter is sampled and not 100% tested

HY62U8400A Series

Rev 07 / Apr. 2001

AC CHARACTERISTICS

= 0

¡ É

to 70

¡ É

(Normal)/-25

C to 85

C (Extended) /-40

C to 85

C (Industrial), unless otherwise specified.

-70*

-85

-10

Min. Max. Min. Max. Min

Max.

1 tRC

Read Cycle Time

100

2 tAA

Address Access Time

100

3 tACS

Chip Select Access Time

100

4 tOE

Output Enable to Output Valid

5 tCLZ

Chip Select to Output in Low Z

6 tOLZ

Output Enable to Output in Low Z

7 tCHZ

Chip Deselection to Output in High Z

8 tOHZ

Out Disable to Output in High Z

9 tOH

Output Hold from Address Change

10 tWC

Write Cycle Time

100

11 tCW

Chip Selection to End of Write

12 tAW

Address Valid to End of Write

13 tAS

Address Set-up Time

14 tWP

Write Pulse Width

15 tWR

Write Recovery Time

16 tWHZ Write to Output in High Z

17 tDW

Data to Write Time Overlap

18 tDH

Data Hold from Write Time

19 tOW

Output Active from End of Write

Note * 70ns is available with 30pF test load

AC TEST CONDITIONS

= 0

¡ É

to 70

¡ É

(Normal)/-25

C to 85

C (Extended) /-40

C to 85

C (Industrial), unless otherwise specified.

Parameter

Value

Input Pulse Level

0.4V to 2.2V

Input Rise and Fall Time

5ns

Input and Output Timing Reference Level

1.5V

Output Load

tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW

CL = 5pF + 1TTL Load

Others

CL = 100pF + 1TTL Load

CL = 30pF + 1TTL Load

AC TEST LOADS

CL(1)

TTL

Note
1. Including jig and scope capacitance

READ CYCLE

Symbol

Parameter

Unit

WRITE CYCLE

HY62U8400A Series

Rev 07 / Apr. 2001

TIMING DIAGRAM

READ CYCLE 1(Note 1,4)

READ CYCLE 2(Note 1,2,4)

tRC

tAA

Data Valid

Previous Data

tOH

ADDR

Data
Out

READ CYCLE 3(Note 1,2,4)

/CS

tACS

Data Valid

tCLZ(3)

tCHZ(3)

Data
Out

Notes:
1. A read occurs during the overlap of a low /OE, a high /WE and a low /CS.
2. /OE = V

3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active

ADDR

tRC

/CS

tAA

tACS

tOH

Data Valid

High-Z

Data

Out

/OE

tOE

tCLZ

(3)

tOLZ

(3)

tCHZ

(3)

tOHZ

(3)

HY62U8400A Series

Rev 07 / Apr. 2001

Notes:
1. A write occurs during the overlap of a low /WE and a low /CS.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS in high for the standby, low for active

DATA RETENTION ELECTRIC CHARATERISTIC

= 0

¡ É

to 70

¡ É

(Normal)/-25

C to 85

C (Extended) /-40

C to 85

C (Industrial), unless otherwise specified.

Symbol

Parameter

Test Condition

Min

Typ Max Unit

Vcc for Data Retention

/CS > Vcc-0.2V,

2.0

> Vcc-0.2V or V

< 0.2V

CCDR

Vcc = 3.0V,

/CS>Vcc-0.2V,

LL-E

Data Retention Current

>Vcc-0.2V or V

<0.2V

LL-I

tCDR

Chip Deselect to Data
Retention Time

Operating Recovery Time

tRC(2)

Notes:
1. Typical values are at the condition of T

= 25

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

/CS

VDR

/CS > VCC-0.2V

tCDR

VSS

VCC

2.7V

2.2V

DATA RETENTION MODE

HY62U8400A Series

Rev 07 / Apr. 2001

PACKAGE INFORMATION

32pin 400mil Thin Small Outline Package Standard(T2)

0.404(10.2620)

0.396(10.0580()

0.470(11.9380)

0.462(11.7350)

0.829(21.0570)

0.822(20.8790)

0.050BSC

(1.2700)

0.017(0.4500)

0.012(0.3050)

BASE PLANE

SEATING PLANE

0.047(1.1940)

0.039(0.9910)

0.0059(0.1500)

0.0020(0.0500)

0.0083(0.2100)

0.0047(0.1200)

0.0235(0.5970)

0.0160(0.4060)

GAGE PLANE

0-5

UNIT : INCH(mm)

MAX.

MIN.

32pin 400mil Thin Small Outline Package Reversed(R2)

0.404(10.2620)

0.396(10.0580)

0.470(11.9380)

0.462(11.7350)

0.829(21.0570)

0.822(20.8790)

0.050 BSC

(1.2700)

0.017(0.4500)

0.012(0.3050)

BASE PLANE

SEATING PLANE

0.047(1.1940)

0.039(0.9910)

0.0059(0.1500)

0.0020(0.0500)

0.0083(0.2100)

0.0047(0.1200)

0.0235(0.5970)

0.0160(0.4060)

GAGE PLANE

0-5

UNIT : INCH(mm)

MAX.

MIN.

HY62U8400A Series

Rev 07 / Apr. 2001

MARKING INFORMATION

SOP

TSOP-II

Package

Marking Example

Index

· hynix

: hynix Logo

· KOREA

: Origin Country

· HY62U8400A

: Part Name

· yy

: Year ( ex : 00 = year 2000, 01 = year 2001 )

· ww

: Work Week ( ex : 12 = ww12 )

· p

: Process Code

· cc

: Power Consumption

- L

: Low Power

- LL

: Low Low Power

· G / T2

: Package Type

- G

: SOP

- T2

: TSOP-II

· ss

: Speed

- 85

: 85ns

- 10

: 100ns

· t

: Temperature

- Blank

: Commercial ( 0 ~ 70

C )

- E

: Extended ( -25 ~ 85

C )

- I

: Industrial ( -40 ~ 85

C )

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item (Except hynix)

SOP

TSOP-II

Package

Marking Example

Index

· hynix

: hynix Logo

· KOREA

: Origin Country

· HY62U8400A

: Part Name

· yy

: Year ( ex : 00 = year 2000, 01 = year 2001 )

· ww

: Work Week ( ex : 12 = ww12 )

· p

: Process Code

· cc

: Power Consumption

- L

: Low Power

- LL

: Low Low Power

· G / T2

: Package Type

- G

: SOP

- T2

: TSOP-II

· ss

: Speed

- 85

: 85ns

- 10

: 100ns

· t

: Temperature

- Blank

: Commercial ( 0 ~ 70

C )

- E

: Extended ( -25 ~ 85

C )

- I

: Industrial ( -40 ~ 85

C )

Note

- Capital Letter

: Fixed Item

- Small Letter

: Non-fixed Item (Except hynix)

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