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Электронный компонент: HY62UF16806A-DMI

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This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 /Jan. 2002 Hynix Semiconductor
HY62UF16806A Series
512Kx16bit full CMOS SRAM
Document Title
512K x16 bit 3.0V Super Low Power Full CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Draft Feb.21.2001 Preliminary
01 Change Logo Apr.28.2001
- Hyundai
Hynix
02 Change DC Parameter Jan.28.2002
- Isb1(LL) : 40uA
25uA
- Isb1(Typ) : 8uA
1uA
- Icc : 5mA
4mA
- Icc1(1us) : 8mA
4mA
- Icc1(Min) : 50mA
40mA
Change Data Retention
- IccDR(LL) : 25uA
15uA
Change AC Parameter
- tOE : 35ns
25ns@55ns
: 40ns
35ns@70ns
- tCW : 50ns
45ns@55ns
- tAW : 50ns
45ns@55ns
- tBW : 50ns
45ns@55ns
- tWP : 45ns
45ns@55ns
- tCHZ : 30ns
20ns@55ns , 30ns
25ns@70ns
- tOHZ : 30ns
20ns@55ns , 30ns
25ns@70ns
- tBHZ : 30ns
20ns@55ns , 30ns
25ns@70ns
























HY62UF16806A
Rev.02/Jan. 2002
2

DESCRIPTION
The HY62UF16806A is a high speed, super low
power and 8Mbit full CMOS SRAM organized as
524,288 words by 16bits. The HY62UF16806A
uses high performance full CMOS process
technology and is designed for high speed and
low power circuit technology. It is particularly well-
suited for the high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 1.2V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(LL/SL-part)
- 1.2V(min) data retention
Standard pin configuration
- 48-uBGA




Product
Voltage
Speed
Operation
Standby Current(uA) Temperature
No.
(V)
(ns)
Current/Icc(mA)
LL
SL
(
C)
HY62UF16806A-C 2.7~3.3 55/70/85
4
25
8
0~70
HY62UF16806A-I
2.7~3.3 55/70/85
4
25
8
-40~85
Note 1. C : Commercial, I : Industrial
2. Current value is max.

PIN CONNECTION
( Top View )
BLOCK DIAGRAM

















PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS1, CS2 Chip Select
I/O1~I/O16
Data Inputs / Outputs
/WE
Write Enable
A0~A18
Address Inputs
/OE
Output Enable
Vcc
Power(2.7V~3.3V)
/LB
Lower Byte Control(I/O1~I/O8)
Vss
Ground
/UB
Upper Byte Control(I/O9~I/O16) NC
No Connection





MEMORY ARRAY
512K x 16
ROW
DECODER
SENSE AMP
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
I/O9
I/O16
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT
BUFFER
A18
/CS1
/OE
/LB
/UB
/WE
CS2
1
2
3
4
5
6
A
B
C
D
E
F
G
H
/LB
IO9
IO10
/OE A0 A1 A2 CS2
/UB A3 A4 /CS1 IO1
IO11 A5 A6 IO2 IO3
Vss IO12 A17 A7 IO4 Vcc
Vcc IO13 Vss A16 IO5 Vss
IO15 IO14 A14 A15 IO6 IO7
IO16 NC A12 A13 /WE IO8
A18 A8 A9 A10 A11 NC
HY62UF16806A
Rev.02/Jan. 2002
2
ORDERING INFORMATION
Part No.
Speed
Power Package Temp.
HY62UF16806A-DMC
55/70/85 LL-part
uBGA
C
HY62UF16806A-SMC
55/70/85 SL-part
uBGA
C
HY62UF16806A-DMI
55/70/85 LL-part
uBGA
I
HY62UF16806A-SMI
55/70/85 SL-part
uBGA
I
Note 1. C : Commercial, I : Industrial

ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Unit
Remark
V
IN,
V
OUT
Input/Output Voltage
-0.3 to Vcc+0.3V
V
Vcc
Power Supply
-0.3 to 3.6
V
0 to 70
C
HY62UF16806A-C
T
A
Operating Temperature
-40 to 85
C
HY62UF16806A-I
T
STG
Storage Temperature
-55 to 150
C
P
D
Power Dissipation
1.0
W
T
SOLDER
Ball Soldering Temperature & Time
260
10
C
sec

Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.

TRUTH TABLE
I/O Pin
/CS1 CS2 /WE /OE /LB /UB
Mode
I/O1~I/O8
I/O9~I/O16
Power
H
X
X
X
X
X
Hi-Z
Hi-Z
X
L
X
X
X
X
Hi-Z
Hi-Z
X
X
X
X
H
H
Deselected
Hi-Z
Hi-Z
Standby
L
H
H
H
L
X
Hi-Z
Hi-Z
L
H
H
H
X
L
Output Disabled
Hi-Z
Hi-Z
Active
L
H
D
OUT
Hi-Z
H
L
Hi-Z
D
OUT
L
H
H
L
L
L
Read
D
OUT
D
OUT
Active
L
H
D
IN
Hi-Z
H
L
Hi-Z
D
IN
L
H
L
X
L
L
Write
D
IN
D
IN
Active

Note:
1. H=V
IH
, L=V
IL
, X=don't care(V
IH or
V
IL)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 -I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 -I/O16.




HY62UF16806A
Rev.02/Jan. 2002
3
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min. Typ.
Max.
Unit
Vcc
Supply Voltage
2.7
3.0
3.3
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
-
0.6
V

Note : 1. VIL = -1.5V for pulse width less than 30ns


DC ELECTRICAL CHARACTERISTICS

Vcc = 2.7V~3.3V, T
A
= 0
C to 70
C/ -40
C to 85
C
Sym
Parameter
Test Condition
Min Typ
1.
Max Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc,
/CS1 = V
IH
or CS2=V
IL
or
/
OE
=
V
IH
or /WE = V
IL
or
/
UB
=
V
IH ,
/LB = V
IH
-1
-
1
uA
Icc
Operating Power Supply Current
/CS1 = V
IL
, CS2=V
IH
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
4
mA
/CS1 = V
IL,
CS2 = V
IH
,
V
IN
= V
IH
or V
IL,
Cycle Time = Min,
100% Duty, I
I/O =
0mA
40
mA
I
CC1
Average Operating Current
/CS1 < 0.2V
,
CS2 > Vcc-0.2V,
V
IN
< 0.2V or V
IN
> Vcc-0.2V
,
Cycle Time = 1us,
100% Duty, I
I/O =
0mA
4
mA
I
SB
Standby Current
(TTL Input)
/CS1 = V
IH
or CS2 = V
IL
or
/UB, /LB = V
IH
V
IN
= V
IH
or V
IL
0.5
mA
SL
-
8
uA
I
SB1
Standby Current
(CMOS Input)
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
LL
1
25
uA
V
OL
Output Low
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High
I
OH =
-1.0mA
2.4
-
-
V

Note : Typical values are at Vcc = 3.0V, T
A
= 25
C



CAPACITANCE

(Temp = 25
C, f = 1.0MHz)
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE)
V
IN
= 0V
8
pF
C
OUT
Output Capacitance (I/O)
V
I/O
= 0V
10
pF

Note : These parameters are sampled and not 100% tested

HY62UF16806A
Rev.02/Jan. 2002
4
AC CHARACTERISTICS

Vcc = 2.7V~3.3V, T
A
= 0
C to 70
C/ -40
C to 85
C unless otherwise specified
-55
-70
-85
# Symbol Parameter
Min. Max. Min. Max. Min
Max.
READ CYCLE
1 tRC
Read Cycle Time
55
-
70
-
85
-
ns
2 tAA
Address Access Time
-
55
-
70
-
85
ns
3 tACS
Chip Select Access Time
-
55
-
70
-
85
ns
4 tOE
Output Enable to Output Valid
-
25
-
35
-
45
ns
5 tBA
/LB, /UB Access Time
-
55
-
70
-
85
ns
6 tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
ns
7 tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
ns
8 tBLZ
/LB, /UB Enable to Output in Low Z
10
-
10
-
10
-
ns
9 tCHZ
Chip Deselection to Output in High Z
0
20
0
25
0
30
ns
10 tOHZ
Out Disable to Output in High Z
0
20
0
25
0
30
ns
11 tBHZ
/LB, /UB Disable to Output in High Z
0
20
0
25
0
30
ns
12 tOH
Output Hold from Address Change
10
-
10
-
10
-
ns
WRITE CYCLE
13 tWC
Write Cycle Time
55
-
70
-
85
-
ns
14 tCW
Chip Selection to End of Write
45
-
60
-
70
-
ns
15 tAW
Address Valid to End of Write
45
-
60
-
70
-
ns
16 tBW
/LB, /UB Valid to End of Write
45
-
60
-
70
-
ns
17 tAS
Address Set-up Time
0
-
0
-
0
-
ns
18 tWP
Write Pulse Width
40
-
50
-
55
-
ns
19 tWR
Write Recovery Time
0
-
0
-
0
-
ns
20 tWHZ
Write to Output in High Z
0
20
0
25
0
30
ns
21 tDW
Data to Write Time Overlap
25
-
30
-
35
-
ns
22 tDH
Data Hold from Write Time
0
-
0
-
0
-
ns
23 tOW
Output Active from End of Write
5
-
5
-
5
-
ns
AC TEST CONDITIONS
T
A
= 0
C to 70
C / -40
C to 85
C, unless otherwise specified
PARAMETER
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
tCLZ,tOLZ,tBLZ,tCHZ,tOHZ,tBHZ,tWHZ,tOW
CL = 5pF + 1TTL Load
Output Load
Other
CL = 30pF + 1TTL Load

AC TEST LOADS
D
O U T
1 7 2 8 O h m
CL(1)
1 0 2 9 O h m
V
T M
= 2.8V
Note
1. Including jig and scope capacitance
Unit
HY62UF16806A
Rev.02/Jan. 2002
5

TIMING DIAGRAM

READ CYCLE 1(Note 1,4)



















READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out

READ CYCLE 3(Note 1,2,4)
/CS1

/UB, /LB
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
CS2

Notes:
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and
CS2 are in active status.
2. /OE = V
IL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active


Data Valid
High-Z
ADDR
Data
Out
tRC
/CS1
CS2
/UB ,/ LB
/OE
tAA
tACS
tBA
tOE
tCLZ
(3)
tBLZ
(3)
tOLZ
(3)
tOH
tCHZ
(3)
tBHZ
(3)
tOHZ
(3)
HY62UF16806A
Rev.02/Jan. 2002
6

WRITE CYCLE 1 (1,4,8) (/WE Controlled)
























WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)



























Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
High-Z
tAS
tWHZ
(3,7)
tDW
tDH
tOW
(5)
(6)
Data Valid
ADDR
Data
Out
/CS1
CS2
/UB,/LB
/WE
tWC
tCW
tWR
(2)
tBW
tAW
tWP
Data In
tDW
tDH
High-Z
High-Z
tAS
HY62UF16806A
Rev.02/Jan. 2002
7
Notes:
1. A write occurs whenever a low on the /WE while /UB and/or /LB and /CS1 and
CS2 are in active state.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the
end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low
transition or after the /WE transition, outputs remain in a high impedance state.
5. Q(data out) is the same phase with the write data of this write cycle.
6. Q(data out) is the read data of the next address.
7. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
8. /CS1 in high for the standby, low for active
CS2 in low for the standby, high for active.
/UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC

T
A
= 0
C to 70
C / -40
C to 85
C
Symbol
Parameter
Test Condition
Min Typ
1.
Max Unit
V
DR
Vcc for Data Retention
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V,
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
1.2
-
3.3
V
SL
-
-
8
uA
Iccdr
Data Retention Current
Vcc=1.5V,
/CS1 > Vcc - 0.2V or
CS2 < Vss + 0.2V or
/UB, /LB > Vcc - 0.2V
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V

LL
-
-
15
uA
tCDR
Chip Deselect to Data
Retention Time
0
-
-
ns
tR
Operating Recovery Time
See Data Retention Timing Diagram
tRC
-
-
ns

Notes:
1. Typical values are under the condition of T
A
= 25
C .
2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM 1

/CS1
VDR
CS1>VCC-0.2V
tCDR
tR
VSS
VCC
2.7V
VIH
DATA RETENTION MODE

HY62UF16806A
Rev.02/Jan. 2002
8
DATA RETENTION TIMING DIAGRAM 2
0.4V
VDR
tCDR
tR
VSS
VCC
CS2
2.7V
DATA RETENTION MODE
CS2<0.2V




































HY62UF16806A
Rev.02/Jan. 2002
9
PACKAGE INFORMATION

48ball Micro Ball Grid Array Package(M)

BOTTOM VIEW
TOP VIEW
B
A
A1 CORNER
INDEX AREA
6
5
4
3
2
1
A
A
B
C
D
C
C1
E
3.0 X 5.0 MIN
F
FLAT AREA
G
C1/2
H
B1/2
B1
SIDE VIEW

5
E1
E2
C
E
SEATING PLANE
4
A
r
3 D(DIAMETER)

Symbol
Min.
Typ.
Max.
A
-
0.75
-
B
-
3.75
-
B1
-
7.4
-
C
-
5.25
-
C1
-
8.5
-
D
0.3
0.35
0.4
E
0.85
0.9
0.95
E1
0.6
0.65
0.7
E2
0.2
0.25
0.3
r
-
-
0.08









Note
1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
5. THIS IS A CONTROLLING DIMENSION.
HY62UF16806A
Rev.02/Jan. 2002
10
MARKING INSTRUCTION

Package
Marking Example
H
Y
U
F
6
8
0
6
A
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
uBGA
Index
HYUF6806A
: Part
Name
c
: Power Consumption
-
D
: Low Low Power
-
S
: Super Low
Power
ss
: Speed
-
55
:
55ns
-
70
: 70ns
-
85
:
85ns
t
:
Temperature
-
C
: Commercial (
-
0 ~ 70
C
)
-
I
: Industrial (
-
40 ~ 85
C
)
y
: Year (ex : 0 = year 2000, 1= year
2001)
ww
: Work Week ( ex : 12 = work week 12
)
p
: Process
Code
xxxxx
: Lot
No.
KOR
: Origin Country
Note
-
Capital Letter
: Fixed Item
-
Small Letter
: Non
-
fixed Item
Package
Marking Example
H
Y
F
6
8
0
A
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
uBGA
Index
: Part
Name
c
: Power Consumption
-
D
: Low Low Power
-
S
: Super Low
Power
ss
: Speed
-
55
:
55ns
-
70
: 70ns
-
85
:
85ns
t
:
Temperature
-
C
: Commercial (
-
0 ~ 70
C
)
-
I
: Industrial (
-
40 ~ 85
C
)
y
: Year (ex : 0 = year 2000, 1= year
2001)
ww
: Work Week ( ex : 12 = work week 12
)
p
: Process
Code
xxxxx
: Lot
No.
KOR
: Origin Country
Note
-
Capital Letter
: Fixed Item
-
Small Letter
: Non
-
fixed Item
l
l
l
l
l
l
l
l
l