This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 06 / Apr. 2001 Hynix Semiconductor
HY62V8400A Series
512Kx8bit CMOS SRAM
Document Title
512K x8 bit 3.3V Low Power CMOS slow SRAM
Revision History
Revision No History Draft Date Remark
03 Revision History Insert Jul.06.2000 Final
Revised
- Improved standby current
Isb1 : 30uA
20uA
04 Revised Aug.04.2000 Final
- Change Iccdr Value : 15uA => 20uA
05 Marking Information Add Dec.04.2000 Final
Revised
-
E.T (-25~85
C), I.T (-40~85
C) Part Insert
-
AC Test Condition Add : 5pF Test Load
-
V
IH
max : Vcc + 0.2V => Vcc + 0.3V
-
V
IL
min : - 0.2V => - 0.3V
06 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
HY62V8400A Series
Rev 06 / Apr. 2001
2
DESCRIPTION
The HY62V8400A is a high-speed, low power and
4M bits CMOS SRAM organized as 512K words
by 8 bits. The HY62V8400A uses Hynix's high
performance twin tub CMOS process technology
and was designed for high-speed and low power
circuit technology. It is particularly well suited for
use in high-density and low power system
applications. This device has a data retention
mode that guarantees data to remain valid at the
minimum power supply voltage of 2.0V.
FEATURES
Fully static operation and Tri-state outputs
TTL compatible inputs and outputs
Low power consumption
Battery backup(LL-part)
-. 2.0V(min) data retention
Standard pin configuration
-. 32pin 525mil SOP
-. 32pin 400mil TSOP-II
(Standard and Reversed)
Product
Voltage
Speed
Operation
Standby Current(uA) Temperature
No.
(V)
(ns)
Current/Icc(mA)
LL
(
C)
HY62V8400A
3.0~3.6 70/85/100
5
20
0~70
HY62V8400A-E 3.0~3.6 70/85/100
5
30
-25~70
HY62V8400A-I
3.0~3.6 70/85/100
5
30
-40~70
Note 1. Current value is max.
PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A17
A17
Vcc
A15
/WE
A13
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
SOP TSOP-II(Standard) TSOP-II(Reversed)
PIN DESCRIPTION BLOCK DIAGRAM
Pin Name
Pin Function
/CS
Chip Select
/WE
Write Enable
/OE
Output Enable
A0 ~ A18
Address Input
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(3.0~3.6V)
Vss
Ground
MEMORY ARRAY
512Kx 8
ROW DECODER
SENSE AMP
WRITE DRIVER
DATA I/O
BUFFER
I/O1
I/O8
COLUMN DECODER
ADD INPUT BUFFER
A0
A18
/CS
/OE
/WE
CONTROL
LOGIC
HY62V8400A Series
Rev 06 / Apr. 2001
2
ORDERING INFORMATION
Part No.
Speed
Power
Temp
Package
HY62V8400ALLG
70/85/100
LL-part
0~70
C SOP
HY62V8400ALLG-E
70/85/100
LL-part -25~85
C SOP
HY62V8400ALLG-I
70/85/100
LL-part -40~85
C SOP
HY62V8400ALLT2
70/85/100
LL-part
0~70
C TSOP-II (Standard)
HY62V8400ALLT2-E
70/85/100
LL-part -25~85
C TSOP-II (Standard)
HY62V8400ALLT2-I
70/85/100
LL-part -40~85
C TSOP-II (Standard)
HY62V8400ALLR2
70/85/100
LL-part
0~70
C TSOP-II (Reversed)
HY62V8400ALLR2-E
70/85/100
LL-part -25~85
C TSOP-II (Reversed)
HY62V8400ALLR2-I
70/85/100
LL-part -40~85
C TSOP-II (Reversed)
ABSOLUTE MAXIMUM RATING (1)
Symbol
Parameter
Rating
Unit
Vcc, V
IN,
V
OUT
Power Supply, Input/Output Voltage
-0.5 to 4.0
V
HY62V8400A
0 to 70
C
HY62V8400A-E
-25 to 85
C
T
A
Operating Temperature
HY62V8400A-I
-40 to 85
C
T
STG
Storage Temperature
-65 to 150
C
P
D
Power Dissipation
1.0
W
I
OUT
Data Output Current
50
MA
T
SOLDER
Lead Soldering Temperature & Time
260
10
C
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
TRUTH TABLE
/CS /WE /OE
MODE
I/O OPERATION
Power
H
X
X
Deselected
High-Z
Standby
L
H
H Output Disabled
High-Z
Active
L
H
L
Read
Data Out
Active
L
L
X
Write
Data In
Active
Note :
1. H=V
IH
, L=V
IL
, X=don't care (V
IH
or V
IL
)
HY62V8400A Series
Rev 06 / Apr. 2001
3
RECOMMENDED DC OPERATING CONDITION
T
A
= 0
to 70
(Normal)/-25
C to 85
C (Extended) /-40
C to 85
C (Industrial), unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vcc
Supply Voltage
3.0
3.3
3.6
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
-
0.4
V
Note :
1. V
IL
= -1.5V for pulse width less than 30ns and not 100% tested.
DC ELECTRICAL CHARACTERISTICS
T
A
= 0
to 70
(Normal)/-25
C to 85
C (Extended) /-40
C to 85
C (Industrial), unless otherwise specified.
Symbol
Parameter
Test Condition
Min Typ Max Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL
-1
-
1
uA
Icc
Operating Power Supply
Current
/CS = V
IL
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
-
5
mA
I
CC1
Average Operating Current
/CS = V
IL
Min Duty Cycle = 100%,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
-
40 mA
I
SB
TTL Standby Current
(TTL Input)
/CS = V
IH ,
V
IN
= V
IH
or V
IL
-
0.5 mA
I
SB1
/CS > Vcc - 0.2V,
LL
-
-
20
uA
Standby Current
(CMOS Input)
V
IN
> Vcc - 0.2V or
V
IN
< Vss + 0.2V
LL-E/I
-
-
30
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1mA
2.2
-
-
V
Note : Typical values are at Vcc = 3.3V, T
A
= 25
C
CAPACITANCE
Temp = 25
C, f= 1.0MHz
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Note : This parameter is sampled and not 100% tested
HY62V8400A Series
Rev 06 / Apr. 2001
4
AC CHARACTERISTICS
T
A
= 0
to 70
(Normal)/-25
C to 85
C (Extended) /-40
C to 85
C (Industrial), unless otherwise specified.
70ns
85ns
100ns
Min. Max. Min. Max. Min
Max.
1 tRC
Read Cycle Time
70
-
85
-
100
-
ns
2 tAA
Address Access Time
-
70
-
85
-
100
ns
3 tACS
Chip Select Access Time
-
70
-
85
-
100
ns
4 tOE
Output Enable to Output Valid
-
40
-
45
-
50
ns
5 tCLZ
Chip Select to Output in Low Z
10
-
10
-
10
-
ns
6 tOLZ
Output Enable to Output in Low Z
5
-
5
-
5
-
ns
7 tCHZ
Chip Deselecting to Output in High Z
0
25
0
30
0
30
ns
8 tOHZ
Out Disable to Output in High Z
0
25
0
30
0
30
ns
9 tOH
Output Hold from Address Change
15
-
15
-
15
-
ns
10 tWC
Write Cycle Time
70
-
85
-
100
-
ns
11 tCW
Chip Selection to End of Write
60
-
70
-
80
-
ns
12 tAW
Address Valid to End of Write
60
-
70
-
80
-
ns
13 tAS
Address Set-up Time
0
-
0
-
0
-
ns
14 tWP
Write Pulse Width
50
-
60
-
70
-
ns
15 tWR
Write Recovery Time
0
-
0
-
0
-
ns
16 tWHZ Write to Output in High Z
0
25
0
30
0
30
ns
17 tDW
Data to Write Time Overlap
30
-
35
-
40
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
5
-
ns
AC TEST CONDITIONS
T
A
= 0
to 70
(Normal)/-25
C to 85
C (Extended) /-40
C to 85
C (Industrial), unless otherwise specified.
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
tCLZ,tOLZ,tCHZ,tOHZ,tWHZ
CL = 5pF + 1TTL Load
Others
CL = 100pF + 1TTL Load
AC TEST LOADS
CL(1)
TTL
Note
1. Including jig and scope capacitance
READ CYCLE
WRITE CYCLE
Symbol
Parameter
#
Unit
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