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Электронный компонент: HY62WT08081E-DG85E

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This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility
for use of circuits described. No patent licenses are implied.
Rev 04 / May . 2001 Hynix Semiconductor
HY62WT08081E
Series
32Kx8bit CMOS SRAM
Document Title
32K x8 bit 2.7~5.5V Low Power Slow SRAM
Revision History
Revision No History Draft Date Remark
00 Initial Feb.05.2001 Preliminary
01 Revised Feb.13.2001 Final
-
Change LL-Part Isb1 Limit @E.T/I.T, 4.5~5.5V
: 15uA => 20uA

02 Revised Feb.21.2001 Final
-
Marking Information Change : SOP Type
-
Voh Limit Change : 2.4V => 2.2V @2.7~3.6V
03 Changed Logo Apr.30.2001 Final
- HYUNDAI -> hynix
- Marking Information Change
04 Revised May.23.2001 Final
-
Iccdr Limit Add : 2uA @40
C


HY62WT08081E Series
Rev 04 / May . 2001
2
DESCRIPTION

The HY62WT08081E is a high-speed, low power
and 32,786 X 8-bits CMOS Static Random
Access Memory fabricated using Hynix's high
performance CMOS process technology. It is
suitable for use in low voltage operation and
battery back-up application. This device has a
data retention mode that guarantees data to
remain valid at the minimum power supply
voltage of 2.0 volt.

FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Low power consumption
Battery backup(LL-part)
- 2.0V(min.) data retention
Standard pin configuration
- 28 pin 600mil PDIP
- 28 pin 330mil SOP
- 28 pin 8x13.4 mm TSOP-I
(Standard)
Product
Voltage
Speed
Operation
Standby Current(uA)
Temperature
No.
(V)
(ns)
Current(mA)
LL-part
(
C)
4.5~5.5
55/70
10
10
HY62WT08081E-C
2.7~3.6
70*/85
2
5
0~70(Normal)
4.5~5.5
55/70
10
20
HY62WT08081E-E
2.7~3.6
70*/85
2
8
-25~85(Extended)
4.5~5.5
55/70
10
20
HY62WT08081E-I
2.7~3.6
70*/85
2
8
-40~85(Industrial)
Note 1. Current value is max.
* 70ns is available with 30pF test load

PIN CONNECTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
/WE
A8
A9
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
/OE
A11
A9
A8
A13
/WE
Vcc
A14
A12
A7
A6
A5
A4
A3
I/O8
PDIP SOP TSOP-I(Standard)

PIN DESCRIPTION BLOCK DIAGRAM
Pin Name
Pin Function
/CS
Chip Select
/WE
Write Enable
/OE
Output Enable
A0 ~ A14
Address Inputs
I/O1 ~ I/O8
Data Input/Output
Vcc
Power(
+
5.0V)
Vss
Ground


A14
COLUMN DECODER
A0
ROW DECODER
MEMORY ARRAY
512x512
SENSE AMP
OUTPUT BUFFER
I/O1
I/O8
ADD INPUT BUFFER
/CS
/OE
/WE
WRITE DRIVER
CONTROL
LOGIC
HY62WT08081E Series
Rev 04 / May. 2001
2

ORDERING INFORMATION
Speed
Part No.
4.5~5.5V 2.7~3.6V
Power
Temp
Package
HY62WT08081E-DPC
0 to 70
C
HY62WT08081E-DPE
-25 to 85
C
HY62WT08081E-DPI
-40 to 85
C
PDIP
HY62WT08081E-DGC
0 to 70
C
HY62WT08081E-DGE
-25 to 85
C
HY62WT08081E-DGI
-40 to 85
C
SOP
HY62WT08081E-DTC
0 to 70
C
HY62WT08081E-DTE
-25 to 85
C
HY62WT08081E-DTI
55/70
70*/85
LL-part
-40 to 85
C
TSOP-I Standard
Note * 70ns is available with 30pF test load


ABSOLUTE MAXIMUM RATING (1)
Symbol
Parameter
Rating
Unit
Vcc, V
IN,
V
OUT
Power Supply,
4.5~5.5V
-0.3 to 7.0
V
Input/Output Voltage
2.7~3.6V
-0.3 to 4.6
V
HY62WT08081E-C
0 to 70
C
HY62WT08081E-E
-25 to 85
C
T
A
Operating Temperature
HY62WT08081E-I
-40 to 85
C
T
STG
Storage Temperature
-65 to 150
C
P
D
Power Dissipation
1.0
W
I
OUT
Data Output Current
50
mA
T
SOLDER
Lead Soldering Temperature & Time
260
10
C
sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliability.





















HY62WT08081E Series
Rev 04 / May. 2001
3
RECOMMENDED DC OPERATING CONDITIONS
Vcc = 4.5~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vcc
Power Supply Voltage
4.5
5.0
5.5
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
-
0.8
V
Note1. V
IL
= -3.0V for pulse width less than 50ns

Vcc = 2.7~3.6V
Symbol
Parameter
Min.
Typ.
Max.
Unit
Vcc
Power Supply Voltage
2.7
3.0/3.3
3.6
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
-
Vcc+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
-
0.6
V
Note1. V
IL
= -1.5V for pulse width less than 50ns

TRUTH TABLE
/CS /WE /OE
Mode
I/O Operation
H
X
X Standby
High-Z
L
H
H Output Disabled High-Z
L
H
L Read
Data Out
L
L
X Write
Data In
Note
1. H=V
IH
, L=V
IL
, X=Don't Care





















HY62WT08081E Series
Rev 04 / May. 2001
4

DC CHARACTERISTICS

Vcc = 4.5 ~ 5.5V, T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial),
unless otherwise specified.
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL
-1
-
1
uA
Icc
Operating Power Supply
Current
/CS = V
IL
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
-
-
10
mA
I
CC1
Average Operating Current /CS = V
IL,
V
IN
= V
IH
or V
IL,
Min. Duty Cycle = 100%, I
I/O =
0mA
-
-
50
mA
I
SB
TTL Standby Current
(TTL Inputs)
/CS= V
IH,
V
IN
= V
IH
or V
IL
-
-
1
mA
I
SB1
CMOS Standby Current
/CS > Vcc - 0.2V,
(CMOS Inputs)
V
IN
> Vcc - 0.2V or
0~ 70
C
-
-
10
uA
V
IN
< Vss + 0.2V
-25~ 85
C or
-40~ 85
C
-
-
20
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1.0mA
2.4
-
-
V

Note : Typical values are at Vcc =5.0V, T
A
= 25
C


Vcc = 2.7~3.6V, T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial),
unless otherwise specified.
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit
I
LI
Input Leakage Current
Vss < V
IN
< Vcc
-1
-
1
uA
I
LO
Output Leakage Current
Vss < V
OUT
< Vcc, /CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL
-1
-
1
uA
Icc
Operating Power Supply
Current
/CS = V
IL
,
V
IN
= V
IH
or V
IL,
I
I/O =
0mA
-
-
2
mA
I
CC1
Average Operating Current /CS = V
IL,
V
IN
= V
IH
or V
IL,
Min. Duty Cycle = 100%, I
I/O =
0mA
-
-
30
mA
I
SB
TTL Standby Current
(TTL Inputs)
/CS= V
IH,
V
IN
= V
IH
or V
IL
-
-
0.3
mA
I
SB1
CMOS Standby Current
/CS > Vcc - 0.2V,
(CMOS Inputs)
V
IN
> Vcc - 0.2V or
0~ 70
C
-
-
5
uA
V
IN
< Vss + 0.2V
-25~ 85
C or
-40~ 85
C
-
-
8
uA
V
OL
Output Low Voltage
I
OL
= 2.1mA
-
-
0.4
V
V
OH
Output High Voltage
I
OH =
-1.0mA
2.2
-
-
V

Note : Typical values are at Vcc =3.0/3.3V, T
A
= 25
C











HY62WT08081E Series
Rev 04 / May. 2001
5
AC CHARACTERISTICS

Vcc = 5V
10%, T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial)
unless otherwise specified.
-55
-70
Min. Max. Min. Max.
Unit
1 tRC
Read Cycle Time
55
-
70
-
ns
2 tAA
Address Access Time
-
55
-
70
ns
3 tACS
Chip Select Access Time
-
55
-
70
ns
4 tOE
Output Enable to Output Valid
-
25
-
35
ns
5 tCLZ
Chip Select to Output in Low Z
10
-
10
-
ns
6 tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
7 tCHZ
Chip Disable to Output in High Z
0
20
0
30
ns
8 tOHZ
Out Disable to Output in High Z
0
20
0
30
ns
9 tOH
Output Hold from Address Change
5
-
5
-
ns
10 tWC
Write Cycle Time
55
-
70
-
ns
11 tCW
Chip Selection to End of Write
45
-
60
-
ns
12 tAW
Address Valid to End of Write
45
-
60
-
ns
13 tAS
Address Set-up Time
0
-
0
-
ns
14 tWP
Write Pulse Width
40
-
50
-
ns
15 tWR
Write Recovery Time
0
-
0
-
ns
16 tWHZ Write to Output in High Z
0
20
0
25
ns
17 tDW
Data to Write Time Overlap
25
-
30
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
ns


Vcc = 2.7~3.6V, T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial)
unless otherwise specified.
-70*
-85
Min. Max. Min
Max.
Unit
1 tRC
Read Cycle Time
70
-
85
-
ns
2 tAA
Address Access Time
-
70
-
85
ns
3 tACS
Chip Select Access Time
-
70
-
85
ns
4 tOE
Output Enable to Output Valid
-
35
-
45
ns
5 tCLZ
Chip Select to Output in Low Z
10
-
10
-
ns
6 tOLZ
Output Enable to Output in Low Z
5
-
5
-
ns
7 tCHZ
Chip Disable to Output in High Z
0
30
0
30
ns
8 tOHZ
Out Disable to Output in High Z
0
30
0
30
ns
9 tOH
Output Hold from Address Change
5
-
5
-
ns
10 tWC
Write Cycle Time
70
-
85
-
ns
11 tCW
Chip Selection to End of Write
60
-
75
-
ns
12 tAW
Address Valid to End of Write
60
-
75
-
ns
13 tAS
Address Set-up Time
0
-
0
-
ns
14 tWP
Write Pulse Width
50
-
60
-
ns
15 tWR
Write Recovery Time
0
-
0
-
ns
16 tWHZ Write to Output in High Z
0
25
0
30
ns
17 tDW
Data to Write Time Overlap
30
-
40
-
ns
18 tDH
Data Hold from Write Time
0
-
0
-
ns
19 tOW
Output Active from End of Write
5
-
5
-
ns
Note * 70ns is available with 30pF test load
READ CYCLE
WRITE CYCLE
READ CYCLE
WRITE CYCLE
Symbol
Parameter
#
Symbol
Parameter
#
HY62WT08081E Series
Rev 04 / May. 2001
6
AC TEST CONDITIONS

T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial)
unless otherwise specified.
Parameter
Value
Input Pulse Level
Vcc = 4.5~5.5V
0.8V to 2.4V
Vcc = 2.7~3.6V
0.4V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing Reference Level
1.5V
Output Load
tCLZ,tOLZ,tCHZ,tOHZ,tWHZ,tOW
CL = 5pF + 1TTL Load
Others
CL = 100pF + 1TTL Load
CL* = 30pF + 1TTL Load

AC TEST LOADS

CL(1)
TTL


Note : Including jig and scope capacitance

CAPACITANCE

T
A
= 25
C, f = 1.0MHz
Symbol
Parameter
Condition
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input /Output Capacitance
V
I/O
= 0V
8
pF

Note : These parameters are sampled and not 100% tested















HY62WT08081E Series
Rev 04 / May. 2001
7

TIMING DIAGRAM

READ CYCLE 1
ADDR
OE
CS
Data
Out
Data Valid
tRC
tACS
tCLZ
tOE
tOLZ
tAA
tOH
tOHZ
tCHZ
High-Z




Note(READ CYCLE):

1. t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and arenot
referenced to output voltage levels.
2. At any given temperature and voltage condition, t
CHZ
max. is less than t
CLZ
min. both for a given device
and from device to device.
3. /WE is high for the read cycle.


READ CYCLE 2

tRC
tAA
Data Valid
Previous Data
tOH
tOH
ADDR
Data
Out


Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS= V
IL.
3. /OE =V
IL
.









HY62WT08081E Series
Rev 04 / May. 2001
8

WRITE CYCLE 1(/OE Clocked)


ADDR
OE
CS
Data
Out
tWC
tDW
tOHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW


WRITE CYCLE 2
(/OE Low Fixed)

tDW
tWHZ
WE
Data Valid
tDH
tWP
tAS
Data In
tWR
tCW
tAW
(7)
(8)
tOW
ADDR
CS
Data
Out
tWC










HY62WT08081E Series
Rev 04 / May. 2001
9

Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of /CS going low to the end of write .
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR is
applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. D
OUT
is the same phase of the latest written data in this write cycle.
8. D
OUT
is the read data of the new address.

DATA RETENTION CHARACTERISTIC

T
A
= 0
C to 70
C (Normal) / -25
C to 85
C (Extended) / -40
C to 85
C (Industrial)
unless otherwise specified.
Symbol
Parameter
Test Condition
Min
Typ
(1)
Max
Unit
V
DR
Vcc for Data Retention
CS>Vcc-0.2V,
2.0
-
-
V
V
IN
>Vcc - 0.2V or V
IN
<Vss + 0.2V
I
CCDR(3)
Data Retention Current
Vcc=3.0V,
/CS>Vcc - 0.2V,
0~ 70
C
-
0.5
5
uA
V
IN
>Vcc - 0.2V or
V
IN
<Vss + 0.2V
-25~ 85
C or
-40~ 85
C
-
0.5
8
uA
tCDR
Chip Deselect to Data
Retention Time
See Data Retention
0
-
-
ns
tR
Operating Recovery Time
Timing Diagram
tRC
(2)
-
-
ns
Notes
1. Typical values are under the condition of T
A
= 25
C.
2. tRC is read cycle time.
3. Iccdr : 2uA at Ta < 40
C

DATA RETENTION TIMING DIAGRAM

CS
VDR
CS>VCC-0.2V
tCDR
tR
VSS
VCC
4.5V/2.7V
2.2V
DATA RETENTION MODE



HY62WT08081E Series
Rev 04 / May. 2001
10
PACKAGE INFORMATION
28pin 600mil Dual In-Line Package(Blank)
UNIT : INCH(mm)
MIN.
MAX.
1.467(37.262)
1.447(36.754)
0.140(3.556)
0.120(3.048)
0.155(3.937)
0.145(3.683)
0.020(0.508)
0.021(0.533)
0.015(0.381)
0.100(2.54)BSC
0.065(1.650)
0.050(1.270)
0.090(2.286)
0.070(1.778)
0.014(0.356)
0.008(0.200)
0.600(15.240)BSC
0.550(13.970)
0.530(13.462)
0.035(0.889)
3 deg
11 deg







28pin 330mil Small O utline Package(FW)

UNIT : INCH(mm)
0.346(8.788)
0.338(8.585)
0.480(12.192)
0.460(11.684)
0.110(2.794)
0.094(2.388)
0.014(0.356)
0.002(0.051)
0.050(1.270)BSC
0.020(0.508)
0.014(0.356)
0.728(18.491)
0.720(18.288)
0.012(0.305)
0.008(0.203)
0.050(1.270)
0.030(0.762)
MAX
.
MIN.





HY62WT08081E Series
Rev 04 / May. 2001
11

28pin 8x13.4mm Thin Small Outline Package Standard(T)

0.468(11.9)
0.460(11.7)
0.536(13.6)
0.520(13.2)
0.027(0.7)
0.012(0.3)
0.008(0.2)
0.004(0.1)
0.319(8.1)
0.311(7.9)
0.040(1.02)
0.036(0.91)
0.008(0.20)
0.002(0.05)
0.022(0.55 BSC)
UNIT : INCH(mm)
MAX.
MIN.






































HY62WT08081E Series
Rev 04 / May. 2001
12

MARKING INFORMATION
PDIP
SOP
Package
Marking Example
Index
hynix
: hynix Logo
KOREA
: Origin Country
HY62WT081E
: Part Name
- HY62WT081E
: 2.7~5.5V
yy
: Year ( ex : 00 = year 2000, 01 = year 2001 )
ww
: Work Week ( ex : 12 = ww12 )
p
: Process Code
c
: Power Consumption
- L
: Low Power
- D
: Low Low Power
ss
: Speed
- 55
: 55ns @ 4.5~5.5V
70ns @ 2.7~3.6V
- 70
: 70ns @ 4.5~5.5V
85ns @ 2.7~3.6V
t
: Temperature
- C
: Commercial ( 0 ~ 70
C )
- E
: Extended ( -25 ~ 85
C )
- I
: Industrial ( -40 ~ 85
C )
xxxxxxxx
: Lot Number
Note
- Capital Letter
: Fixed Item
- Small Letter
: Non-fixed Item ( Except hynix )
h
y
n
i
x
y
H
Y
6
2
W
T
0
8
1
E
K
O
R
E
A
TSOP-I
y
w
w
p
c
s
s
t
h
y
n
i
x
y
y
H
Y
6
2
W
T
0
8
1
E
c
K
O
R
E
A
w
w
p
s
s
t
h
y
n
i
x
y
y
H
Y
6
2
W
T
0
8
1
E
c
K
O
R
E
A
x
x
x
x
x
w
w
p
s
s
t
x
x
x
PDIP
SOP
Package
Marking Example
Index
hynix
: hynix Logo
KOREA
: Origin Country
HY62WT081E
: Part Name
- HY62WT081E
: 2.7~5.5V
yy
: Year ( ex : 00 = year 2000, 01 = year 2001 )
ww
: Work Week ( ex : 12 = ww12 )
p
: Process Code
c
: Power Consumption
- L
: Low Power
- D
: Low Low Power
ss
: Speed
- 55
: 55ns @ 4.5~5.5V
70ns @ 2.7~3.6V
- 70
: 70ns @ 4.5~5.5V
85ns @ 2.7~3.6V
t
: Temperature
- C
: Commercial ( 0 ~ 70
C )
- E
: Extended ( -25 ~ 85
C )
- I
: Industrial ( -40 ~ 85
C )
xxxxxxxx
: Lot Number
Note
- Capital Letter
: Fixed Item
- Small Letter
: Non-fixed Item ( Except hynix )
h
y
n
i
x
y
H
Y
6
2
W
T
0
8
1
E
K
O
R
E
A
TSOP-I
y
w
w
p
c
s
s
t
h
y
n
i
x
y
y
H
Y
6
2
W
T
0
8
1
E
c
K
O
R
E
A
w
w
p
s
s
t
h
y
n
i
x
y
y
H
Y
6
2
W
T
0
8
1
E
c
K
O
R
E
A
w
w
p
s
s
t
h
y
n
i
x
y
y
H
Y
6
2
W
T
0
8
1
E
c
K
O
R
E
A
x
x
x
x
x
w
w
p
s
s
t
x
x
x