HY64UD16162B Series
1
Revision 1.1
Apr. 2003
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Document Title
Document Title
1
1
M x 16 bit Low Low Power 1T/1C
M x 16 bit Low Low Power 1T/1C
Pseudo SRAM
Pseudo SRAM
Revision history
Revision history
Revision No.
Revision No.
1.0
1.1
Draft Date
Draft Date
Dec. 3. '02
Apr. 21. `03
Remark
Remark
Preliminary
History
History
Initial
History
History
Initial
DC Spec.
HY64UD16162B Series
2
Revision 1.1
Apr. 2003
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
1
1
M x 16 bit Low
M x 16 bit Low
Low Power 1T/1C
Low Power 1T/1C
SRAM
SRAM
DESCRIPTION
The HY64UD16162B is a 16Mbit 1T/1C SRAM
featured by high-speed operation and super low
power consumption. The HY64UD16162B adopts
one transistor memory cell and is organized as
1,048,576 words by 16bits. The HY64UD16162B
operates in the extended range of temperature and
supports a wide operating voltage range. The
HY64UD16162B also supports the deep power
down mode for a super low standby current. The
HY64UD16162B delivers the high-density low
power SRAM capability to the high-speed low power
system.
CMOS Process Technology
1M x 16 bit Organization
TTL compatible and Tri-state outputs
Deep Power Down : Memory cell data hold invalid
Standard pin configuration : 48-FBGA(6mmX8mm)
Data mask function by /LB, /UB
Separated I/O Power Supply : Vddq
PRODUCT FAMILY
FEATURES
Note 1. tCS - /UB,/LB=High : Chip Deselect.
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS1
Chip Select
IO1~IO8
Lower Data Inputs/Outputs
/WE
Write Enable
A0~A19
Address Inputs
/OE
Output Enable
Vdd
Power Supply for Internal Circuit
/LB
Lower Byte(I/O1~I/O8)
Vss
Ground
/UB
Upper Byte(I/O9~I/O16)
CS2
Deep Power Down
DNU
Do Not Use
IO9~IO16
Upper Data Inputs/Outputs
Vddq
Power Supply for I/O
NC
No Connection
PIN CONNECTION
(Top View)
/LB
/OE
A0
A1
A2
CS2
IO9
/UB
A3
A4
/CS1 IO1
IO10 IO11
A5
A6
IO2
IO3
Vss IO12 A17
A7
IO4
Vdd
Vddq IO13 DNU A16
IO5
Vss
IO15 IO14 A14
A15
IO6
IO7
IO16 A19
A12
A13
/WE
IO8
A18
A8
A9
A10
A11
NC
BLOCK DIAGRAM
ADD
IN
PU
T
BUFFER
P
R
E
DE
CODE
R
COL
U
MN
DE
CODE
R
BLOC
K
DE
CODE
R
ROW
DECODER
SEN
SE AM
P
W
R
I
TE
D
R
I
VER
D
A
T
A
I/O
BUFFER
MEMORY ARRAY
1,024K x 16
CONTROL
LOGIC
A0
A19
IO1
IO8
IO9
IO16
/CS1
CS2
/OE
/LB
/UB
/WE
Product No.
Voltage [V]
Vdd/Vddq
Speed
tRC[ns]
Temp.
[
C]
(I
SB1
,Max) (I
DPD
,Max) (I
CC2
,Max)
Power Dissipation
Mode
HY64UD16162B-DF70E
3.0/3.0
70
-25~85
85
A
2
A
25
mA
1CS with /UB,/LB:tCS
1
HY64UD16162B-DF60E
3.0/3.0
TBD
-25~85
TBD
2
A
25
mA
1CS with /UB,/LB:tCS
1
HY64UD16162B-DF60I
3.0/3.0
TBD
-40~85
TBD
2
A
25
mA
1CS with /UB,/LB:tCS
1
HY64UD16162B-DF70I
3.0/3.0
70
-40~85
85
A
2
A
25
mA
1CS with /UB,/LB:tCS
1
HY64UD16162B Series
3
Revision 1.1
Apr. 2003
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied. Exposure
to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
Power
Standby
/CS1
H
CS2
H
/WE
X
/OE
X
/LB
X
/UB
X
Mode
Deselected
I/O1~I/O8
High-Z
I/O9~I/O16
High-Z
I/O Pin
X
X
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
X
X
L
H
H
L
H
H
L
H
H
X
X
X
L
H
X
L
H
X
L
H
X
H
L
L
L
H
H
H
L
L
L
X
H
H
H
H
L
L
L
L
L
L
Deselected
Deselected
Write
Read
Output Disabled
Write
Read
Output Disabled
Write
Read
Output Disabled
High-Z
High-Z
High-Z
High-Z
D
IN
High-Z
D
OUT
High-Z
High-Z
High-Z
D
IN
High-Z
D
OUT
High-Z
D
IN
D
OUT
High-Z
High-Z
High-Z
D
IN
D
OUT
High-Z
Deep Power Down
Standby
Active
Active
Active
Active
Active
Active
Active
Active
Active
Note
1. H=V
IH
, L=V
IL
, X=don't care(V
IL
or V
IH
)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
ORDERING INFORMATION
Part Number
Speed
Package
HY64UD16162B-E
60 / 70
FBGA
HY64UD16162B-I
60 / 70
FBGA
Power
LL-Part
LL-Part
Temperature
E
1
I
2*
Note
1. E : Extended Temp. (-25
C ~ 85C)
2. I : Industrial Temp. (-40
C ~ 85C)
ABSOLUTE MAXIMUM RATINGS
1
Symbol
Parameter
Rating
Remark
V
IN
Input Voltage
-0.3 to Vdd+0.3
Unit
V
Vdd
Core Power Supply
-0.3 to 3.6
V
T
A
Ambient Temperature
-25 to 85
HY64PD16162A-E
C
T
STG
Storage Temperature
-55 to 150
C
P
D
Power Dissipation
1.0
W
T
SOLDER
Ball Soldering Temperature & Time
26010
Csec
-40 to 85
HY64PD16162A-I
C
Vddq
I/O Power Supply
-0.3 to 3.6
V
V
OUT
Output Voltage
-0.3 to Vddq+0.3
V
HY64UD16162B Series
4
Revision 1.1
Apr. 2003
CAPACITANCE
(Temp = 25
C, f=1.0MHz)
Symbol
Parameter
C
IN
Input Capacitance(ADD, /CS1, CS2, /WE, /OE, /UB, /LB)
Unit
pF
Max.
8
Condition
V
IN
=0V
C
OUT
Output Capacitance(I/O)
pF
10
V
I/O
=0V
Note : These parameters are sampled and not 100% tested
Note 1. VIL=-1.5V for pulse width less than 10ns
Undershoot is sampled, not 100% tested.
RECOMMENDED DC OPERATING CONDITION
Symbol
Parameter
Min.
Vdd
Core Supply Voltage
2.7
Unit
V
Typ.
3.0
Max.
3.3
V
SS
Ground
0
V
-
0
V
IH
Input High Voltage
2.2
V
-
Vdd+0.3
V
IL
Input Low Voltage
-0.3
1
V
-
0.6
Vddq
I/O Supply Voltage
2.7
V
3.0
3.3
DC ELECTRICAL CHARACTERISTICS
Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, T
A
= -25
C to 85C(E) / -40C to 85C(I)
Sym.
Parameter
Min.
I
LI
Input Leakage Current
-1
Unit
A
Max.
1
Test Condition
V
SS
V
IN
Vdd
I
LO
Output Leakage Current
-1
A
1
V
SS
V
OUT
Vddq,
/CS1=V
IH
, CS2=V
IH
,
/OE=V
IH
or /WE=V
IL
I
CC
Operating Power Supply Current
-
mA
3
/CS1=V
IL
, CS2=V
IH
,
V
IN
=V
IH
or V
IL
, I
I/O
=0mA
I
CC1
Average Operating Current
-
mA
25
/CS1=V
IL
, CS2=V
IH
,
V
IN
=V
IH
or V
IL
, Cycle Time=Min.
100% Duty, I
I/O
=0mA
-
mA
5
/CS1
0.2V, CS2 Vdd-0.2V,
V
IN
0.2V or V
IN
Vdd-0.2V,
Cycle Time=1
s
.
100% Duty, I
I/O
=0mA
I
SB
TTL Standby Current
-
mA
0.5
/CS1,CS2=V
IH
or /UB,/LB= V
IH
I
SB1
Standby Current(CMOS Input)
/CS1,CS2
Vdd-0.2V,
/UB,/LB
0.2V or /UB,/LB
Vdd-0.2V, otherwise
CS2,/UB,/LB
Vdd-0.2V,
/CS1
0.2V or /CS1Vdd-0.2V
V
OL
Output Low Voltage
-
V
0.4
I
OL
=2.1mA
V
OH
Output High Voltage
2.4
V
-
I
OH
=-1.0mA
I
CC2
I
DPD
Deep Power Down
-
A
2
CS2
V
SS+
0.2V
-
A
TBD
-
A
85
60ns
70ns
mA
25
60ns
70ns
HY64UD16162B Series
5
Revision 1.1
Apr. 2003
AC TEST LOADS
Note
1. Including jig and scope capacitance.
AC CHARACTERISTICS
C
L
1
=50 pF
D
OUT
R
L
=50 Ohm
V
L
=0.5*Vddq
Z
0
=50 Ohm
Vdd=2.7V~3.3V, Vddq=2.7V~3.3V, T
A =
-25
C to 85C(E) / -40C to 85C(I), unless otherwise specified
AC TEST CONDITIONS
T
A =
-25
C to 85C(E) / -40C to 85C(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rising and Fall Time
5ns
Input Timing Reference Level
1.5V
Output Load
See Below
Output Timing Reference Level
0.5*Vddq
#
Parameter
1
Read Cycle Time
Unit
ns
Symbol
tRC
Read Cycle
2
Address Access Time
ns
tAA
3
Chip Select Access Time
ns
tACS
4
Output Enable to Output Valid
ns
tOE
5
/LB, /UB Access Time
ns
tBA
6
Chip Select to Output in Low Z
ns
tCLZ
7
Output Enable to Output in Low Z
ns
tOLZ
8
/LB, /UB Enable to Output in Low Z
ns
tBLZ
9
Chip Disable to Output in High Z
ns
tCHZ
10
Out Disable to Output in High Z
ns
tOHZ
11
/LB, /UB Disable to Output in High Z
ns
tBHZ
12
Output Hold from Address Change
ns
tOH
13
Write Cycle Time
ns
tWC
Write Cycle
14
Chip Selection to End of Write
ns
tCW
15
Address Valid to End of Write
ns
tAW
16
/LB, /UB Valid to End of Write
ns
tBW
17
Address Set-up Time
ns
tAS
18
Write Pulse Width
ns
tWP
19
Write Recovery Time
ns
tWR
20
Write to Output in High Z
ns
tWHZ
21
Data to Write Time Overlap
ns
tDW
22
Data Hold from Write Time
ns
tDH
23
Output Active from End of Write
ns
tOW
Min.
60
Max.
-
-
60
-
60
-
20
-
60
10
-
5
-
10
-
0
10
0
10
0
10
5
-
60
-
55
-
55
-
55
-
0
-
50
-
0
-
0
15
25
-
0
-
5
-
-60
Min.
70
Max.
-
-
70
-
70
-
20
-
70
10
-
5
-
10
-
0
10
0
10
0
10
5
-
70
-
60
-
60
-
60
-
0
-
50
-
0
-
0
20
30
-
0
-
5
-
-70
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