16Mx72bits

PC100 SDRAM SO DIMM

based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh

This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1/May. 02 1

HYM71V16M755HC(L)T8 Series

DESCRIPTION

The HYM71V16M755HC(L)T8 Series are 16Mx72bits Synchronous DRAM Modules. The modules are composed of nine
16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package
on a 144pin glass-epoxy printed circuit board.

The HYM71V16M755HC(L)T8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of
128Mbytes memory. The HYM71V16M755HC(L)T8 Series are fully synchronous operation referenced to the positive
edge of the clock . All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are inter-
nally pipelined to achieve very high bandwidth.

FEATURES

PC100MHz support

144pin SDRAM SO DIMM

Serial Presence Detect with EEPROM

1.25" Height PCB with single sided components

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL interface

Data mask function by DQM

SDRAM internal banks : four banks

Module bank : one physical bank

Auto refresh and self refresh

4096 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4 or 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock

Frequency

Internal

Bank

Ref.

Power

SDRAM

Package

Plating

HYM71V16M755HCT8-8

125MHz

4 Banks

Normal

TSOP-II

Gold

HYM71V16M755HCT8-P

100MHz

HYM71V16M755HCT8-S

100MHz

HYM71V16M755HCLT8-8

125MHz

Low Power

HYM71V16M755HCLT8-P

100MHz

HYM71V16M755HCLT8-S

100MHz

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 2

HYM71V16M755HC(L)T8 Series

PIN DESCRIPTION

PIN

PIN NAME

DESCRIPTION

CK0, CK1

Clock Inputs

The system clock input. All other inputs are registered to the SDRAM on
the rising edge of CLK

CKE0

Clock Enable

Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh

/S0

Chip Select

Enables or disables all inputs except CK, CKE and DQM

BA0, BA1

SDRAM Bank Address

Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity

A0 ~ A11

Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10

/RAS, /CAS, /WE

Row Address Strobe, Column
Address Strobe, Write Enable

/RAS, /CAS and /WE define the operation
Refer function truth table for details

DQM0~DQM7

Data Input/Output Mask

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ63

Data Input/Output

Multiplexed data input / output pin

VCC

Power Supply (3.3V)

Power supply for internal circuits and input buffers

Ground

SCL

SPD Clock Input

Serial Presence Detect Clock input

SDA

SPD Data Input/Output

Serial Presence Detect Data input/output

SA0~2

SPD Address Input

Serial Presence Detect Address Input

No Connection

No connection

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 3

HYM71V16M755HC(L)T8 Series

PIN ASSIGNMENTS

FRONT SIDE

BACK SIDE

FRONT SIDE

BACK SIDE

PIN NO.

NAME

PIN NO.

NAME

PIN NO.

NAME

PIN NO.

NAME

VSS

DQ0

DQ32

CK1

DQ1

DQ33

VSS

DQ2

DQ34

DQ3

DQ35

VCC

DQ4

DQ36

DQ16

DQ48

DQ5

DQ37

DQ17

DQ49

DQ6

DQ38

DQ18

DQ50

DQ7

DQ39

DQ19

DQ51

VSS

DQM0

DQM4

DQ20

DQ52

DQM1

DQM5

DQ21

DQ53

VCC

DQ22

DQ54

DQ23

100

DQ55

101

VCC

102

VCC

103

104

VSS

105

106

BA0

DQ8

DQ40

107

VSS

108

VSS

DQ9

DQ41

109

110

BA1

DQ10

DQ42

111

A10/AP

112

A11

DQ11

DQ43

113

VCC

114

VCC

115

DQM2

116

DQM6

DQ12

DQ44

117

DQM3

118

DQM7

DQ13

DQ45

119

VSS

120

VSS

DQ14

DQ46

121

DQ24

122

DQ56

DQ15

DQ47

123

DQ25

124

DQ57

VSS

125

DQ26

126

DQ58

127

DQ27

128

DQ59

129

VCC

130

VCC

Voltage Key

131

DQ28

132

DQ60

133

DQ29

134

DQ61

CK0

CKE0

135

DQ30

136

DQ62

VCC

137

DQ31

138

DQ63

/RAS

/CAS

139

VSS

140

VSS

/WE

141

SDA

142

SCL

/S0

143

VCC

144

VCC

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 4

HYM71V16M755HC(L)T8 Series

BLOCK DIAGRAM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

/CS

DM0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

/CS

DM1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

/CS

DM2

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

/CS

DM3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS

DM4

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

/CS

DM5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

/CS

DM6

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

/CS

DM7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

/S0

BA0-BA1 BA0-BA1 : SDRAMs U0 - U8
A0 - A12 A0 - A12 : SDRAMs U0 - U8

/RAS /RAS : SDRAMs U0 - U8

/CAS /CAS : SDRAMs U0 - U8

CKE0 CKE : SDRAMs U0 - U8

/WE /WE : SDRAMs U0 - U8

Serial PD

SA0

SA1

SA2

SCL

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

/CS

DM0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

U0/U4

U1, U8/U5

U2/U6

U3/U7

CLK0/1

10 Ohm

VDD

VSS

Two 0.1uF Capacitors

per each SDRAM

To all SDRAMs

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

/CS

DM0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

/CS

DM1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

/CS

DM2

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

/CS

DM3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS

DM4

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

/CS

DM5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

/CS

DM6

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

/CS

DM7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

/S0

BA0-BA1 BA0-BA1 : SDRAMs U0 - U8
A0 - A12 A0 - A12 : SDRAMs U0 - U8

/RAS /RAS : SDRAMs U0 - U8

/CAS /CAS : SDRAMs U0 - U8

CKE0 CKE : SDRAMs U0 - U8

/WE /WE : SDRAMs U0 - U8

BA0-BA1 BA0-BA1 : SDRAMs U0 - U8
A0 - A12 A0 - A12 : SDRAMs U0 - U8

/RAS /RAS : SDRAMs U0 - U8

/CAS /CAS : SDRAMs U0 - U8

CKE0 CKE : SDRAMs U0 - U8

/WE /WE : SDRAMs U0 - U8

Serial PD

SA0

SA1

SA2

SCL

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

/CS

DM0

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

U0/U4

U1, U8/U5

U2/U6

U3/U7

CLK0/1

10 Ohm

VDD

VSS

Two 0.1uF Capacitors

per each SDRAM

To all SDRAMs

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 5

HYM71V16M755HC(L)T8 Series

SERIAL PRESENCE DETECT

BYTE

NUMBER

FUNCTION

DESCRIPTION

FUNCTION

VALUE

NOTE

-8

-P

-S

-8

-P

-S

BYTE0

# of Bytes Written into Serial Memory at Module
Manufacturer

128 Bytes

80h

BYTE1

Total # of Bytes of SPD Memory Device

256 Bytes

08h

BYTE2

Fundamental Memory Type

SDRAM

04h

BYTE3

# of Row Addresses on This Assembly

0Ch

BYTE4

# of Column Addresses on This Assembly

0Ah

BYTE5

# of Module Banks on This Assembly

1 Bank

01h

BYTE6

Data Width of This Assembly

72 Bits

48h

BYTE7

Data Width of This Assembly (Continued)

00h

BYTE8

Voltage Interface Standard of This Assembly

LVTTL

01h

BYTE9

SDRAM Cycle Time @/CAS Latency=3

8ns

10ns

80h

A0h

BYTE10

Access Time from Clock @/CAS Latency=3

6ns

60h

BYTE11

DIMM Configuration Type

ECC

02h

BYTE12

Refresh Rate/Type

15.625us

/ Self Refresh Supported

80h

BYTE13

Primary SDRAM Width

08h

BYTE14

Error Checking SDRAM Width

08h

BYTE15

Minimum Clock Delay Back to Back Random Column
Address

tCCD = 1 CLK

01h

BYTE16

Burst Lenth Supported

1,2,4,8,Full Page

8Fh

BYTE17

# of Banks on Each SDRAM Device

4 Banks

04h

BYTE18

SDRAM Device Attributes, /CAS Lataency

/CAS Latency=2,3

06h

BYTE19

SDRAM Device Attributes, /CS Lataency

/CS Latency=0

01h

BYTE20

SDRAM Device Attributes, /WE Lataency

/WE Latency=0

01h

BYTE21

SDRAM Module Attributes

Neither Buffered nor Registered

00h

BYTE22

SDRAM Device Attributes, General

+/- 10% voltage tolerence, Burst

Read Single Bit Write,

Precharge All, Auto Precharge,

Early RAS Precharge

0Eh

BYTE23

SDRAM Cycle Time @/CAS Latency=2

8ns

10ns

12ns

A0h

C0h

BYTE24

Access Time from Clock @/CAS Latency=2

6ns

60h

BYTE25

SDRAM Cycle Time @/CAS Latency=1

00h

BYTE26

Access Time from Clock @/CAS Latency=1

00h

BYTE27

Minimum Row Precharge Time (tRP)

20ns

14h

BYTE28

Minimum Row Active to Row Active Delay (tRRD)

16ns

20ns

10h

14h

BYTE29

Minimum /RAS to /CAS Delay (tRCD)

20ns

14h

BYTE30

Minimum /RAS Pulse Width (tRAS)

48ns

50ns

30h

32h

BYTE31

Module Bank Density

128MB

20h

BYTE32

Command and Address Signal Input Setup Time

2ns

20h

BYTE33

Command and Address Signal Input Hold Time

1ns

10h

BYTE34

Data Signal Input Setup Time

2ns

20h

BYTE35

Data Signal Input Hold Time

1ns

10h

BYTE36
~61

Superset Information (may be used in future)

00h

BYTE62

SPD Revision

Intel SPD 1.2B

12h

3, 8

BYTE63

Checksum for Byte 0~62

E2h

28h

38h

BYTE64

Manufacturer JEDEC ID Code

Hynix JEDED ID

ADh

BYTE65
~71

....Manufacturer JEDEC ID Code

Unused

FFh

BYTE72

Manufacturing Location

HSI(Korea Area)

HSA (United States Area)

HSE (Europe Area)

HSJ (Japan Area)

HSS(Singapore)

Asia Area

0*h
1*h
2*h
3*h
4*h
5*h

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 6

HYM71V16M755HC(L)T8 Series

BYTE

NUMBER

FUNCTION

DESCRIPTION

FUNCTION

VALUE

NOTE

-8

-P

-S

-8

-P

-S

BYTE73

Manufacturer's Part Number (Component)

7 (SDRAM)

37h

4, 5

BYTE74

Manufacturer's Part Number (128Mb based)

31h

4, 5

BYTE75

Manufacturer's Part Number (Voltage Interface)

V (3.3V, LVTTL)

56h

4, 5

BYTE76

Manufacturer's Part Number (Memory Width)

31h

4, 5

BYTE77

....Manufacturer's Part Number (Memory Width)

36h

4, 5

BYTE78

Manufacturer's Part Number (Module Type)

M (SO DIMM)

4Dh

4, 5

BYTE79

Manufacturer's Part Number (Data Width)

37h

4, 5

BYTE80

....Manufacturer's Part Number (Data Width)

35h

4, 5

BYTE81

Manufacturer's Part Number (Refresh, SDRAM Bank)

5 (4K Refresh, 4Banks)

35h

4, 5

BYTE82

Manufacturer's Part Number (Manufacturing Site)

48h

4, 5

BYTE83

Manufacturer's Part Number (Generation)

43h

4, 5

BYTE84

Manufacturer's Part Number (Package Type)

54h

4, 5

BYTE85

Manufacturer's Part Number (Component Configuration)

8 (x8 based)

48h

4, 5

BYTE86

Manufacturer's Part Number (Hyphent)

- (Hyphen)

2Dh

4, 5

BYTE87

Manufacturer's Part Number (Min. Cycle Time)

38h

50h

53h

4, 5

BYTE88

~90

Manufacturer's Part Number

Blanks

20h

4, 5

BYTE91

Revision Code (for Component)

Process Code

4, 6

BYTE92

....Revision Code (for PCB)

Process Code

4, 6

BYTE93

Manufacturing Date

Year

3, 6

BYTE94

....Manufacturing Date

Work Week

3, 6

BYTE95

~98

Assembly Serial Number

Serial Number

BYTE99

~125

Manufacturer Specific Data (may be used in future)

None

00h

BYTE126

System Frequency Support

100MHz

64h

7, 8

BYTE127

Intel Specification Details for 100MHz Support

Refer to Note7

CFh

CDh

7, 8

BYTE128

~256

Unused Storage Locations

00h

Continued

Byte 84~88 for L-Part

BYTE

NUMBER

FUNCTION

DESCRIPTION

FUNCTION

VALUE

NOTE

-8

-P

-S

-8

-P

-S

BYTE84

Manufacturer's Part Number (Power)

4Ch

4, 5

BYTE85

Manufacturer's Part Number (Package Type)

54h

4, 5

BYTE86

Manufacturer's Part Number (Component Configuration)

8 (x8 based)

38h

4, 5

BYTE87

Manufacturer's Part Number (Hyphent)

- (Hyphen)

2Dh

4, 5

BYTE88

Manufacturer's Part Number (Min. Cycle Time)

38h

50h

53h

4, 5

Note :

1. The bank address is excluded

2. 1, 2, 4, 8 for Interleave Burst Type

3. BCD adopted

4. ASCII adopted

5. Basically Hynix writes Part No. except for `HYM' in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90

6. Not fixed but dependent

7. CK0, CK1 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support

8. Refer to Intel SPD Specification 1.2B

9. Refer to HSI Web site

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 7

HYM71V16M755HC(L)T8 Series

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability.

DC OPERATING CONDITION

=0 to 70

Note :
1.All voltages are referenced to V

= 0V

2.V

(max) is acceptable 5.6V AC pulse width with <=3ns of duration.

3.V

(min) is acceptable -2.0V AC pulse width with <=3ns of duration.

AC OPERATING TEST CONDITION

=0 to 70

C, V

=3.3

0.3V, V

=0V)

Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

Storage Temperature

STG

-55 ~ 125

Voltage on Any Pin relative to V

, V

OUT

-1.0 ~ 4.6

Voltage on V

relative to V

DD,

DDQ

-1.0 ~ 4.6

Short Circuit Output Current

Power Dissipation

Soldering Temperature

Time

SOLDER

260

Sec

Parameter

Symbol

Min

Typ

Max

Unit

Note

Power Supply Voltage

, V

DDQ

3.0

3.3

3.6

Input High voltage

2.0

3.0

DDQ

+ 0.3

1,2

Input Low voltage

-0.3

0.8

1,3

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

/ V

2.4/0.4

Input Timing Measurement Reference Level Voltage

Vtrip

1.4

Input Rise / Fall Time

tR / tF

Output Timing Measurement Reference Level Voltage

Voutref

1.4

Output Load Capacitance for Access Time Measurement

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 9

HYM71V16M755HC(L)T8 Series

DC CHARACTERISTICS I

(TA=0 to 70

C, V

=3.3

0.3V)

Note :

1.V

= 0 to 3.6V, All other pins are not tested under V

=0V

2.D

OUT

is disabled, V

OUT

=0 to 3.6

DC CHARACTERISTICS II

Note :
1. I

DD1

and I

DD4

depend on output loading and cycle rates. Specified values are measured with the output open

2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM71V16M755HCT8-8/P/S
4. HYM71V16M755HCLT8-8/P/S

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

-8

Output Leakage Current

-1

Output High Voltage

2.4

= -2mA

Output Low Voltage

0.4

= +2mA

Parameter

Symbol

Test Condition

Speed

Unit

Note

-8

-P

-S

Operating Current

DD1

Burst length=1, One bank active
t

(min), I

=0mA

800

Precharge Standby Current
in Power Down Mode

DD2P

CKE

(max), t

= min

DD2PS

CKE

(max), t

Precharge Standby Current
in Non Power Down Mode

DD2N

CKE

(min), CS

(min), t

= min

Input signals are changed one time during
2clks. All other pins

-0.2V or

0.2V

160

DD2NS

CKE

(min), t

Input signals are stable.

Active Standby Current
in Power Down Mode

DD3P

CKE

(max), t

= min

DD3PS

CKE

(max), t

Active Standby Current
in Non Power Down Mode

DD3N

CKE

(min), CS

(min), t

= min

Input signals are changed one time during
2clks. All other pins

-0.2V or

0.2V

320

DD3NS

CKE

(min), t

Input signals are stable.

320

Burst Mode Operating
Current

DD4

(min), I

=0mA

All banks active

CL=3

880

800

CL=2

800

Auto Refresh Current

DD5

RRC

(min), All banks active

1600

Self Refresh Current

DD6

CKE

0.2V

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 10

HYM71V16M755HC(L)T8 Series

AC CHARACTERISTICS I

(AC operating conditions unless otherwise noted)

Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter

Parameter

Symbol

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

System Clock
Cycle Time

CAS Latency = 3

tCK3

1000

CAS Latency = 2

tCK2

Clock High Pulse Width

tCHW

Clock Low Pulse Width

tCLW

Access Time
From Clock

CAS Latency = 3

tAC3

CAS Latency = 2

tAC2

Data-Out Hold Time

tOH

Data-Input Setup Time

tDS

Data-Input Hold Time

tDH

Address Setup Time

tAS

Address Hold Time

tAH

CKE Setup Time

tCKS

CKE Hold Time

tCKH

Command Setup Time

tCS

Command Hold Time

tCH

CLK to Data Output in Low-Z Time

tOLZ

CLK to Data
Output in High-Z
Time

CAS Latency = 3

tOHZ3

CAS Latency = 2

tOHZ2

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 11

HYM71V16M755HC(L)T8 Series

AC CHARACTERISTICS II

Note :
1. A new command can be given tRRC after self refresh exit

Parameter

Symbol

-8

-P

-S

Unit

Note

Min

Max

Min

Max

Min

Max

RAS Cycle Time

Operation

tRC

Auto Refresh

tRRC

RAS to CAS Delay

tRCD

RAS Active Time

tRAS

100K

RAS Precharge Time

tRP

RAS to RAS Bank Active Delay

tRRD

CAS to CAS Delay

tCCD

CLK

Write Command to Data-In Delay

tWTL

CLK

Data-In to Precharge Command

tDPL

CLK

Data-In to Active Command

tDAL

CLK

DQM to Data-Out Hi-Z

tDQZ

CLK

DQM to Data-In Mask

tDQM

CLK

MRS to New Command

tMRD

CLK

Precharge to Data
Output Hi-Z

CAS Latency = 3

tPROZ3

CLK

CAS Latency = 2

tPROZ2

CLK

Power Down Exit Time

tPDE

CLK

Self Refresh Exit Time

tSRE

CLK

Refresh Time

tREF

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 12

HYM71V16M755HC(L)T8 Series

DEVICE OPERATING OPTION TABLE

HYM71V16M755HC(L)T8-8

HYM71V16M755HC(L)T8-P

HYM71V16M755HC(L)T8-S

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

3CLKs

6CLKs

9CLKs

3CLKs

6ns

3ns

100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

83MHz(12ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

83MHz(12ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

3CLKs

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

83MHz(12ns)

2CLKs

5CLKs

7CLKs

2CLKs

6ns

3ns

66MHz(15ns)

2CLKs

4CLKs

6CLKs

2CLKs

6ns

3ns

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 13

HYM71V16M755HC(L)T8 Series

COMMAND TRUTH TABLE

Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don

t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1.

Command

CKEn-1

CKE

RAS

CAS

ADDR

A10/

Note

Mode Register Set

OP code

No Operation

Bank Active

Read

Read with Autoprecharge

Write

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

DQM

Auto Refresh

Burst-Read-Single-WRITE

A9 Pin High

(Other Pins OP code)

MRS

Mode

Self Refresh

Entry

Exit

Precharge power
down

Entry

Exit

Clock
Suspend

Entry

Exit

PC100 SDRAM SO DIMM

Rev. 0.1/May. 02 14

HYM71V16M755HC(L)T8 Series

PACKAGE DEMENSION

0.91

0.13

1.29

0.18

0.083

0.10

0.2

0.16±0.039

2.50

2.66

0.7

9
0

1.2

5
0

2 - 0.07

2-R 0.078 Min

0.15

0.16±0.0039

0.06±0.0039

0.01±Max

0.030 TYP

0 .024±0.001

0 .10

0.04±0.0039

0 .12

5
Min

0 .15

7
Min

0.150 Max

Detail Z

Detail Y

Tolerances : ±0.005 unless otherwise specified

Units : Inches

0.91

0.13

1.29

0.18

0.083

0.10

0.2

0.16±0.039

.
.

2.50

2.66

0.7

9
0

1.2

5
0

2 - 0.07

2-R 0.078 Min

0.15

0.16±0.0039

0.06±0.0039

0.01±Max

0.030 TYP

0 .024±0.001

0 .10

0.04±0.0039

0 .12

5
Min

0 .15

7
Min

0.150 Max

Detail Z

Detail Y

Tolerances : ±0.005 unless otherwise specified

Units : Inches

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