32Mx64bits
PC133 SDRAM Unbuffered DIMM
based on 16Mx8 SDRAM with LVTTL, 4 banks & 4K Refresh
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4/Dec. 01 2
HYM71V32635HCT8 Series
DESCRIPTION
The Hynix HYM71V32635HCT8 Series are 32Mx64bits Synchronous DRAM Modules. The modules are composed of sixteen
16Mx8bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin
glass-epoxy printed circuit board. One 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V32635HCT8 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 256Mbytes
memory. The Hynix HYM71V32635HCT8 Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
PC133/PC100MHz support
168pin SDRAM Unbuffered DIMM
Serial Presence Detect with EEPROM
1.25" (31.75mm) Height PCB with double sided com-
ponents
Single 3.3
0.3V power supply
All device pins are compatible with LVTTL interface
Data mask function by DQM
SDRAM internal banks : four banks
Module bank : two physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
HYM71V32635HCT8-K
133MHz
4 Banks
4K
Normal
TSOP-II
Gold
HYM71V32635HCT8-H
HYM71V32635HCLT8-K
Low Power
HYM71V32635HCLT8-H
PC133 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01 3
HYM71V32635HCT8 Series
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CK0~CK3
Clock Inputs
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE0, CKE1
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
/S0 ~ /S3
Chip Select
Enables or disables all inputs except CK, CKE and DQM
BA0, BA1
SDRAM Bank Address
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
/RAS, /CAS, /WE
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ63
Data Input/Output
Multiplexed data input / output pin
VCC
Power Supply (3.3V)
Power supply for internal circuits and input buffers
V
SS
Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
SA0~2
SPD Address Input
Serial Presence Detect Address Input
WP
Write Protect for SPD
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
No connection
PC133 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01 4
HYM71V32635HCT8 Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
1
VSS
85
VSS
41
VCC
125
CK1
2
DQ0
86
DQ32
42
CK0
126
NC
3
DQ1
87
DQ33
43
VSS
127
VSS
4
DQ2
88
DQ34
44
NC
128
CKE0
5
DQ3
89
DQ35
45
/S2
129
/S3
6
VCC
90
VCC
46
DQM2
130
DQM6
7
DQ4
91
DQ36
47
DQM3
131
DQM7
8
DQ5
92
DQ37
48
NC
132
NC
9
DQ6
93
DQ38
49
VCC
133
VCC
10
DQ7
94
DQ39
50
NC
134
NC
Architecture Key
51
NC
135
NC
52
NC
136
NC
11
DQ8
95
DQ40
53
NC
137
NC
12
VSS
96
VSS
54
VSS
138
VSS
13
DQ9
97
DQ41
55
DQ16
139
DQ48
14
DQ10
98
DQ42
56
DQ17
140
DQ49
15
DQ11
99
DQ43
57
DQ18
141
DQ50
16
DQ12
100
DQ44
58
DQ19
142
DQ51
17
DQ13
101
DQ45
59
VCC
143
VCC
18
VCC
102
VCC
60
DQ20
144
DQ52
19
DQ14
103
DQ46
61
NC
145
NC
20
DQ15
104
DQ47
62
NC
146
NC
21
NC
105
NC
63
CKE1
147
NC
22
NC
106
NC
64
VSS
148
VSS
23
VSS
107
VSS
65
DQ21
149
DQ53
24
NC
108
NC
66
DQ22
150
DQ54
25
NC
109
NC
67
DQ23
151
DQ55
26
VCC
110
VCC
68
VSS
152
VSS
27
/WE
111
/CAS
69
DQ24
153
DQ56
28
DQM0
112
DQM4
70
DQ25
154
DQ57
29
DQM1
113
DQM5
71
DQ26
155
DQ58
30
/S0
114
/S1
72
DQ27
156
DQ59
31
NC
115
/RAS
73
VCC
157
VCC
32
VSS
116
VSS
74
DQ28
158
DQ60
33
A0
117
A1
75
DQ29
159
DQ61
34
A2
118
A3
76
DQ30
160
DQ62
35
A4
119
A5
77
DQ31
161
DQ63
36
A6
120
A7
78
VSS
162
VSS
37
A8
121
A9
79
CK2
163
CK3
38
A10/AP
122
BA0
80
NC
164
NC
39
BA1
123
A11
81
WP
165
SA0
40
VCC
124
VCC
82
SDA
166
SA1
Voltage Key
83
SCL
167
SA2
84
VCC
168
VCC
PC133 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01 5
HYM71V32635HCT8 Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10ohms
PC133 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01 6
HYM71V32635HCT8 Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIPTION
FUNCTION
VALUE
NOTE
-K
-H
-K
-H
BYTE0
# of Bytes Written into Serial Memory at Module
Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
SDRAM
04h
BYTE3
# of Row Addresses on This Assembly
12
0Ch
1
BYTE4
# of Column Addresses on This Assembly
10
0Ah
BYTE5
# of Module Banks on This Assembly
2 Bank
02h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @/CAS Latency=3
7.5ns
7.5
75h
75h
BYTE10
Access Time from Clock @/CAS Latency=3
5.4ns
5.4
54h
54h
BYTE11
DIMM Configuration Type
None
00h
BYTE12
Refresh Rate/Type
15.625us
/ Self Refresh Supported
80h
BYTE13
Primary SDRAM Width
x8
08h
BYTE14
Error Checking SDRAM Width
None
00h
BYTE15
Minimum Clock Delay Back to Back Random Column
Address
tCCD = 1 CLK
01h
BYTE16
Burst Lenth Supported
1,2,4,8,Full Page
8Fh
2
BYTE17
# of Banks on Each SDRAM Device
4 Banks
04h
BYTE18
SDRAM Device Attributes, /CAS Lataency
/CAS Latency=2,3
06h
BYTE19
SDRAM Device Attributes, /CS Lataency
/CS Latency=0
01h
BYTE20
SDRAM Device Attributes, /WE Lataency
/WE Latency=0
01h
BYTE21
SDRAM Module Attributes
Neither Buffered nor Registered
00h
BYTE22
SDRAM Device Attributes, General
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
0Eh
BYTE23
SDRAM Cycle Time @/CAS Latency=2
7.5ns
10
75h
A0h
BYTE24
Access Time from Clock @/CAS Latency=2
5.4ns
6
54h
60h
BYTE25
SDRAM Cycle Time @/CAS Latency=1
-
-
00h
00h
BYTE26
Access Time from Clock @/CAS Latency=1
-
-
00h
00h
BYTE27
Minimum Row Precharge Time (tRP)
15ns
20ns
0Fh
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
15ns
15ns
0Fh
0Fh
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
15ns
20ns
0Fh
14h
BYTE30
Minimum /RAS Pulse Width (tRAS)
45ns
45ns
2Dh
2Dh
BYTE31
Module Bank Density
128MB
20h
BYTE32
Command and Address Signal Input Setup Time
1.5ns
1.5ns
15h
15h
BYTE33
Command and Address Signal Input Hold Time
0.8ns
0.8ns
08h
08h
BYTE34
Data Signal Input Setup Time
1.5ns
1.5ns
15h
15h
BYTE35
Data Signal Input Hold Time
0.8ns
0.8ns
08h
08h
BYTE36
~61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
Intel SPD1.2B
12h
3, 8
BYTE63
Checksum for Byte 0~62
-
6Fh
B0h
BYTE64
Manufacturer JEDEC ID Code
Hynix JEDED ID
ADh
BYTE65
~71
....Manufacturer JEDEC ID Code
Unused
FFh
BYTE72
Manufacturing Location
HSI (Korea Area)
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
HSS(Singapore)
Asia Area
0*h
1*h
2*h
3*h
4*h
5*h
11
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