64Mx72 bits

Unbuffered DDR SDRAM DIMM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2003 1

HYMD264726A8J

DESCRIPTION

Hynix HYMD264726A8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory
Modules (DIMMs) which are organized as 64Mx72 high-speed memory arrays. Hynix HYMD264726A8J series con-
sists of eighteen 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix
HYMD264726A8J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It
is suitable for easy interchange and addition.

Hynix HYMD264726A8J series is designed for high speed of up to 200MHz and offers fully synchronous operations
referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are
latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising
and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All
input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD264726A8J series incorporates SPD(serial presence detect). Serial presence detect function is imple-
mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

ORDERING INFORMATION

Part No.

Power Supply

Clock Frequency

Interface

Form Factor

HYMD264726A8J-J

DDQ

=2.5V

166MHz (DDR333)

SSTL_2

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

HYMD264726A8J-D4

DDQ

=2.6V

200MHz (DDR400)

SSTL_2

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

HYMD264726A8J-D43

DDQ

=2.6V

200MHz (DDR400)

SSTL_2

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

512MB (64M x 72) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)

Error Check Correction (ECC) Capability

2.5V +/- 0.2V VDD and VDDQ Power supply

2.6V +/- 0.1V VDD and VDDQ Power supply for
DDR400

All inputs and outputs are compatible with SSTL_2
interface

Fully differential clock operations (CK & /CK) with
125MHz/133MHz/166MHz/200MHz

All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock

Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock

Data inputs on DQS centers when write (centered
DQ)

Data strobes synchronized with output data for read
and input data for write

Programmable CAS Latency 3 / 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192refresh cycles / 64ms

PRELIMINARY

HYMD264726A8J

Rev. 0.2 / Apr. 2003 2

PIN DESCRIPTION

PIN ASSIGNMENT

Pin

Pin Description

Pin

Pin Description

CK0,/CK0,CK1,/CK1,CK2,/CK2

Differential Clock Inputs

VDDQ

DQs Power Supply

CS0, CS1

Chip Select Input

VSS

Ground

CKE0, CKE1

Clock Enable Input

VREF

Reference Power Supply

/RAS, /CAS, /WE

Commend Sets Inputs

VDDSPD

Power Supply for SPD

A0 ~ A12

Address

SA0~SA2

PROM Address Inputs

BA0, BA1

Bank Address

SCL

PROM Clock

DQ0~DQ63

Data Inputs/Outputs

SDA

PROM Data I/O

CB0~CB7

Check Bit

Write Protect Flag

DQS0~DQS7

Data Strobe Inputs/Outputs

VDDID

VDD Identification Flag

DM0~8

Data-in Mask

Do not Use

VDD

Power Supply

No Connection

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

VREF

VDDQ

VSS

124

VSS

154

/RAS

DQ0

DQ24

/WE

DQ4

125

155

DQ45

VSS

DQ41

DQ5

126

DQ28

156

VDDQ

DQ1

DQ25

/CAS

VDDQ

127

DQ29

157

/CS0

DQS0

DQS3

VSS

DM0

128

VDDQ

158

/CS1

DQ2

DQS5

DQ6

129

DM3

159

DM5

VDD

DQ42

DQ7

130

160

VSS

DQ3

DQ26

DQ43

100

VSS

131

DQ30

161

DQ46

DQ27

VDD

101

132

VSS

162

DQ47

102

133

DQ31

163

VSS

Vss

DQ48

103

A13*

134

CB4

164

VDDQ

DQ8

DQ49

104

VDDQ

135

CB5

165

DQ52

DQ9

CB0

VSS

105

DQ12

136

VDDQ

166

DQ53

DQS1

CB1

/CK2

106

DQ13

137

CK0

167

VDDQ

VDD

CK2

107

DM1

138

/CK0

168

VDD

CK1

DQS8

VDDQ

108

VDD

139

VSS

169

DM6

/CK1

DQS6

109

DQ14

140

DM8

170

DQ54

VSS

CB2

DQ50

110

DQ15

141

A10

171

DQ55

DQ10

VSS

DQ51

111

CKE1

142

CB6

172

VDDQ

DQ11

CB3

VSS

112

VDDQ

143

VDDQ

173

CKE0

BA1

VDDID

113

BA2*

144

CB7

174

DQ60

VDDQ

Key

DQ56

114

DQ20

key

175

DQ61

DQ16

DQ32

DQ57

115

A12

145

VSS

176

VSS

DQ17

VDDQ

VDD

116

VSS

146

DQ36

177

DM7

DQS2

DQ33

DQS7

117

DQ21

147

DQ37

178

DQ62

VSS

DQS4

DQ58

118

A11

148

VDD

179

DQ63

DQ34

DQ59

119

DM2

149

DM4

180

VDDQ

DQ18

VSS

120

VDD

150

DQ38

181

SA0

BA0

121

DQ22

151

DQ39

182

SA1

VDDQ

DQ35

SDA

122

152

VSS

183

SA2

DQ19

DQ40

SCL

123

DQ23

153

DQ44

184

VDDSPD

* These are not used on this module but may be used for other module in 184pin DIMM family

HYMD264726A8J

Rev. 0.2 / Apr. 2003 3

FUNCTIONAL BLOCK DIAGRAM

/CS

DQS

/CS

DQS

D10

/CS

DQS

/CS

DQS

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

/CS

DQS

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

/CS

DQS

/CS

DQS

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

/CS

DQS

DQ32
DQ33

DQ35
DQ36
DQ37
DQ38
DQ39

/CS

DQS

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

/CS

DQS

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

/CS

DQS

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

/CS

DQS

DM0

DQS0

DM4

DQS4

DQ8

DQ9

DM1

DQS1

DM2

DQS2

DM3

DQS3

DM7

DQS7

DM6

DQS6

DM5

DQS5

/CS0

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

/CS

DQS

D14

/CS

DQS

D16

/CS

DQS

D11

/CS1

D12

D15

D12

/CS

DQS

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

D13

DQ34

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

/CS

DQS

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

/CS

DQS

DM8

DQS8

D17

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O0

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

I/O0

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7

Strap:see Note 4

VDD SPD

VDD /VDDQ

VREF

VSS

VDDID

SPD

DO-D17

SCL

SDA

SA0 SA1 SA2

Serial PD

*Clock Wiring

Clock Input

SDRAMs

*CK0, /CK0
*CK1, /CK1
*CK2, /CK2

6 SDRAMs
6 SDRAMs
6 SDRAMs

*Wire per Clock Loading

Table/Wiring Diagrams

Note :

1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained
as shown.
3. DQ, DQS, DM/DQS resistors : 22 Ohms ± 5%.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN) : VDD = VDDQ

STRAP IN (VSS) : VDD V DDQ

5. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%

BA0-BA1

A0-A13

/RAS

/CAS

CKE0

/WE

BA0-BA1 : SDRAMs D0-D17

A0-A13 : SDRAMs D0-D17

/RAS : SDRAMs D0-D17

/CAS : SDRAMs D0-D17

CKE : SDRAMs D0-D8

/WE : SDRAMs D0-D17

CKE1

CKE : SDRAMs D9-D17

HYMD264726A8J

Rev. 0.2 / Apr. 2003 4

ABSOLUTE MAXIMUM RATINGS

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :
1. V

DDQ

must not exceed the level of V

2. V

(min) is acceptable -1.5V AC pulse width with < 5ns of duration.

3. The value of V

REF

is approximately equal to 0.5V

DDQ

4. For DDR400, VDD=2.6V +/- 0.1V, VDDQ=2.6V+/-0.1V

Parameter

Symbol

Rating

Unit

Ambient Temperature

0 ~ 70

Storage Temperature

STG

-55 ~ 125

Voltage on Inputs relative to V

-0.5 ~ 3.6

Voltage on I/O Pins relative to V

-0.5 ~ 3.6

Voltage on V

relative to V

-0.5 ~ 3.6

Voltage on V

DDQ

relative to V

DDQ

-0.5 ~ 3.6

Output Short Circuit Current

Power Dissipation

Soldering Temperature Þ Time

SOLDER

260 / 10

C / Sec

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

2.3

2.5

2.7

Power Supply Voltage

2.5

2.6

2.7

Power Supply Voltage

DDQ

2.3

2.5

2.7

Power Supply Voltage

DDQ

2.5

2.6

2.7

1,4

Input High Voltage

REF

+ 0.15

DDQ

+ 0.3

Input Low Voltage

-0.3

REF

- 0.15

Termination Voltage

REF

- 0.04

REF

+ 0.04

Reference Voltage

REF

0.49*V

DDQ

0.5*V

DDQ

0.51*V

DDQ

HYMD264726A8J

Rev. 0.2 / Apr. 2003 5

AC OPERATING CONDITIONS

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.

AC OPERATING TEST CONDITIONS

(TA=0 to 70

C, Voltage referenced to VSS = 0V)

Parameter

Symbol

Min

Max

Unit

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

IH(AC)

REF

+ 0.31

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

IL(AC)

REF

- 0.31

Input Differential Voltage, CK and /CK inputs

ID(AC)

0.7

DDQ

+ 0.6

Input Crossing Point Voltage, CK and /CK inputs

IX(AC)

0.5*V

DDQ

-0.2

0.5*V

DDQ

+0.2

Parameter

Value

Unit

Reference Voltage

DDQ

x 0.5

Termination Voltage

DDQ

x 0.5

AC Input High Level Voltage (V

, min)

REF

+ 0.31

AC Input Low Level Voltage (V

, max)

REF

- 0.31

Input Timing Measurement Reference Level Voltage

REF

Output Timing Measurement Reference Level Voltage

Input Signal maximum peak swing

1.5

Input minimum Signal Slew Rate

V/ns

Termination Resistor (R

)

Series Resistor (R

)

Output Load Capacitance for Access Time Measurement (C

)

HYMD264726A8J

Rev. 0.2 / Apr. 2003 6

CAPACITANCE

=25

C, f=100MHz )

Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, V

peak-to-peak = 0.2V

2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.

OUTPUT LOAD CIRCUIT

Parameter

Pin

Symbol

Min

Max

Unit

Input Capacitance

A0 ~ A12, BA0, BA1

IN1

TBD

Input Capacitance

/RAS, /CAS, /WE

IN2

TBD

Input Capacitance

CKE0, CKE1

IN3

TBD

Input Capacitance

CS0, CS1

IN4

TBD

Input Capacitance

CK0, /CK0, CK1, /CK1, CK2,/CK2

IN5

TBD

Input Capacitance

DM0 ~ DM8

IN6

TBD

Data Input / Output Capacitance

DQ0 ~ DQ63, DQS0 ~ DQS8

IO1

TBD

Data Input / Output Capacitance

CB0 ~ CB7

IO2

TBD

REF

=50

Zo=50

=30pF

Output

HYMD264726A8J

Rev. 0.2 / Apr. 2003 8

DC CHARACTERISTICS II

(TA=0 to 70

C, Voltage referenced to V

= 0V)

Parameter

Symbol

Test Condition

Speed

Unit

Note

D43

-J

Operating Current

IDD0

One bank; Active Precharge; tRC=tRC(min);
tCK=tCK(min); DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle

TBD

1485

Operating Current

IDD1

One bank; Active - Read Precharge; Burst Length
=2; tRC=tRC(min); tCK=tCK(min); address and
control inputs changing once per clock cycle

TBD

1890

Precharge Power
Down Standby Current

IDD2P

All banks idle; Power down mode; CKE=Low,
tCK=tCK(min)

TBD

360

Idle Standby Current

IDD2F

/CS=High, All banks idle ; tCK=tCK(min); CKE=
High; address and control inputs changing once
per clock cycle. VIN=VREF for DQ, DQS and DM

TBD

900

Active Power Down
Standby Current

IDD3P

One bank active; Power down mode; CKE=Low,
tCK=tCK(min)

TBD

450

Active Standby
Current

IDD3N

/CS=HIGH; CKE=HIGH; One bank; Active
Precharge; tRC=tRAS(max); tCK=tCK(min); DQ,
DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle

TBD

1080

Operating Current

IDD4R

Burst=2; Reads; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); IOUT=0mA

TBD

3150

Operating Current

IDD4W

Burst=2; Writes; Continuous burst; One bank
active; Address and control inputs changing once
per clock cycle; tCK=tCK(min); DQ, DM, and DQS
inputs changing twice per clock cycle

TBD

3150

Auto Refresh Current

IDD5

tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh

TBD

2610

Self Refresh Current

IDD6

CKE=<0.2V; External clock on;
tCK=tCK(min)

Normal

TBD

Low Power

TBD

Operating Current -
Four Bank Operation

IDD7

Four bank interleaving with BL=4 Refer to the
following page for detailed test condition

TBD

3375

HYMD264726A8J

Rev. 0.2 / Apr. 2003 9

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

DDR333

Unit

Note

Min

Max

Row Cycle Time

Auto Refresh Row Cycle Time

RFC

Row Active Time

RAS

70K

Active to Read with Auto Precharge Delay

RAP

Row Address to Column Address Delay

RCD

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

tWR

Last Data-In to Read Command

DRL

Auto Precharge Write Recovery + Precharge Time

DAL

(tWR/tCK)

(tRP/tCK)

System Clock Cycle Time

CL = 2.5

CL = 2

7.5

Clock High Level Width

0.45

0.55

Clock Low Level Width

0.45

0.55

Data-Out edge to Clock edge Skew

-0.7

0.7

DQS-Out edge to Clock edge Skew

DQSCK

-0.6

0.6

DQS-Out edge to Data-Out edge Skew

DQSQ

0.45

Data-Out hold time from DQS

-t

QHS

1, 10

Clock Half Period

min

(tCL,tCH)

1,9

Data Hold Skew Factor

QHS

0.55

Valid Data Output Window

-t

DQSQ

Data-out high-impedance window from CK, /CK

-0.7

0.7

Data-out low-impedance window from CK, /CK

-0.7

0.7

Input Setup Time (fast slew rate)

0.75

2,3,5,6

Input Hold Time (fast slew rate)

0.75

2,3,5,6

Input Setup Time (slow slew rate)

0.8

2,4,5,6

Input Hold Time (slow slew rate)

0.8

2,4,5,6

HYMD264726A8J

Rev. 0.2 / Apr. 2003

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

- continued -

Parameter

Symbol

DDR333

Unit

Note

Min

Max

Input Pulse Width

IPW

2.2

Write DQS High Level Width

DQSH

0.35

Write DQS Low Level Width

DQSL

0.35

Clock to First Rising edge of DQS-In

DQSS

0.75

1.25

Data-In Setup Time to DQS-In (DQ & DM)

0.45

6,7, 11~13

Data-in Hold Time to DQS-In (DQ & DM)

0.45

6,7, 11~13

DQ & DM Input Pulse Width

DIPW

1.75

Read DQS Preamble Time

RPRE

0.9

1.1

Read DQS Postamble Time

RPST

0.4

0.6

Write DQS Preamble Setup Time

WPRES

Write DQS Preamble Hold Time

WPREH

0.25

Write DQS Postamble Time

WPST

0.4

0.6

Mode Register Set Delay

MRD

Exit Self Refresh to Any Execute Command

XSC

200

Average Periodic Refresh Interval

REFI

7.8

HYMD264726A8J

Rev. 0.2 / Apr. 2003

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

Parameter

Symbol

DDR400 (D4)

DDR400 (D43)

Unit

Note

Min

Max

Min

Max

Row Cycle Time

Auto Refresh Row Cycle Time

RFC

Row Active Time

RAS

70K

Active to Read with Auto Precharge Delay

RAP

tRCD or

tRAS(min)

tRCD or

tRAS(min)

Row Address to Column Address Delay

RCD

Row Active to Row Active Delay

RRD

Column Address to Column Address Delay

CCD

Row Precharge Time

Write Recovery Time

tWR

Write to Read Command Delay

tWTR

Auto Precharge Write Recovery + Precharge Time

DAL

(tWR/tCK)

(tRP/tCK)

(tWR/tCK)

(tRP/tCK)

System Clock Cycle Time

CL = 3

Clock High Level Width

0.45

0.55

0.45

0.55

Clock Low Level Width

0.45

0.55

0.45

0.55

Data-Out edge to Clock edge Skew

-0.7

0.7

-0.7

0.7

DQS-Out edge to Clock edge Skew

DQSCK

-0.55

0.55

-0.55

0.55

DQS-Out edge to Data-Out edge Skew

DQSQ

0.4

Data-Out hold time from DQS

-t

QHS

-t

QHS

1, 10

Clock Half Period

min

(tCL,tCH)

min

(tCL,tCH)

1,9

Data Hold Skew Factor

QHS

0.5

Data-out high-impedance window from CK, /CK

tAC(Max)

Data-out low-impedance window from CK, /CK

tAC(min) tAC(Max) tAC(min) tAC(Max)

Input Setup Time (fast slew rate)

0.6

2,3,5,6

Input Hold Time (fast slew rate)

0.6

2,3,5,6

Input Setup Time (slow slew rate)

0.7

2,4,5,6

Input Hold Time (slow slew rate)

0.7

2,4,5,6

HYMD264726A8J

Rev. 0.2 / Apr. 2003

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

- continued -

Note :

This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.

Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.

For command/address input slew rate >=1.0V/ns

For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.

5. CK, /CK slew rates are >=1.0V/ns, ie, >=2.0V/ns differential.

6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by
design or tester correlation.

7. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.

Parameter

Symbol

DDR400 (D4)

DDR400 (D43)

Unit

Note

Min

Max

Min

Max

Input Pulse Width

IPW

2.2

Write DQS High Level Width

DQSH

0.35

Write DQS Low Level Width

DQSL

0.35

Clock to First Rising edge of DQS-In

DQSS

0.72

1.28

0.72

1.28

DQS falling edge to CK setup time

DSS

0.2

DQS falling edge hold time from CK

DSH

0.2

Data-In Setup Time to DQS-In (DQ & DM)

0.4

6,7,11,

12,13

Data-in Hold Time to DQS-In (DQ & DM)

0.4

DQ & DM Input Pulse Width

DIPW

1.6

Read DQS Preamble Time

RPRE

0.9

1.1

0.9

1.1

Read DQS Postamble Time

RPST

0.4

0.6

0.4

0.6

Write DQS Preamble Setup Time

WPRES

Write DQS Preamble Hold Time

WPREH

0.25

Write DQS Postamble Time

WPST

0.4

0.6

0.4

0.6

Mode Register Set Delay

MRD

Exit self refresh to non-READ command

XSNR

200

Exit self refresh to READ command

XSRD

200

Average Periodic Refresh Interval

REFI

7.8

Input Setup / Hold Slew-rate

Delta tIS

Delta tIH

V/ns

0.5

0.4

+50

0.3

+100

HYMD264726A8J

Rev. 0.2 / Apr. 2003

8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.

9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).

10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel
to n-channel variation of the output drivers.

This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.

Input Setup / Hold Slew-rate Derating Table.

12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below
VREF +/-310mV for a duration of up to 2ns.

13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate
1=0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times.
Signal transi tions through the DC region must be monotonic.

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clock

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be
tRAS - BL/2 x tCK.

17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced
to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).

Input Setup / Hold Slew-rate

Delta tDS

Delta tDH

V/ns

0.5

0.4

+75

0.3

+150

I/O Input Level

Delta tDS

Delta tDH

+280

+50

(1/SlewRate1)-(1/SlewRate2)

Delta tDS

Delta tDH

ns/V

+/-0.25

+50

+/- 0.5

+100

HYMD264726A8J

Rev. 0.2 / Apr. 2003

SIMPLIFIED COMMAND TRUTH TABLE

Note :
1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A

and BA

~BA

used for Mode Registering duing Extended MRS or MRS.

Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+t

4. If a Write with Autoprecharge command is detected by memory compoment in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+t

DPL

). Last Data-In to Prechage delay(t

DPL

) which is also called Write Recovery Time

(tWR) is needed to guarantee that the last data has been completely written.
5. If A

/AP is High when Row Precharge command being issued, BA

/BA

are ignored and all banks are selected to be

precharged.

Command

CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

ADDR

A10/

Note

Extended Mode Register Set

OP code

1,2

Mode Register Set

OP code

1,2

Device Deselect

No Operation

Bank Active

Read

Read with Autoprecharge

1,3

Write

Write with Autoprecharge

1,4

Precharge All Banks

1,5

Precharge selected Bank

Read Burst Stop

Auto Refresh

Self Refresh

Entry

Exit

Precharge
Power Down
Mode

Entry

Exit

Active Power
Down Mode
(Clock Suspend)

Entry

Exit

( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

HYMD264726A8J

Rev. 0.2 / Apr. 2003

SERIAL PRESENCE DETECT

Byte#

Function Description

Function Supported

Hexa Value

Note

D43

Number of Bytes written into serial memory at module manufac-
turer

128 Bytes

80h

Total number of Bytes in SPD device

256 Bytes

08h

Fundamental memory type

DDR SDRAM

07h

Number of row address on this assembly

0Dh

Number of column address on this assembly

0Ah

Number of physical banks on DIMM

2Banks

02h

Module data width

72 Bits

48h

Module data width (continued)

00h

Module voltage Interface levels(VDDQ)

SSTL 2.5V

04h

DDR SDRAM cycle time at CAS Latency=2.5(tCK)@DDR333,
3(tCK)@DDR400

5.0ns

6.0ns

50h

60h

DDR SDRAM access time from clock at CL=2.5 (tAC)

+/-0.7ns

70h

Module configuration type

ECC

02h

Refresh rate and type

7.8us & Self refresh

82h

Primary DDR SDRAM width

08h

Error checking DDR SDRAM data width

08h

Minimum clock delay for back-to-back random column
address(tCCD)

1 CLK

01h

Burst lengths supported

2,4,8

0Eh

Number of banks on each DDR SDRAM

4 Banks

04h

CAS latency supported

2, 2.5, 3

2, 2.5

1Ch

0Ch

CS latency

01h

WE latency

02h

DDR SDRAM module attributes

Differential Clock Input

20h

DDR SDRAM device attributes : General

+/-0.2Voltage tolerance,

Concurrent Auto Precharge

tRAS Lock Out

C0h

DDR SDRAM cycle time at CL=2.0(tCK), 2.5(tCK)

6ns

7.5ns

60h

75h

DDR SDRAM access time from clock at CL=2.0(tAC), 2.5(tAC)

+/-0.7ns

70h

DDR SDRAM cycle time at CL=1.5(tCK), 2.0(tCK)

7.5ns

75h

00h

DDR SDRAM access time from clock at CL=1.5(tAC), 2.0(tAC)

+/-0.75ns +/-0.75ns

75h

00h

Minimum row precharge time(tRP)

15ns

18ns

3Ch

48h

Minimum row activate to row active delay(tRRD)

10ns

12ns

28h

30h

Minimum RAS to CAS delay(tRCD)

15ns

18ns

3Ch

48h

Minimum active to precharge time(tRAS)

40ns

40n

42ns

28h

2Ah

Module row density

256MB

40h

Command and address signal input setup time(tIS)

0.6ns

0.75ns

60h

75h

Command and address signal input hold time(tIH)

0.6ns

0.75ns

60h

75h

Data signal input setup time(tDS)

0.4ns

0.45ns

40h

45h

Data signal input hold time(tDH)

0.4ns

0.45ns

40h

45h

36~40 Reserved for VCSDRAM

Undefined

00h

Minimum active / auto-refresh time ( tRC)

55ns

58ns

60ns

37h

3Ah

3Ch

Minimum auto-refresh to active/auto-refresh
command period(tRFC)

70ns

72ns

46h

48h

Maximum cycle time (tCK max)

10ns

12ns

28h

30h

Maximim DQS-DQ skew time(tDQSQ)

0.4ns

0.45ns

28h

2Dh

Maximum read data hold skew factor(tQHS)

0.50ns

0.55ns

50h

55h

46~61 Superset information(Reserved for IDD values, Tcase, etc.)

Undefined

00h

SPD Revision code

Initial release

00h

Checksum for Bytes 0~62

79h

94h

13h

Manufacturer JEDEC ID Code

Hynix JEDEC ID

ADh

65~71 --------- Manufacturer JEDEC ID Code

00h

Bin Sort : J(DDR333@CL=2.5), D4/D43(DDR400@CL=3)

HYMD264726A8J

Rev. 0.2 / Apr. 2003

SERIAL PRESENCE DETECT

- continued -

Note :
1. The bank address is excluded
2. These value is based on the component specification
3. These bytes are programmed by code of date week & date year
4. These bytes apply to Hynix's own Module Serial Number system
5. These bytes undefined and coded as `00h'
6. Refer to Hynix web site

Byte #

Function Description

Function Supported

Hexa Value

Note

D43

Manufacturing location

Hynix(Korea Area)

HSA(United States Area)

HSE(Europe Area)

HSJ(Japan Area)

Singapore

Asia Area

0*h
1*h
2*h
3*h
4*h
5*h

Manufacture part number(Hynix Memory Module)

48h

-------- Manufacture part number(Hynix Memory Module)

59h

-------- Manufacture part number(Hynix Memory Module)

4Dh

Manufacture part number (DDR SDRAM)

44h

Manufacture part number(Memory density)

32h

Manufacture part number(Module Depth)

36h

------- Manufacture part number(Module Depth)

34h

Manufacture part number(Module type)

Blank

20h

Manufacture part number(Data width)

37h

-------Manufacture part number(Data width)

32h

Manufacture part number(Refresh, # of Bank.)

6(8K refresh,4Bank)

36h

Manufacture part number(Component Generation)

41h

Manufacture part number(Component configuration)

38h

Manufacture part number(Module Type)

4Ah

Manufacture part number(Hyphen)

`-'

2Dh

Manufacture part number(Minimum cycle time)

44h

4Ah

Manufacture part number(Minimum cycle time)

Blank

34h

20h

Manufacture part number(Minimum cycle time

Blank

33h

20h

Manufacture revision code(for Component)

Manufacture revision code (for PCB)

Manufacturing date(Year)

Manufacturing date(Week)

95~98

Module serial number

99~127

Manufacturer specific data (may be used in future)

Undefined

00h

128~255 Open for customer use

Undefined

00h

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