Motorola Inc. 1997. All rights reserved.
Portions hereof International Business Machines Corp. 19911997. All rights reserved.
This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or
discontinue this product without notice. Information in this document is provided solely to enable system and software implementers to use PowerPC
microprocessors. There are no express or implied copyright or patent licenses granted hereunder by Motorola or IBM to design, modify the design of, or
fabricate circuits based on the information in this document.
The PowerPC microprocessor embodies the intellectual property of Motorola and of IBM. However, neither Motorola nor IBM assumes any responsibility
or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party.
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Accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party.
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THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS, AND OTHER SUPPORTING DOCUMENTATION, SHALL BE
INTERPRETED AS THE CONVEYANCE BY MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY,
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PURPOSE
. Neither Motorola nor IBM assumes any liability or obligation for damages of any kind arising out of the application or use of these materials.
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"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals," must be validated for each customer
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Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
IBM, the IBM logo, and IBM Microelectronics are trademarks of International Business Machines Corporation.
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Contents
iii
CONTENTS
Paragraph
Number
Title
Page
Number
About This Document
Audience .............................................................................................................. xvi
Organization......................................................................................................... xvi
Suggested Reading.............................................................................................. xvii
Conventions ...........................................................................................................xx
Acronyms and Abbreviations .............................................................................. xxi
Chapter 1
Overview
1.1
PowerPC 60x Microprocessor Interface .............................................................. 1-1
1.2
PowerPC System Block Diagram ........................................................................ 1-3
1.3
Processor Bus Features ........................................................................................ 1-3
1.4
Bus Interface Signals ........................................................................................... 1-4
Chapter 2
Signal Descriptions
2.1
Address Bus Arbitration Signals.......................................................................... 2-2
2.1.1
Bus Request (
BR
)--Output ............................................................................. 2-2
2.1.2
Bus Grant (
BG
)--Input ................................................................................... 2-2
2.1.3
Address Bus Busy (
ABB
)--Output ................................................................. 2-3
2.1.4
Address Bus Busy (
ABB
)--Input.................................................................... 2-4
2.2
Address Transfer Start Signals............................................................................. 2-4
2.2.1
Transfer Start (
TS
)--Output ............................................................................ 2-4
2.2.2
Transfer Start (
TS
)--Input............................................................................... 2-5
2.2.3
Extended Address Transfer Start (
XATS
)--Output (Direct-Store)................. 2-5
2.2.4
Extended Address Transfer Start (
XATS
)--Input (Direct-Store) ................... 2-5
2.3
Address Transfer Signals ..................................................................................... 2-6
2.3.1
Address Bus (A[031])--Output (Memory Operations)................................. 2-6
2.3.2
Address Bus (A[031])--Input (Memory Operations) ................................... 2-6
2.3.3
Address Bus (A[031])--Output (Direct-Store Operations)........................... 2-6
2.3.4
Address Bus (A[031])--Input (Direct-Store Operations) ............................. 2-7
2.3.5
Address Bus Parity (AP[03])--Output .......................................................... 2-7
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