PowerPC 740 and PowerPC 750
Microprocessor Datasheet
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Version 2.0
09/6/2002
IBM Microelectronics Division
Notices
Before using this information and the product it supports, be sure to read the general information on the
back cover of this book.
Trademarks
The following are trademarks of International Business Machines Corporation in the United States, or
other countries, or both:
IBM
IBM Logo
PowerPC
AIX
PowerPC 750
PowerPC 740
Other company, product, and service names may be trademarks or service marks of others.
This document contains information on a new product under development by IBM. IBM reserves the
right to change or discontinue this product without notice.
International Business Machines Corporation 2001, 2002.
All rights reserved.
09/06/2002
Version 2.0
Page 3
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Table of Contents
Preface ..................................................................................................................................................... 5
New Features for dd3.x ............................................................................................................................ 5
Overview................................................................................................................................................... 6
Features ................................................................................................................................................... 7
General Parameters ................................................................................................................................. 9
Electrical and Thermal Characteristics ................................................................................................... 10
DC Electrical Characteristics .............................................................................................................. 10
AC Electrical Characteristics .................................................................................................................. 14
Clock AC Specifications ...................................................................................................................... 14
Spread Spectrum Clock Generator (SSCG) ....................................................................................... 15
60x Bus Input AC Specifications ......................................................................................................... 16
60x Bus Output AC Specifications ...................................................................................................... 18
L2 Clock AC Specifications ................................................................................................................. 20
L2 Bus Input AC Specifications ........................................................................................................... 22
L2 Bus Output AC Specifications ........................................................................................................ 23
IEEE 1149.1 AC Timing Specifications .................................................................................................. 25
PowerPC 740 Microprocessor Pin Assignments .................................................................................... 27
PowerPC 740 Package .......................................................................................................................... 30
Mechanical Dimensions of the PowerPC 740 255 CBGA Package .................................................... 31
PowerPC 750 Microprocessor Pin Assignments .................................................................................... 32
PowerPC 750 Package .......................................................................................................................... 35
Mechanical Dimensions of the PowerPC 750 360 CBGA Package .................................................... 36
System Design Information .................................................................................................................... 38
PLL Power Supply Filtering ................................................................................................................. 41
Decoupling Recommendations ........................................................................................................... 41
Connection Recommendations ........................................................................................................... 41
Output Buffer DC Impedance .............................................................................................................. 42
Pull-up Resistor Requirements ........................................................................................................... 43
Thermal Management Information ...................................................................................................... 45
Internal Package Conduction Resistance ........................................................................................... 46
Heat Sink Selection Example .............................................................................................................. 48
Ordering Information............................................................................................................................... 51
09/06/2002
Version 2.0
Page 4
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Page 5
Version 2.0
9/6/2002
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Preface
The PowerPC 740
and PowerPC 750
are members of the PowerPC
family of reduced instruction set
computer (RISC) microprocessors. The PPC740L and PPC750L microprocessors are the PID-8p implemen-
tations of the PowerPC 740 and PowerPC 750 in IBM CMOS 7S 0.20
m copper technology. They are
referred to in the body of this document as "740" and "750."
Information in this document does not apply to implementations of the PowerPC 740 and PowerPC 750 in
other technologies, such as the PID-8t.
The information in this document is also specific to revision level dd3.2 of the (PID-8p) PPC740L and
PPC750L, and does not apply to previous revisions.
This document is generally written in terms of the 750. Unless otherwise noted, information that applies to the
750 also applies to the 740. Exceptions are detailed.
The 740 uses the same die as the 750, but the 740 does not bring the L2 cache interface out to external
package pins.
New Features for dd3.x
Selectable I/O voltages on 60X bus and L2 bus. See "Recommended Operating Conditions," on page 11.
Older revs must leave these pins "no connect" or "tied high" for 3.3v I/Os. AC timings are the same for all
I/O voltages modes unless otherwise noted.
60X bus:core frequency ratios now also support the 10x ratio. See "PLL Configuration," on page 40.
Extra output hold on the 60x bus by L2_TSTCLK pin tied low is no longer available. The L2_TSTCLK pin
must now be tied to OV
DD
for normal operation. See "60X Bus Output AC Timing Specifications for the
750
1
," on page 18.
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