ChipFind - документация

Электронный компонент:

Скачать:  PDF   ZIP

Document Outline

cddrh251620.07
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 26
IBM0418A8CFLBB
IBM0436A8CFLBB
IBM0418A4CFLBB
IBM0436A4CFLBB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Features
8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
CMOS Technology
Double Data Rate and Single Data Rate Syn-
chronous Modes of Operation
Pipeline Mode of Operation
Self-Timed Late Write with Full Data Coherency
Single Differential Extended HSTL Clock
+2.5V Power Supply, Ground, 1.6V V
DDQ
, and
1.05V V
REF
Extended HSTL Input
HSTL Outputs
Registered Addresses, Controls, and Data Ins
Burst Mode of operation
Common I/O
Asynchronous Output Enable
Boundary Scan using limited set of JTAG
1149.1 functions
9 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Programmable Impedance Output Drivers
Description
The IBM0436A4CFLBB, IBM0418A4CFLBB,
IBM0418A8CFLBB, and IBM0436A8CFLBB
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 3.0ns
cycle times. Differential CK clocks are used to ini-
tiate the read/write operation and all internal opera-
tions are self-timed. At the rising edge of the CK
clock, all Addresses, Controls, and Data Ins are reg-
istered internally. Data Outs are updated from out-
put registers off the next rising and falling edge of
the K clock, hence the Double Data Rate. Internal
Write buffers allow write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
.
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 26
cddrh251620.07
12/00
x36 BGA Pinout
(Top View)
1
2
3
4
5
6
7
8
9
A
V
SS
V
DDQ
SA
SA
ZQ
SA
SA
V
DDQ
V
SS
B
DQ
DQ
SA
V
SS
B1(LD)
V
SS
SA
DQ
DQ
C
V
SS
V
DDQ
SA
SA
G
SA
SA
V
DDQ
V
SS
D
DQ
DQ
NC
V
SS
V
DD
VSS
SA(8M)
DQ
DQ
E
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
F
DQ
CQ
DQ
V
DD
V
DD
V
DD
DQ
CQ
DQ
G
V
SS
V
DDQ
V
SS
V
SS
CK
V
SS
V
SS
V
DDQ
V
SS
H
DQ
DQ
DQ
V
DD
CK
V
DD
DQ
DQ
DQ
J
V
SS
V
DDQ
V
SS
V
DD
V
DD
V
DD
V
SS
V
DDQ
V
SS
K
DQ
DQ
DQ
V
SS
B2(WE)
V
SS
DQ
DQ
DQ
L
V
SS
V
DDQ
V
SS
LBO
B3(DDR)
NC
V
SS
V
DDQ
V
SS
M
DQ
CQ
DQ
V
DD
V
DD
V
DD
DQ
CQ
DQ
N
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
P
DQ
DQ
NC
V
SS
V
DD
V
SS
SA
DQ
DQ
R
V
SS
V
DDQ
V
DD
SA
SA1
SA
V
DD
V
DDQ
V
SS
T
DQ
DQ
SA
V
SS
SA0
V
SS
SA
DQ
DQ
U
V
SS
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
V
SS
x18 BGA Pinout
(Top View)
1
2
3
4
5
6
7
8
9
A
V
SS
V
DDQ
SA
SA
ZQ
SA
SA
V
DDQ
V
SS
B
NC
DQ
SA
V
SS
B1(LD)
V
SS
SA
NC
DQ
C
V
SS
V
DDQ
SA
SA
G
SA
SA
V
DDQ
V
SS
D
DQ
NC
NC
V
SS
V
DD
V
SS
SA(8M)
DQ
NC
E
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
F
NC
CQ
NC
V
DD
V
DD
V
DD
DQ
NC
DQ
G
V
SS
V
DDQ
V
SS
V
SS
CK
V
SS
V
SS
V
DDQ
V
SS
H
DQ
NC
DQ
V
DD
CK
V
DD
NC
DQ
NC
J
V
SS
V
DDQ
V
SS
V
DD
V
DD
V
DD
V
SS
V
DDQ
V
SS
K
NC
DQ
NC
V
SS
B2(WE)
V
SS
DQ
NC
DQ
L
V
SS
V
DDQ
V
SS
LBO
B3(DDR)
NC
V
SS
V
DDQ
V
SS
M
DQ
NC
DQ
V
DD
V
DD
V
DD
NC
CQ
NC
N
V
SS
V
DDQ
V
SS
V
DD
V
REF
V
DD
V
SS
V
DDQ
V
SS
P
NC
DQ
SA
V
SS
V
DD
V
SS
SA
NC
DQ
R
V
SS
V
DDQ
V
DD
SA
SA1
SA
V
DD
V
DDQ
V
SS
T
DQ
NC
SA
V
SS
SA0
V
SS
SA
DQ
NC
U
V
SS
V
DDQ
TMS
TDI
TCK
TDO
NC
V
DDQ
V
SS
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
cddrh251620.07
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 26
Pin Description
SA0-SA18
Address Inputs
SA0-SA1 Burst control starting addresses
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels)
DQ0-DQ35
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
TDO
IEEE 1149.1 Test Output (LVTTL level)
CQ, CQ
Output Differential Echo Clocks
V
REF
(2)
Extended HSTL Input Reference Voltage
CK, CK
Differential Input Register Clocks
V
DD
Power Supply (+2.5V)
B1
Synchronous Function Control Input. B1 = 0
Loads a new Address
V
SS
Ground
B2
Synchronous Function Control Input (WE). B2
= 0 starts Write & B2 = 1 starts Read.
V
DDQ
Output Power Supply
B3
Synchronous Function Control Input. B3 = 0
starts a DDR (Burst) operation. B3 = 1 starts a
SDR (Single Data Rate)
ZQ
Input pin for Output Driver Impedance Control.
LBO
Linear Burst Order, (LBO =1 interleave mode,
LBO = 0 linear mode)
NC
No Connect
G
Asynchronous Output Enable
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 26
cddrh251620.07
12/00
Ordering Information
Part Number
Organization
Speed
Leads
IBM0418A4CFLBB-3P
256K x 18
1.7ns Access / 3.0ns Cycle
9 x 17 BGA
IBM0418A4CFLBB-3
256K x 18
1.8ns Access / 3.5ns Cycle
9 x 17 BGA
IBM0418A4CFLBB-4
256K x 18
2.0ns Access / 4.0ns Cycle
9 x 17 BGA
IBM0418A4CFLBB-4H
256K x 18
2.0ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0418A4CFLBB-5
256K x 18
2.5ns Access / 5.0ns Cycle
9 x 17 BGA
IBM0436A4CFLBB-3P
128K x 36
1.7ns Access / 3.0ns Cycle
9 x 17 BGA
IBM0436A4CFLBB-3
128K x 36
1.8ns Access / 3.5ns Cycle
9 x 17 BGA
IBM0436A4CFLBB-4
128K x 36
2.0ns Access / 4.0ns Cycle
9 x 17 BGA
IBM0436A4CFLBB-4H
128K x 36
2.0ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0436A4CFLBB-5
128K x 36
2.5ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0418A8CFLBB-3P
512K x 18
1.7ns Access / 3.0ns Cycle
9 x 17 BGA
IBM0418A8CFLBB-3
512K x 18
1.8ns Access / 3.5ns Cycle
9 x 17 BGA
IBM0418A8CFLBB-4
512K x 18
2.0ns Access / 4.0ns Cycle
9 x 17 BGA
IBM0418A8CFLBB-4H
512K x 18
2.0ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0418A8CFLBB-5
512K x 18
2.5ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0436A8CFLBB-3P
256K x 36
1.7ns Access / 3.0ns Cycle
9 x 17 BGA
IBM0436A8CFLBB-3
256K x 36
1.8ns Access / 3.5ns Cycle
9 x 17 BGA
IBM0436A8CFLBB-4
256K x 36
2.0ns Access / 4.0ns Cycle
9 x 17 BGA
IBM0436A8CFLBB-4H
256K x 36
2.0ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0436A8CFLBB-5
256K x 36
2.5ns Access / 4.5ns Cycle
9 x 17 BGA
IBM0418A8CFLBB IBM0436A8CFLBB
IBM0418A4CFLBB IBM0436A4CFLBB
Preliminary
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
cddrh251620.07
12/00
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 26
Block Diagram
(x36 Double Data Rate Mode)
Logic
128Kx72
Buffer
Write
Decode
0
2:1 MUX
DQ0-DQ35
Compare
CK, CK
B1-B3
SA0-SA18
Array
G
1
0
1
Buffer
Write
0
1
0
1
REG
Output
Output
REG
0
1
36
36
36
36
36
36
36
36
REG
Output
Output
REG
0
1
4
4
CQa, CQa
CQb, CQb
0
1
0
1
E
E
V
DD
V
SS
E
E
Burst
A2-A18
A0,A1
A0', A1'
A0'
A0'
A0'
A0'
Control
Logic
Load
Write
Output Enable
E
Advance
Match
36
36
Read
Address
Register
Write
Address
Register