Document Outline

• Contents
• List of Tables
• List of Figures
• About This Book
  • Who Should Read This Manual
  • Related Publications
  • Conventions Used in This Manual
• 1. General Information
  • 1.1 Features
  • 1.2 Ordering Information
  • 1.3 Overview
  • 1.4 NP4GS3-Based Systems
    • Figure1-1. Function Placement in an NP4GS3-Based System
  • 1.5 Structure
    • Figure1-2. NP4GS3 Major Functional Blocks
    • 1.5.1 EPC Structure
      • 1.5.1.1 Coprocessors
      • 1.5.1.2 Enhanced Threads
      • 1.5.1.3 Hardware Accelerators
    • 1.5.2 NP4GS3 Memory
  • 1.6 Data Flow
    • Figure1-3. Data Flow Overview
    • 1.6.1 Basic Data Flow
    • 1.6.2 Data Flow in the EPC
      • Figure1-4. Basic Data Flow in the EPC
• 2. Physical Description
  • Figure2-1. Device Interfaces
  • 2.1 Pin Information
    • Table2-1. Signal Pin Functions
    • 2.1.1 Packet Routing Switch Interface Pins
      • Table2-2. IBM 28.4 Gbps Packet Routing Switch Interface Pins
    • 2.1.2 Flow Control Interface Pins
      • Table2-3. Flow Control Pins
    • 2.1.3 ZBT Interface Pins
      • Table2-4. Z0 ZBT SRAM Interface Pins
      • Table2-5. Z1 ZBT SRAM Interface Pins
      • Figure2-2. ZBT SRAM Timing Diagram
      • Table2-6. ZBT SRAM Timing Diagram Legend (for Figure 2-2)
    • 2.1.4 DDR DRAM Interface Pins
      • Figure2-3. DDR Control Timing Diagram
      • Figure2-4. DDR Read Timing Diagram
      • Figure2-5. DDR Write Output Timing Diagram
      • Table2-7. DDR Timing Diagram Legend (for Figure 2-3, Figure 2-4, and Figure 2-5)
      • Table2-8. DDR Timing Diagram Legend (for Figure 2-3, Figure 2-4, and Figure 2-5)
      • Table2-9. DDR Timing Diagram Legend (for Figure 2-3, Figure 2-4, and Figure 2-5)
      • 2.1.4.1 D3, D2, D1, and D0 Interface Pins
        • Table2-10. D3, D2, and D1 Interface Pins
        • Table2-11. D0 Memory Pins
      • 2.1.4.2 D4_0 and D4_1 Interface Pins
        • Table2-12. D4_0 and D4_1 Interface Pins
      • 2.1.4.3 D6_x Interface Pins
        • Table2-13. D6_5, D6_4, D6_3, D6_2, D6_1, and D6_0 Memory Pins
      • 2.1.4.4 DS1 and DS0 Interface Pins
        • Table2-14. DS1 and DS0 Interface Pins
    • 2.1.5 PMM Interface Pins
      • Table2-15. PMM Interface Pins
      • Table2-16. PMM Interface Pin Multiplexing
      • Figure2-6. NP4GS3 DMU Bus Clock Connections
      • Figure2-7. NP4GS3 DMU Bus Clock Connections (POS Overview)
      • 2.1.5.1 TBI Bus Pins
        • Table2-17. PMM Interface Pins: Debug (DMU_D Only)
        • Table2-18. Parallel Data Bit to 8B/10B Position Mapping (TBI Interface)
        • Table2-19. PMM Interface Pins: TBI Mode
        • Figure2-8. TBI Timing Diagram
        • Table2-20. TBI Timing Diagram Legend (for Figure 2-8)
      • 2.1.5.2 GMII Bus Pins
        • Table2-21. PMM Interface Pins: GMII Mode
        • Figure2-9. GMII Timing Diagram
        • Table2-22. GMII Timing Diagram Legend (for Figure 2-9)
      • 2.1.5.3 SMII Bus Pins
        • Table2-23. PMM Interface Pins: SMII Mode
        • Figure2-10. SMII Timing Diagram
        • Table2-24. SMII Timing Diagram Legend (for Figure 2-10)
      • 2.1.5.4 POS Bus Pins
        • Table2-25. PMM Interface Pins POS32 Mode
        • Table2-26. POS Signals
        • Figure2-11. POS Transmit Timing Diagram
        • Figure2-12. POS Receive Timing Diagram
        • Table2-27. POS Timing Diagram Legend (for Figure 2-11 and Figure 2-12)
    • 2.1.6 PCI Pins
      • Table2-28. PCI Pins
      • Figure2-13. PCI Timing Diagram
      • Table2-29. PCI Timing Diagram Legend (for Figure 2-13)
    • 2.1.7 Management Bus Interface Pins
      • Table2-30. Management Bus Pins
      • Figure2-14. SPM Bus Timing Diagram
      • Table2-31. SPM Bus Timing Diagram Legend (for Figure 2-14)
    • 2.1.8 Miscellaneous Pins
      • Table2-32. Miscellaneous Pins
      • Table2-33. Signals Requiring Pull-Up or Pull-Down
    • 2.1.9 PLL Filter Circuit
      • Figure2-15. PLL Filter Circuit Diagram
    • 2.1.10 Thermal I/O Usage
      • Figure2-16. Thermal Monitor
      • 2.1.10.1 Temperature Calculation
      • 2.1.10.2 Measurement Calibration
  • 2.2 Clocking Domains
    • Figure2-17. Clock Generation and Distribution
    • Figure2-18. Pins Diagram
  • 2.3 Mechanical Specifications
    • Figure2-19. Mechanical Diagram
    • Table2-34. Mechanical Specifications
  • 2.4 IEEE 1149 (JTAG) Compliance
    • 2.4.1 Statement of JTAG Compliance
    • 2.4.2 JTAG Compliance Mode
      • Table2-35. JTAG Compliance-Enable Inputs
    • 2.4.3 JTAG Implementation Specifics
      • Table2-36. Implemented JTAG Public Instructions
    • 2.4.4 Brief Overview of JTAG Instructions
  • 2.5 Signal Pin Lists
• 3. Physical MAC Multiplexer
  • Figure3-1. PMM Overview
  • 3.1 Ethernet Overview
    • Figure3-2. Ethernet Mode
    • 3.1.1 Ethernet Interface Timing Diagrams
      • Figure3-3. SMII Timing Diagram
      • Figure3-4. GMII Timing Diagram
      • Figure3-5. TBI Timing Diagram
      • Figure3-6. GMII POS Mode Timing Diagram
    • 3.1.2 Ethernet Counters
      • Table3-1. Ingress Ethernet Counters
      • Table3-2. Egress Ethernet Counters
    • 3.1.3 Ethernet Support
      • Table3-3. Ethernet Support
  • 3.2 POS Overview
    • Table3-4. DMU and Framer Configurations
    • Figure3-7. OC-3c / OC-12 / OC-12c Configuration
    • Figure3-8. OC-48 Configuration
    • Figure3-9. OC-48c Configuration
    • 3.2.1 POS Timing Diagrams
      • Figure3-10. Receive POS8 Interface Timing for 8-bit Data Bus (OC-3c)
      • Figure3-11. Transmit POS8 Interface Timing for 8-bit Data Bus (OC-3c)
      • Figure3-12. Receive POS8 Interface Timing for 8-bit Data Bus (OC-12c)
      • Figure3-13. Transmit POS8 Interface Timing for 8-bit Data Bus (OC-12c)
      • Figure3-14. Receive POS32 Interface Timing for 32-bit Data Bus (OC-48c)
      • Figure3-15. Transmit POS32 Interface Timing for 32-bit Data Bus (OC-48c)
    • 3.2.2 POS Counters
      • Table3-5. Receive Counter RAM Addresses for Ingress POS MAC
      • Table3-6. Transmit Counter RAM Addresses for Egress POS MAC
    • 3.2.3 POS Support
      • Table3-7. POS Support
• 4. Ingress Enqueuer / Dequeuer / Scheduler
  • 4.1 Overview
  • 4.2 Operation
    • Figure4-1. Logical Organization of Ingress EDS Data Flow Management
    • 4.2.1 Operational Details
      • Figure4-2. SOF Ring Structure
      • Figure4-3. Ingress EDS Logical Structure
  • 4.3 Ingress Flow Control
    • 4.3.1 Flow Control Hardware Facilities
      • Table4-1. Flow Control Hardware Facilities
    • 4.3.2 Hardware Function
      • 4.3.2.1 Exponentially Weighted Moving Average (EWMA)
      • 4.3.2.2 Flow Control Hardware Actions
• 5. Switch Interface
  • Figure5-1. Switch Interface Functional Blocks
  • 5.1 Ingress Switch Data Mover
    • 5.1.1 Cell Header
      • Figure5-2. Cell Header Format
      • Figure5-3. Cell Header Format - 32-Blade Mode
      • Table5-1. Cell Header Fields
    • 5.1.2 Frame Header
      • Figure5-4. Frame Header Format
      • Figure5-5. Frame Header Blade32 Format of Bytes 3-5
      • Table5-2. Frame Header Fields
  • 5.2 Ingress Switch Cell Interface
    • 5.2.1 Idle Cell Format
      • Table5-3. Idle Cell Format Transmitted to the Switch Interface
      • 5.2.1.1 CRC Bytes: Word 15
        • Figure5-6. CRC Calculation Example
      • 5.2.1.2 I-SCI Transmit Header for the Idle Cell
    • 5.2.2 Switch Data Cell Format - Ingress and Egress
      • Table5-4. Switch Data Cell Format
  • 5.3 Data-Aligned Synchronous Link Interface
  • 5.4 Egress Switch Cell Interface
    • 5.4.1 Master and Multicast Grant Reporting
    • 5.4.2 Output Queue Grant Reporting
      • 5.4.2.1 OQG Reporting in External Wrap Mode
        • Figure5-7. External Wrap Mode (Two NP4GS3 interconnected)
        • Figure5-8. External Wrap Mode (single NP4GS3 configuration)
    • 5.4.3 Switch Fabric to Network Processor Egress Idle Cell
      • Table5-5. Receive Cell Header Byte H0 for an Idle Cell
      • Table5-6. Idle Cell Format Received from the Switch Interface - 16-blade Mode
      • Table5-7. Idle Cell Format Received from the Switch Interface - 32-blade Mode
      • Table5-8. Idle Cell Format Received from the Switch Interface - 64-blade Mode
    • 5.4.4 Receive Header Formats for Sync Cells
  • 5.5 Egress Switch Data Mover
  • 5.6 IBM Packet Routing Switch PRS28.4G Configuration Notes
• 6. Egress Enqueuer / Dequeuer / Scheduler
  • 6.1 Functional Blocks
    • Figure6-1. Egress EDS Functional Blocks
  • 6.2 Operation
    • Figure6-2. Cell Formats and Storage in the Egress DS
    • Figure6-3. TPQ, FCB, and Egress Frame Example
  • 6.3 Egress Flow Control
    • 6.3.1 Flow Control Hardware Facilities
      • Table6-1. Flow Control Hardware Facilities
    • 6.3.2 Remote Egress Status Bus
      • 6.3.2.1 Bus Sequence and Timing
        • Figure6-4. RES Bus Timing
      • 6.3.2.2 Configuration
        • Figure6-5. Hub-based RES Bus configuration to support more than two NP4GS3s
    • 6.3.3 Hardware Function
      • Figure6-6. RES Bus Configuration Using External Transceivers
      • 6.3.3.1 Exponentially Weighted Moving Average
      • 6.3.3.2 Flow Control Hardware Actions
  • 6.4 The Egress Scheduler
    • Table6-2. Flow Queue Parameters
    • Table6-3. Valid Combinations of Scheduler Parameters
    • Figure6-7. The Egress Scheduler
    • 6.4.1 Egress Scheduler Components
      • 6.4.1.1 Scheduling Calendars
      • 6.4.1.2 Flow Queues
      • 6.4.1.3 Target Port Queues
    • 6.4.2 Configuring Flow Queues
      • Table6-4. Configure a Flow QCB
      • 6.4.2.1 Additional Configuration Notes
    • 6.4.3 Scheduler Accuracy and Capacities
• 7. Embedded Processor Complex
  • 7.1 Overview
    • Figure7-1. Embedded Processor Complex Block Diagram
    • 7.1.1 Thread Types
  • 7.2 Dyadic Protocol Processor Unit (DPPU)
    • Figure7-2. Dyadic Protocol Processor Unit Functional Blocks
    • 7.2.1 Core Language Processor (CLP)
      • Figure7-3. Core Language Processor
      • 7.2.1.1 Core Language Processor Address Map
        • Table7-1. Core Language Processor Address Map
    • 7.2.2 CLP Opcode Formats
    • 7.2.3 DPPU Coprocessors
    • 7.2.4 Shared Memory Pool
      • Table7-2. Shared Memory Pool
  • 7.3 CLP Opcode Formats
    • 7.3.1 Control Opcodes
      • Table7-3. Condition Codes (Cond Field)
      • 7.3.1.1 Nop Opcode
      • 7.3.1.2 Exit Opcode
      • 7.3.1.3 Test and Branch Opcode
      • 7.3.1.4 Branch and Link Opcode
      • 7.3.1.5 Return Opcode
      • 7.3.1.6 Branch Register Opcode
      • 7.3.1.7 Branch PC Relative Opcode
      • 7.3.1.8 Branch Reg+Off Opcode
    • 7.3.2 Data Movement Opcodes
      • Figure7-4. ot5 Field Definition: Loading Halfword/Word GPRs from a Halfword/Word Array
      • Figure7-5. ot5 Field Definition: Loading GPR Byte From Array Byte
      • Figure7-6. ot5 Field Definition: Loading GPR Halfword/Word from Array Byte
      • Figure7-7. ot5 FIeld Definition: Store GPR Byte/Halfword/Word to Array Byte/Halfword/Word
      • 7.3.2.1 Memory Indirect Opcode
      • 7.3.2.2 Memory Address Indirect Opcode
      • 7.3.2.3 Memory Direct Opcode
      • 7.3.2.4 Scalar Access Opcode
      • 7.3.2.5 Scalar Immediate Opcode
      • 7.3.2.6 Transfer Quadword Opcode
      • 7.3.2.7 Zero Array Opcode
    • 7.3.3 Coprocessor Execution Opcodes
      • 7.3.3.1 Execute Direct Opcode
      • 7.3.3.2 Execute Indirect Opcode
      • 7.3.3.3 Execute Direct Conditional Opcode
      • 7.3.3.4 Execute Indirect Conditional Opcode
      • 7.3.3.5 Wait Opcode
      • 7.3.3.6 Wait and Branch Opcode
    • 7.3.4 ALU Opcodes
      • 7.3.4.1 Arithmetic Immediate Opcode
        • Table7-4. AluOp Field Definition
        • Figure7-8. ot3i Field Definition
      • 7.3.4.2 Logical Immediate Opcode
        • Table7-5. Lop Field Definition
      • 7.3.4.3 Compare Immediate Opcode
        • Figure7-9. ot2i Field Definition: Compare Halfword/Word Immediate
      • 7.3.4.4 Load Immediate Opcode
        • Figure7-10. ot4i Field Definition Load Immediate Halfword/Word
        • Figure7-11. ot4i Field Definition: Load Immediate Byte
      • 7.3.4.5 Arithmetic Register Opcode
        • Table7-6. Arithmetic Opcode Functions
        • Figure7-12. ot3r Field Definition
      • 7.3.4.6 Count Leading Zeros Opcode
  • 7.4 DPPU Coprocessors
    • Table7-7. Coprocessor Instruction Format
    • 7.4.1 Tree Search Engine Coprocessor
    • 7.4.2 Data Store Coprocessor
      • 7.4.2.1 Data Store Coprocessor Address Map
        • Table7-8. Data Store Coprocessor Address Map
        • Table7-9. Ingress DataPool Byte Address Definitions
        • Figure7-13. A Frame in the Ingress Data Store
        • Figure7-14. Frame in the Egress Data Store
        • Table7-10. Egress Frames DataPool Quadword Addresses
        • Table7-11. DataPool Byte Addressing with Cell Header Skip
        • Table7-12. Number of Frame-bytes in the DataPool
      • 7.4.2.2 Data Store Coprocessor Commands
        • Table7-13. WREDS Input
        • Table7-14. WREDS Output
        • Table7-15. RDEDS Input
        • Table7-16. RDEDS Output
        • Table7-17. WRIDS Input
        • Table7-18. WRIDS Output
        • Table7-19. RDIDS Input
        • Table7-20. RDIDS Output
        • Table7-21. RDMOREE Input
        • Table7-22. RDMOREE Output
        • Table7-23. RDMOREI Input
        • Table7-24. RDMOREI Output
        • Table7-25. LEASETWIN Output
        • Table7-26. EDIRTY Inputs
        • Table7-27. EDIRTY Output
        • Table7-28. IDIRTY Inputs
        • Table7-29. IDIRTY Output
    • 7.4.3 Control Access Bus (CAB) Coprocessor
      • 7.4.3.1 CAB Coprocessor Address Map
        • Table7-30. CAB Coprocessor Address Map
      • 7.4.3.2 CAB Access to NP4GS3 Structures
        • Table7-31. CAB Address Field Definitions
        • Table7-32. CAB Address, Functional Island Encoding
      • 7.4.3.3 CAB Coprocessor Commands
        • Table7-33. CABARB Input
        • Table7-34. CABACCESS Input
        • Table7-35. CABACCESS Output
    • 7.4.4 Enqueue Coprocessor
      • 7.4.4.1 Enqueue Coprocessor Address Map
        • Table7-36. Enqueue Coprocessor Address Map
        • Figure7-15. Ingress FCBPage Format
        • Table7-37. Ingress FCBPage Description
        • Figure7-16. Egress FCBPage Format (NP4GS3B (R2.0))
        • Figure7-17. Egress FCBPage Format (NP4GS3C (R3.x))
        • Table7-38. Egress FCBPage Description
      • 7.4.4.2 Enqueue Coprocessor Commands
        • Table7-39. ENQE Target Queues
        • Table7-40. Egress Target Queue Selection Coding
        • Table7-41. Egress Target Queue Parameters
        • Table7-42. Type Field for Discard Queue
        • Table7-43. ENQE Command Input
        • Table7-44. Egress Queue Class Definitions
        • Table7-45. ENQI Target Queues
        • Table7-46. Ingress Target Queue Selection Coding
        • Table7-47. Ingress Target Queue FCBPage Parameters
        • Table7-48. ENQI Command Input
        • Table7-49. Ingress-Queue Class Definition
        • Table7-50. ENQCLR Command Input
        • Table7-51. ENQCLR Output
        • Table7-52. RELEASE_LABEL Output
    • 7.4.5 Checksum Coprocessor
      • 7.4.5.1 Checksum Coprocessor Address Map
        • Table7-53. Checksum Coprocessor Address Map
      • 7.4.5.2 Checksum Coprocessor Commands
        • Table7-54. GENGEN/GENGENX Command Inputs
        • Table7-55. GENGEN/GENGENX/GENIP/GENIPX Command Outputs
        • Table7-56. GENIP/GENIPX Command Inputs
        • Table7-57. CHKGEN/CHKGENX Command Inputs
        • Table7-58. CHKGEN/CHKGENX/CHKIP/CHKIPX Command Outputs
        • Table7-59. CHKIP/CHKIPX Command Inputs
    • 7.4.6 String Copy Coprocessor
      • 7.4.6.1 String Copy Coprocessor Address Map
        • Table7-60. String Copy Coprocessor Address Map
      • 7.4.6.2 String Copy Coprocessor Commands
        • Table7-61. StrCopy Command Input
        • Table7-62. StrCopy Command Output
    • 7.4.7 Policy Coprocessor
      • 7.4.7.1 Policy Coprocessor Address Map
        • Table7-63. Policy Coprocessor Address Map
      • 7.4.7.2 Policy Coprocessor Commands
        • Table7-64. PolAccess Input
        • Table7-65. PolAccess Output
    • 7.4.8 Counter Coprocessor
      • 7.4.8.1 Counter Coprocessor Address Map
        • Table7-66. Counter Coprocessor Address Map
      • 7.4.8.2 Counter Coprocessor Commands
        • Table7-67. Ctrinc Input
        • Table7-68. CtrRInc Input (NP4GS3C (R3.x))
        • Table7-69. CtrAdd Input
        • Table7-70. CtrRAdd Input (NP4GS3C (R3.x))
        • Table7-71. CtrRd/CtrRdClr Input
        • Table7-72. CtrRd/CtrRdClr Output
        • Table7-73. CtrWr15_0/CtrWr31_16 Input
    • 7.4.9 Coprocessor Response Bus
      • 7.4.9.1 Coprocessor Response Bus Address Map
        • Table7-74. Coprocessor Response Bus Coprocessor Address Map
      • 7.4.9.2 Coprocessor Response Bus Commands
        • Table7-75. Coprocessor Response Bus Coprocessor Command Summary
        • Table7-76. CrbSetBusy Output
      • 7.4.9.3 14-bit Coprocessor Response Bus
        • Table7-77. 14-bit Response Bus Bit and Cycle Definition
    • 7.4.10 Semaphore Coprocessor
      • 7.4.10.1 Semaphore Coprocessor Commands
        • Table7-78. Semaphore Lock Input
        • Table7-79. Semaphore Unlock Input
        • Table7-80. Reservation Release Input
      • 7.4.10.2 Error Conditions
      • 7.4.10.3 Software Use Models
  • 7.5 Interrupts and Timers
    • 7.5.1 Interrupts
      • 7.5.1.1 Interrupt Vector Registers
      • 7.5.1.2 Interrupt Mask Registers
      • 7.5.1.3 Interrupt Target Registers
      • 7.5.1.4 Software Interrupt Registers
    • 7.5.2 Timers
      • 7.5.2.1 Timer Interrupt Counters
  • 7.6 Dispatch Unit
    • Figure7-18. Dispatch Unit
    • Table7-81. Priority Assignments for the Dispatch Unit Queue Arbiter
    • 7.6.1 Port Configuration Memory
      • 7.6.1.1 Port Configuration Memory Index Definition
        • Table7-82. Port Configuration Memory Index
        • Table7-83. Relationship Between SP Field, Queue, and Port Configuration Memory Index
    • 7.6.2 Port Configuration Memory Contents Definition
      • Table7-84. Port Configuration Memory Content
    • 7.6.3 Completion Unit
  • 7.7 Hardware Classifier
    • 7.7.1 Ingress Classification
      • 7.7.1.1 Ingress Classification Input
        • Table7-85. Protocol Identifiers
      • 7.7.1.2 Ingress Classification Output
        • Table7-86. HCCIA Table
        • Table7-87. Protocol Identifiers for Frame Encapsulation Types
        • Table7-88. General Purpose Register Bit Definitions for Ingress Classification Flags
        • Table7-89. Flow Control Information Values
    • 7.7.2 Egress Classification
      • 7.7.2.1 Egress Classification Input
      • 7.7.2.2 Egress Classification Output
        • Table7-90. HCCIA Index Definition
        • Table7-91. General Purpose Register 1 Bit Definitions for Egress Classification Flags
    • 7.7.3 Completion Unit Label Generation
      • Table7-92. Completion Unit Label
  • 7.8 Policy Manager
    • Figure7-19. Split between Picocode and Hardware for the Policy Manager
    • Table7-93. PolCB Field Definitions
  • 7.9 Counter Manager
    • Figure7-20. Counter Manager Block Diagram
    • Table7-94. Counter Manager Components
    • Table7-95. Counter Types
    • Table7-96. Counter Actions
    • 7.9.1 Counter Manager Usage
      • Table7-97. Counter Definition Entry Format
      • Figure7-21. Counter Definition Entry
      • Figure7-22. Counter Blocks and Sets
      • Table7-98. Counter Manager Passed Parameters
      • Table7-99. Counter Manager use of Address Bits
  • 7.10 Semaphore Manager
• 8. Tree Search Engine
  • 8.1 Overview
    • 8.1.1 Addressing Control Store (CS)
      • Table8-1. Control Store Address Mapping for TSE References
      • Table8-2. CS Address Map and Use
    • 8.1.2 D6 Control Store.
    • 8.1.3 Logical Memory Views of D6
      • Table8-3. PLB and D6 Control Store Addressing
    • 8.1.4 Control Store Use Restrictions
    • 8.1.5 Object Shapes
      • Table8-4. DTEntry, PSCB, and Leaf Shaping
      • Figure8-1. Example Shaping Dimensions
      • Table8-5. Height, Width, and Offset Restrictions for TSE Objects
    • 8.1.6 Illegal Memory Access
    • 8.1.7 Memory Range Checking (Address Bounds Check)
  • 8.2 Trees and Tree Searches
    • Table8-6. FM and LPM Tree Fixed Leaf Formats
    • Table8-7. SMT Tree Fixed Leaf Formats
    • Table8-8. Search Input Parameters
    • 8.2.1 Input Key and Color Register for FM and LPM Trees
    • 8.2.2 Input Key and Color Register for SMT Trees
    • 8.2.3 Direct Table
      • Figure8-2. Effects of Using a Direct Table
      • 8.2.3.1 Pattern Search Control Blocks (PSCB)
      • 8.2.3.2 Leaves and Compare-at-End Operation
      • 8.2.3.3 Cascade/Cache
      • 8.2.3.4 Cache Flag and NrPSCBs Registers
        • Table8-9. Cache Status Registers
      • 8.2.3.5 Cache Management
      • 8.2.3.6 Search Output
        • Table8-10. Search Output Parameters
    • 8.2.4 Tree Search Algorithms
      • 8.2.4.1 FM Trees
        • Table8-11. DTEntry and PSCBLine Formats
      • 8.2.4.2 LPM Trees
        • Table8-12. LPM DTEntry and PSCBLine Formats
      • 8.2.4.3 LPM PSCB Structure in Memory
        • Figure8-3. Example of LPM PSCB Detail Layout in Memory
      • 8.2.4.4 LPM Compact PSCB Support
      • 8.2.4.5 LPM Trees with Multibit Compare
        • Figure8-4. Example of LPM PSCB and Compact LPM PSCB Layout in Memory
        • Figure8-5. LPM Multibit NBT PSCB Detail Layout
        • Figure8-6. Example Multibit LPM Tree Layout
      • 8.2.4.6 SMT Trees
        • Table8-13. NLASMT Field Format
      • 8.2.4.7 Compare-at-End Operation
        • Figure8-7. Example Input Key and Leaf Pattern Fields
        • Table8-14. CompDefTable Entry Format
      • 8.2.4.8 Ropes
        • Figure8-8. Rope Structure
        • Table8-15. LUDefTable Rope Parameters
      • 8.2.4.9 Aging
        • Table8-16. NLARope Field Format
    • 8.2.5 Tree Configuration and Initialization
      • 8.2.5.1 The LUDefTable
        • Table8-17. LUDefTable Entry Definitions
      • 8.2.5.2 TSE Free Lists (TSE_FL)
        • Table8-18. Free List Entry Definition
    • 8.2.6 TSE Registers and Register Map
      • Table8-19. TSE Scalar Registers for GTH Only
      • Table8-20. TSE Array Registers for All GxH
      • Table8-21. TSE Registers for GTH (Tree Management)
      • Table8-22. TSE Scalar Registers for GDH and GTH
      • Table8-23. PSCB Register Format
      • Table8-24. TSE GTH Indirect Registers
      • Table8-25. Address Map for PSCB0-2 Registers in GTH
    • 8.2.7 TSE Instructions
      • Table8-26. General TSE Instructions
      • Figure8-9. General Layout of TSE Fields in Shared Memory Pool
      • 8.2.7.1 FM Tree Search (TS_FM)
        • Table8-27. FM Tree Search Input Operands
        • Table8-28. FM Tree Search Results (TSR) Output
      • 8.2.7.2 LPM Tree Search (TS_LPM)
        • Table8-29. LPM Tree Search Input Operands
        • Table8-30. LPM Tree Search Results Output
      • 8.2.7.3 SMT Tree Search (TS_SMT)
        • Table8-31. SMT Tree Search Input Operands
        • Table8-32. SMT Tree Search Results Output
      • 8.2.7.4 Memory Read (MRD)
        • Table8-33. Memory Read Input Operands
        • Table8-34. Memory Read Output Results
      • 8.2.7.5 Memory Write (MWR)
        • Table8-35. Memory Write Input Operands
      • 8.2.7.6 Hash Key (HK)
        • Table8-36. Hash Key Input Operands
        • Table8-37. Hash Key Output Results
      • 8.2.7.7 Read LUDefTable (RDLUDEF)
        • Figure8-10. General Layout of TSE RDLUDEF in Shared Memory Pool
        • Table8-38. RDLUDEF Input Operands
        • Table8-39. RDLUDEF Output Results
      • 8.2.7.8 Compare-at-End (COMPEND)
        • Table8-40. COMPEND Input Operands
        • Table8-41. COMPEND Output Results
      • 8.2.7.9 DistinguishPosition for Fast Table Update (DISTPOS_GDH)
        • Figure8-11. Shared Memory Pool with DISTPOS_GDH Command Subfields
        • Table8-42. DISTPOS_GDH Input Operands
        • Table8-43. DISTPOS_GDH Output Results
      • 8.2.7.10 Read PSCB for Fast Table Update (RDPSCB_GDH)
        • Figure8-12. Shared Memory Pool with PSCB Subfields
        • Table8-44. RDPSCB_GDH Input Operands
        • Table8-45. RDPSCB_GDH Output Results
      • 8.2.7.11 Write PSCB for Fast Table Update (WRPSCB_GDH)
        • Table8-46. WRPSCB_GDH Input Operands
        • Table8-47. WRPSCB_GDH Output Results
      • 8.2.7.12 SetPatBit_GDH
        • Table8-48. SetPatBit_GDH Input Operands
        • Table8-49. SetPatBit_GDH Output Results
    • 8.2.8 GTH Hardware Assist Instructions
      • Table8-50. General GTH Instructions
      • 8.2.8.1 Hash Key GTH (HK_GTH)
        • Table8-51. Hash Key GTH Input Operands
        • Table8-52. Hash Key GTH Output Results
      • 8.2.8.2 Read LUDefTable GTH (RDLUDEF GTH)
        • Table8-53. RDLUDEF_GTH Input Operands
        • Table8-54. RDLUDEF_GTH Output Results
      • 8.2.8.3 Tree Search Enqueue Free List (TSENQFL)
        • Table8-55. TSENQFL Input Operands
        • Table8-56. TSENQFL Output Results
      • 8.2.8.4 Tree Search Dequeue Free List (TSDQFL)
        • Table8-57. TSDQFL Input Operands
        • Table8-58. TSDQFL Output Results
      • 8.2.8.5 Read Current Leaf from Rope (RCLR)
        • Table8-59. RCLR Input Operands
        • Table8-60. RCLR Output Results
      • 8.2.8.6 Advance Rope with Optional Delete Leaf (ARDL)
        • Table8-61. ARDL Input Operands
        • Table8-62. ARDL Output Results
      • 8.2.8.7 Tree Leaf Insert Rope (TLIR)
        • Table8-63. TLIR Input Operands
        • Table8-64. TLIR Output Results
      • 8.2.8.8 Clear PSCB (CLRPSCB)
        • Table8-65. CLRPSCB Input Operands
        • Table8-66. CLRPSCB Output Results
      • 8.2.8.9 Read PSCB (RDPSCB)
        • Table8-67. RDPSCB Input Operands
        • Table8-68. RDPSCB Output Results
      • 8.2.8.10 Write PSCB (WRPSCB)
        • Table8-69. WRPSCB Input Operands 
      • 8.2.8.11 Push PSCB (PUSHPSCB)
        • Table8-70. PUSHPSCB Input Operands
        • Table8-71. PUSHPSCB Output Results
      • 8.2.8.12 Distinguish (DISTPOS)
        • Table8-72. DISTPOS Input Operands
        • Table8-73. DISTPOS Output Results
      • 8.2.8.13 TSR0 Pattern (TSR0PAT)
        • Table8-74. TSR0PAT Input Operands
        • Table8-75. TSR0PAT Output Results
      • 8.2.8.14 Pattern 2DTA (PAT2DTA)
        • Table8-76. PAT2DTA Input Operands
        • Table8-77. PAT2DTA Output Results
    • 8.2.9 Hash Functions
      • Table8-78. General Hash Functions
      • Figure8-13. No-Hash Function
      • Figure8-14. 192-Bit IP Hash Function
      • Figure8-15. MAC Hash Function
      • Figure8-16. Network Dispatcher Hash Function
      • Figure8-17. 48-Bit MAC Hash Function
      • Figure8-18. 60-Bit MAC Hash Function
      • Figure8-19. 8-bit Hash Function
      • Figure8-20. 12-bit Hash Function
      • Figure8-21. 16 bit Hash Function
• 9. Serial / Parallel Manager Interface
  • 9.1 SPM Interface Components
    • Figure9-1. SPM Interface Block Diagram
  • 9.2 SPM Interface Data Flow
    • Figure9-2. EPC Boot Image in External EEPROM
  • 9.3 SPM Interface Protocol
    • Figure9-3. SPM Bit Timing
    • Figure9-4. SPM Interface Write Protocol
    • Figure9-5. SPM Interface Read Protocol
  • 9.4 SPM CAB Address Space
    • 9.4.1 Byte Access Space
    • 9.4.2 Word Access Space
    • 9.4.3 EEPROM Access Space
      • Table9-1. Field Definitions for CAB Addresses
      • 9.4.3.1 EEPROM Single-Byte Access
      • 9.4.3.2 EEPROM 2-Byte Access
      • 9.4.3.3 EEPROM 3-Byte Access
      • 9.4.3.4 EEPROM 4-Byte Access
• 10. Embedded PowerPC� Subsystem
  • 10.1 Description
    • Figure10-1. PowerPC Subsystem Block Diagram
  • 10.2 Processor Local Bus and Device Control Register Buses
    • 10.2.1 Processor Local Bus (PLB)
      • Table10-1. PLB Master Connections
    • 10.2.2 Device Control Register (DCR) Bus
      • Table10-2. Device Control Registers
  • 10.3 PLB Address Map
    • Table10-3. Address Map for CAB Interface Macro
    • Table10-4. PLB Address Map for Mailbox and DRAM Interface Macro
  • 10.4 CAB Address Map
    • Table10-5. CAB Address Map for Mailbox and DRAM Interface Macro
  • 10.5 Universal Interrupt Controller (UIC) Macro
    • Table10-6. UIC Interrupt Assignments
  • 10.6 PCI/PLB Bridge Macro
    • Table10-7. NP4GS3 PCI Device Configuration Header Values
    • Table10-8. PLB Address Map for PCI/PLB Macro
    • Table10-9. PCI/PLB Bridge Macro Configuration Registers
  • 10.7 CAB Interface Macro
    • Figure10-2. Polled Access Flow Diagram
    • 10.7.1 PowerPC CAB Address (PwrPC_CAB_Addr) Register
    • 10.7.2 PowerPC CAB Data (PwrPC_CAB_Data) Register
    • 10.7.3 PowerPC CAB Control (PwrPC_CAB_Cntl) Register
    • 10.7.4 PowerPC CAB Status (PwrPC_CAB_Status) Register
    • 10.7.5 PowerPC CAB Mask (PwrPC_CAB_Mask) Register
    • 10.7.6 PowerPC CAB Write Under Mask Data (PwrPC_CAB_WUM_Data)
    • 10.7.7 PCI Host CAB Address (Host_CAB_Addr) Register
    • 10.7.8 PCI Host CAB Data (Host_CAB_Data) Register
    • 10.7.9 PCI Host CAB Control (Host_CAB_Cntl) Register
    • 10.7.10 PCI Host CAB Status (Host_CAB_Status) Register
    • 10.7.11 PCI Host CAB Mask (Host_CAB_Mask) Register
    • 10.7.12 PCI Host CAB Write Under Mask Data (Host_CAB_WUM_Data) Register
  • 10.8 Mailbox Communications and DRAM Interface Macro
    • 10.8.1 Mailbox Communications Between PCI Host and PowerPC Subsystem
    • 10.8.2 PCI Interrupt Status (PCI_Interr_Status) Register
    • 10.8.3 PCI Interrupt Enable (PCI_Interr_Ena) Register
    • 10.8.4 PowerPC Subsystem to PCI Host Message Resource (P2H_Msg_Resource) Register
    • 10.8.5 PowerPC Subsystem to Host Message Address (P2H_Msg_Addr) Register
    • 10.8.6 PowerPC Subsystem to Host Doorbell (P2H_Doorbell) Register
    • 10.8.7 Host to PowerPC Subsystem Message Address (H2P_Msg_Addr) Register
    • 10.8.8 Host to PowerPC Subsystem Doorbell (H2P_Doorbell) Register
    • 10.8.9 Mailbox Communications Between PowerPC Subsystem and EPC
    • 10.8.10 EPC to PowerPC Subsystem Resource (E2P_Msg_Resource) Register
    • 10.8.11 EPC to PowerPC Subsystem Message Address (E2P_Msg_Addr) Register
    • 10.8.12 EPC to PowerPC Subsystem Doorbell (E2P_Doorbell) Register
    • 10.8.13 EPC Interrupt Vector Register
    • 10.8.14 EPC Interrupt Mask Register
    • 10.8.15 PowerPC Subsystem to EPC Message Address (P2E_Msg_Addr) Register
    • 10.8.16 PowerPC Subsystem to EPC Doorbell (P2E_Doorbell) Register
    • 10.8.17 Mailbox Communications Between PCI Host and EPC
    • 10.8.18 EPC to PCI Host Resource (E2H_Msg_Resource) Register
    • 10.8.19 EPC to PCI Host Message Address (E2H_Msg_Addr) Register
    • 10.8.20 EPC to PCI Host Doorbell (E2H_Doorbell) Register
    • 10.8.21 PCI Host to EPC Message Address (H2E_Msg_Addr) Register
    • 10.8.22 PCI Host to EPC Doorbell (H2E_Doorbell) Register
    • 10.8.23 Message Status (Msg_Status) Register
    • 10.8.24 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst)
    • 10.8.25 PowerPC Machine Check (PwrPC_Mach_Chk) Register
    • 10.8.26 Parity Error Status and Reporting
    • 10.8.27 Slave Error Address Register (SEAR)
    • 10.8.28 Slave Error Status Register (SESR)
    • 10.8.29 Parity Error Counter (Perr_Count) Register
  • 10.9 System Start-Up and Initialization
    • 10.9.1 NP4GS3 Resets
      • Table10-10. Reset Domains
    • 10.9.2 Systems Initialized by External PCI Host Processors
    • 10.9.3 Systems with PCI Host Processors and Initialized by PowerPC Subsystem
    • 10.9.4 Systems Without PCI Host Processors and Initialized by PowerPC Subsystem
    • 10.9.5 Systems Without PCI Host or Delayed PCI Configuration and Initialized by EPC
• 11. Reset and Initialization
  • 11.1 Overview
    • Table11-1. Reset and Initialization Sequence
    • Figure11-1. System Environments
  • 11.2 Step 1: Set I/Os
    • Table11-2. Set I/Os Checklist
  • 11.3 Step 2: Reset the NP4GS3
  • 11.4 Step 3: Boot
    • 11.4.1 Boot the Embedded Processor Complex (EPC)
    • 11.4.2 Boot the PowerPC Processor
    • 11.4.3 Boot Summary
  • 11.5 Step 4: Setup 1
    • Table11-3. Setup 1 Checklist
  • 11.6 Step 5: Diagnostics 1
    • Table11-4. Diagnostics 1 Checklist
  • 11.7 Step 6: Setup 2
    • Table11-5. Setup 2 Checklist
  • 11.8 Step 7: Hardware Initialization
    • Table11-6. Hardware Initialization Checklist
  • 11.9 Step 8: Diagnostics 2
    • Table11-7. Diagnostic 2 Checklist
  • 11.10 Step 9: Operational
  • 11.11 Step 10: Configure
    • Table11-8. Configure Checklist
  • 11.12 Step 11: Initialization Complete
• 12. Debug Facilities
  • 12.1 Debugging Picoprocessors
    • 12.1.1 Single Step
    • 12.1.2 Break Points
    • 12.1.3 CAB Accessible Registers
  • 12.2 RISCWatch
• 13. Configuration
  • 13.1 Memory Configuration
    • Figure13-1. NP4GS3 Memory Subsystems
    • 13.1.1 Memory Configuration Register (Memory_Config)
    • 13.1.2 DRAM Parameter Register (DRAM_Parm)
    • 13.1.3 Delay Calibration Registers (NP4GS3C (R3.x))
  • 13.2 Master Grant Mode Register (MG_Mode)
  • 13.3 TB Mode Register (TB_Mode)
    • 13.3.1 Toggle Mode
      • 13.3.1.1 DSU information
      • 13.3.1.2 ENQE Command and Qclass 5 or 6
  • 13.4 Egress Reassembly Sequence Check Register (E_Reassembly_Seq_Ck)
  • 13.5 Aborted Frame Reassembly Action Control Register (AFRAC)
  • 13.6 Packing Registers
    • 13.6.1 Packing Control Register (Pack_Ctrl)
    • 13.6.2 Packing Delay Register (Pack_Dly) (NP4GS3B (R2.0))
  • 13.7 Initialization Control Registers
    • 13.7.1 Initialization Register (Init)
    • 13.7.2 Initialization Done Register (Init_Done)
  • 13.8 NP4GS3 Ready Register (NPR_Ready)
  • 13.9 Phase-Locked Loop Registers
    • 13.9.1 Phase-Locked Loop Fail Register (PLL_Lock_Fail)
  • 13.10 Software Controlled Reset Register (Soft_Reset)
  • 13.11 Ingress Free Queue Threshold Configuration
    • 13.11.1 BCB_FQ Threshold Registers
    • 13.11.2 BCB_FQ Threshold for Guided Traffic (BCB_FQ_Th_GT)
    • 13.11.3 BCB_FQ_Threshold_0 Register (BCB_FQ_TH_0)
    • 13.11.4 BCB_FQ_Threshold_1 Register (BCB_FQ_TH_1)
    • 13.11.5 BCB_FQ_Threshold_2 Register (BCB_FQ_Th_2)
  • 13.12 I-GDQ Threshold Register (I-GDQ_Th) (NP4GS3C (R3.x))
  • 13.13 Ingress Target DMU Data Storage Map Register (I_TDMU_DSU)
  • 13.14 Embedded Processor Complex Configuration
    • 13.14.1 PowerPC Core Reset Register (PowerPC_Reset)
    • 13.14.2 PowerPC Boot Redirection Instruction Registers (Boot_Redir_Inst)
    • 13.14.3 Watch Dog Reset Enable Register (WD_Reset_Ena)
    • 13.14.4 Boot Override Register (Boot_Override)
    • 13.14.5 Thread Enable Register (Thread_Enable)
    • 13.14.6 GFH Data Disable Register (GFH_Data_Dis)
    • 13.14.7 Ingress Maximum DCB Entries (I_Max_DCB)
    • 13.14.8 Egress Maximum DCB Entries (E_Max_DCB)
    • 13.14.9 My Target Blade Address Register (My_TB)
    • 13.14.10 Local Target Blade Vector Register (Local_TB_Vector)
    • 13.14.11 Local MCTarget Blade Vector Register (Local_MC_TB_Max)
    • 13.14.12 Ordered Semaphore Enable Register (Ordered_Sem_Ena)
    • 13.14.13 Enhanced Classification Enable Register (Enh_HWC_Ena) (NP4GS3C (R3.x))
  • 13.15 Flow Control Structures
    • 13.15.1 Ingress Flow Control Hardware Structures
      • 13.15.1.1 Ingress Transmit Probability Memory Register (I_Tx_Prob_Mem)
      • 13.15.1.2 Ingress pseudorandom Number Register (I_Rand_Num)
      • 13.15.1.3 Free Queue Thresholds Register (FQ_Th)
    • 13.15.2 Egress Flow Control Structures
      • 13.15.2.1 Egress Transmit Probability Memory (E_Tx_Prob_Mem) Register
      • 13.15.2.2 Egress pseudorandom Number (E_Rand_Num)
      • 13.15.2.3 P0 Twin Count Threshold (P0_Twin_Th)
      • 13.15.2.4 P1 Twin Count Threshold (P1_Twin_Th)
      • 13.15.2.5 Egress P0 Twin Count EWMA Threshold Register (E_P0_Twin_EWMA_Th)
      • 13.15.2.6 Egress P1 Twin Count EWMA Threshold Register (E_P1_Twin_EWMA_Th)
    • 13.15.3 Exponentially Weighted Moving Average Constant (K) Register (EWMA_K)
    • 13.15.4 Exponentially Weighted Moving Average Sample Period (T) Register (EWMA_T)
    • 13.15.5 Flow Control Force Discard Register (FC_Force_Discard) (NP4GS3B (R2.0))
    • 13.15.6 Remote Egress Status Bus Configuration Enables (RES_Data_Cnf)
  • 13.16 Target Port Data Storage Map (TP_DS_MAP) Register
  • 13.17 Egress SDM Stack Threshold Register (E_SDM_Stack_Th)
  • 13.18 Free Queue Extended Stack Maximum Size (FQ_ES_Max) Register
  • 13.19 Egress Free Queue Thresholds
    • 13.19.1 FQ_ES_Threshold_0 Register (FQ_ES_Th_0)
    • 13.19.2 FQ_ES_Threshold_1 Register (FQ_ES_Th_1)
    • 13.19.3 FQ_ES_Threshold_2 Register (FQ_ES_Th_2)
  • 13.20 Egress Frame Data Queue Thresholds (E_GRx_GBx_th) (NP4GS3C (R3.x))
  • 13.21 Discard Flow QCB Register (Discard_QCB)
  • 13.22 Bandwidth Allocation Register (BW_Alloc_Reg) (NP4GS3B (R2.0))
  • 13.23 Miscellaneous Controls Register (MISC_CNTRL) (NP4GS3C (R3.x))
  • 13.24 Frame Control Block FQ Size Register (FCB_FQ_Max)
  • 13.25 Data Mover Unit (DMU) Configuration Registers
  • 13.26 Frame Pad Configuration Register (DMU_Pad) (NP4GS3C (R3.x))
  • 13.27 Ethernet Jumbo Frame Size Register (EN_Jumbo_FS) (NP4GS3C (R3.x))
  • 13.28 QD Accuracy Register (QD_Acc)
  • 13.29 Packet Over SONET Control Register (POS_Ctrl)
    • 13.29.1 Initial CRC Value Determination
  • 13.30 Packet Over SONET Maximum Frame Size (POS_Max_FS)
  • 13.31 Ethernet Encapsulation Type Register for Control (E_Type_C)
  • 13.32 Ethernet Encapsulation Type Register for Data (E_Type_D)
  • 13.33 Source Address Array (SA_Array)
  • 13.34 Destination Address Array (DA_Array) (NP4GS3C (R3.x))
  • 13.35 DASL Initialization and Configuration
    • 13.35.1 DASL Configuration Register (DASL_Config)
      • 13.35.1.1 Dynamic Switch Interface Selection
    • 13.35.2 DASL Bypass and Wrap Register (DASL_Bypass_Wrap)
    • 13.35.3 DASL Start Register (DASL_Start)
  • 13.36 Programmable I/O Register (PIO_Reg)
• 14. Electrical and Thermal Specifications
  • Table14-1. Absolute Maximum Ratings
  • Table14-2. Input Capacitance (pF)
  • Table14-3. Operating Supply Voltages
  • Table14-4. Operating Supply Currents
  • Table14-5. Thermal Characteristics
  • 14.1 Driver Specifications
    • Table14-6. Definition of Terms
    • Table14-7. 1.8 V CMOS Driver DC Voltage Specifications
    • Table14-8. 1.8 V CMOS Driver Minimum DC Currents at Rated Voltage
    • Table14-9. 2.5 V CMOS Driver DC Voltage Specifications
    • Table14-10. 2.5 V CMOS Driver Minimum DC Currents at Rated Voltage
    • Table14-11. 3.3 V-Tolerant 2.5 V CMOS Driver DC Voltage Specifications
    • Table14-12. 3.3 V LVTTL Driver DC Voltage Specifications
    • Table14-13. 3.3 V LVTTL/5.0 V-Tolerant Driver DC Voltage Specifications
    • Table14-14. 3.3 V LVTTL Driver Minimum DC Currents at Rated Voltage
  • 14.2 Receiver Specifications
    • Table14-15. 1.8 V CMOS Receiver DC Voltage Specifications
    • Table14-16. 2.5 V CMOS Receiver DC Voltage Specifications
    • Table14-17. 3.3 V LVTTL Receiver DC Voltage Specifications
    • Table14-18. 3.3 V LVTTL / 5 V Tolerant Receiver DC Voltage Specifications
    • Table14-19. Receiver Maximum Input Leakage DC Current Input Specifications
    • Figure14-1. 3.3 V LVTTL / 5 V Tolerant BP33 and IP33 Receiver Input Current/Voltage Curve
  • 14.3 Other Driver and Receiver Specifications
    • Table14-20. LVDS Receiver DC Specifications
    • Table14-21. SSTL2 DC Specifications
    • 14.3.1 DASL Specifications
      • Table14-22. DASL Receiver DC SpecificationsIDASL_A
      • Table14-23. DASL Driver DC Specifications ODASL_A
• 15. Glossary of Terms and Abbreviations
• Revision Log
• Copyright and Disclaimer