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Электронный компонент: IC41C8512-60T

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IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
1
DR029-0A 09/28/2001
Document Title
512K x 8 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 28,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC41C8512
IC41LV8512
2
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1024 cycles /16 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR),
Hidden
Single power supply:
5V 10% (IC41C8512)
3.3V 10% (IC41LV8512)
Industrail Temperature Range -40
o
C to 85
o
C
DESCRIPTION
The
ICSI
IC41C8512 and IC41LV8512 is a 524,288 x 8-bit high-
performance CMOS Dynamic Random Access Memories. The
IC41C8512 offer an accelerated cycle access called EDO Page
Mode. EDO Page Mode allows 1024 random accesses within
a single row with access cycle time as short as 12 ns per 8-bit
word.
These features make the IC41C8512and IC41LV8512 ideally
suited for, digital signal processing, high-performance audio
systems, and peripheral applications.
The IC41C8512 is packaged in a 28-pin 400mil SOJ and 400mil
TSOP-2.
512K x 8 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter
-35
-50
-60
Unit
Max.
RAS
Access Time (t
RAC
)
35
50
60
ns
Max.
CAS
Access Time (t
CAC
)
10
14
15
ns
Max. Column Address Access Time (t
AA
)
18
25
30
ns
Min. EDO Page Mode Cycle Time (t
PC
)
12
20
25
ns
Min. Read/Write Cycle Time (t
RC
)
60
90
110
ns
PIN DESCRIPTIONS
A0-A9
Address Inputs
I/O0-7
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
PIN CONFIGURATION
28 Pin SOJ, TSOP
-
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
GND
IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
3
DR029-0A 09/28/2001
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
524,288 x 8
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O7
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C8512
IC41LV8512
4
Integrated Circuit Solution Inc.
DR029-0A 09/28/2001
TRUTH TABLE
Function
R A S
R A S
R A S
R A S
R A S
C A S
C A S
C A S
C A S
C A S
W E
W E
W E
W E
W E
O E
O E
O E
O E
O E Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read:
L
L
H
L
ROW/COL
D
OUT
Write: (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
EDO Page-Mode Read
1st Cycle:
L
H
L
H
L
ROW/COL
D
OUT
2nd Cycle:
L
H
L
H
L
NA/COL
D
OUT
Any Cycle:
L
L
H
H
L
NA/NA
D
OUT
EDO Page-Mode Write
1st Cycle:
L
H
L
L
X
ROW/COL
D
IN
2nd Cycle:
L
H
L
L
X
NA/COL
D
IN
EDO Page-Mode
1st Cycle:
L
H
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Read-Write
2nd Cycle:
L
H
L
H
L
L
H
NA/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
L
H
L
L
L
X
ROW/COL
D
IN
RAS
-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
IC41C8512
IC41LV8512
Integrated Circuit Solution Inc.
5
DR029-0A 09/28/2001
Functional Description
The IC41C8512 and IC41LV8512 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 10 address bits. These are entered
10 bits (A0-A9) at a time. The row address is latched by the
Row Address Strobe (
RAS
). The column address is latched
by the Column Address Strobe (
CAS
)
. RAS
is used to latch
the first ten bits and
CAS
is used to latch the latter nine bits.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs first.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0 through
A9) with
RAS
at least once every 16 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle's falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.