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IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
1
DR027-0A 09/05/2001
Document Title
1Mx4 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
September 5,2001
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC41C4100
IC41LV4100
2
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1024 cycles /16 ms
Refresh Mode:
RAS
-Only,
CAS
-before-
RAS
(CBR),
Hidden
Single power supply:
5V 10% (IC41C4100)
3.3V 10% (IC41LV4100)
Industrail Temperature Range -40
o
C to 85
o
C
DESCRIPTION
The
ICSI
IC41C4100 and IC41LV4100 is a 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access Memories.
The IC41C4100 offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1024 random accesses
within a single row with access cycle time as short as 12 ns per
4-bit word.
These features make the IC41C4100and IC41LV4100 ideally
suited for, digital signal processing, high-performance audio
systems, and peripheral applications.
The IC41C4100 is packaged in a 20-pin 300mil SOJ and 300mil
TSOP-2.
1M x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
KEY TIMING PARAMETERS
Parameter
-35
-50
-60
Unit
Max.
RAS
Access Time (t
RAC
)
35
50
60
ns
Max.
CAS
Access Time (t
CAC
)
10
14
15
ns
Max. Column Address Access Time (t
AA
)
18
25
30
ns
Min. EDO Page Mode Cycle Time (t
PC
)
12
20
25
ns
Min. Read/Write Cycle Time (t
RC
)
60
90
110
ns
PIN DESCRIPTIONS
A0-A9
Address Inputs
I/O0-3
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
PIN CONFIGURATION
20 (26) Pin SOJ, TSOP
-
2
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
I/O0
I/O1
WE
RAS
A9
A0
A1
A2
A3
VCC
GND
I/O3
I/O2
CAS
OE
A8
A7
A6
A5
A4
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
3
DR027-0A 09/05/2001
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
1,048,576 x 4
ROW DECODER
DATA I/O BUFFERS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O3
RAS
RAS
A0-A9
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
IC41C4100
IC41LV4100
4
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
TRUTH TABLE
Function
R A S
R A S
R A S
R A S
R A S
C A S
C A S
C A S
C A S
C A S
W E
W E
W E
W E
W E
O E
O E
O E
O E
O E Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read:
L
L
H
L
ROW/COL
D
OUT
Write: (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
EDO Page-Mode Read
1st Cycle:
L
H
L
H
L
ROW/COL
D
OUT
2nd Cycle:
L
H
L
H
L
NA/COL
D
OUT
Any Cycle:
L
L
H
H
L
NA/NA
D
OUT
EDO Page-Mode Write
1st Cycle:
L
H
L
L
X
ROW/COL
D
IN
2nd Cycle:
L
H
L
L
X
NA/COL
D
IN
EDO Page-Mode
1st Cycle:
L
H
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Read-Write
2nd Cycle:
L
H
L
H
L
L
H
NA/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
L
H
L
L
L
X
ROW/COL
D
IN
RAS
-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
5
DR027-0A 09/05/2001
Functional Description
The IC41C4100 and IC41LV4100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits. These are entered
10 bits (A0-A9) at a time. The row address is latched by the
Row Address Strobe (
RAS
). The column address is latched
by the Column Address Strobe (
CAS
)
.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE
,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE
, whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE
, whichever
occurs first.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0 through
A9) with
RAS
at least once every 16 ms. Any read, write,
read-modify-write or
RAS
-only cycle refreshes the ad-
dressed row.
2. Using a
CAS
-before-
RAS
refresh cycle.
CAS
-before-
RAS
refresh is activated by the falling edge of
RAS
,
while holding
CAS
LOW. In
CAS
-before-
RAS
refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS
-before-
RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle's falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
IC41C4100
IC41LV4100
6
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
CC
Supply Voltage
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
Industrial Operationg Temperature
40 to +85
C
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
5V
4.5
5.0
5.5
V
3.3V
3.0
3.3
3.6
V
IH
Input High Voltage
5V
2.4
--
V
CC
+ 1.0
V
3.3V
2.0
--
V
CC
+ 0.3
V
IL
Input Low Voltage
5V
1.0
--
0.8
V
3.3V
0.3
--
0.8
T
A
Commercial Ambient Temperature
0
--
70
C
Industrial Ambient Temperature
40
--
85
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A9
5
pF
C
IN
2
Input Capacitance:
RAS
,
CAS
,
WE
,
OE
7
pF
C
IO
Data Input/Output Capacitance: I/O0-I/O3
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz.
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
7
DR027-0A 09/05/2001
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
V
IN
Vcc
10
10
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
10
10
A
0V
V
OUT
Vcc
V
OH
Output High Voltage Level
I
OH
= 2.5 mA
2.4
--
V
V
OL
Output Low Voltage Level
I
OL
=+2.1mA
--
0.4
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
V
IH
Commerical
5V
--
2
mA
Industrial
5V
--
3
Commerical 3.3V
--
1
Industrial
3.3V
--
2
I
CC
2
Standby Current: CMOS
RAS
,
CAS
V
CC
0.2V
5V
--
1
mA
3.3V
--
0.5
I
CC
3
Operating Current:
RAS
,
CAS
,
-35
--
110
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-50
--
95
Average Power Supply Current
-60
--
85
I
CC
4
Operating Current:
RAS
= V
IL
,
CAS
,
-35
--
90
mA
EDO Page Mode
(2,3,4)
Cycling t
PC
= t
PC
(min.)
-50
--
80
Average Power Supply Current
-60
--
70
I
CC
5
Refresh Current:
RAS
Cycling,
CAS
V
IH
-35
--
110
mA
RAS
-Only
(2,3)
t
RC
= t
RC
(min.)
-50
--
95
Average Power Supply Current
-60
--
85
I
CC
6
Refresh Current:
RAS
,
CAS
Cycling
-35
--
110
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-50
--
95
Average Power Supply Current
-60
--
85
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IC41C4100
IC41LV4100
8
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-35
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Units
t
RC
Random READ or WRITE Cycle Time
60
--
90
--
110
--
ns
t
RAC
Access Time from
RAS
(6, 7)
--
35
--
50
--
60
ns
t
CAC
Access Time from
CAS
(6, 8, 15)
--
10
--
14
--
15
ns
t
AA
Access Time from Column-Address
(6)
--
18
--
25
--
30
ns
t
RAS
RAS
Pulse Width
35
10K
50
10K
60
10K
ns
t
RP
RAS
Precharge Time
20
--
30
--
40
--
ns
t
CAS
CAS
Pulse Width
(26)
6
10K
8
10K
10
10K
ns
t
CP
CAS
Precharge Time
(9, 25)
5
--
8
--
10
--
ns
t
CSH
CAS
Hold Time
(21)
35
--
50
--
60
--
ns
t
RCD
RAS
to
CAS
Delay Time
(10, 20)
11
28
19
36
20
45
ns
t
ASR
Row-Address Setup Time
0
--
0
--
0
--
ns
t
RAH
Row-Address Hold Time
6
--
8
--
10
--
ns
t
ASC
Column-Address Setup Time
(20)
0
--
0
--
0
--
ns
t
CAH
Column-Address Hold Time
(20)
6
--
8
--
10
--
ns
t
AR
Column-Address Hold Time
30
--
40
--
40
--
ns
(referenced to
RAS
)
t
RAD
RAS
to Column-Address Delay Time
(11)
10
20
14
25
15
30
ns
t
RAL
Column-Address to
RAS
Lead Time
18
--
25
--
30
--
ns
t
RPC
RAS
to
CAS
Precharge Time
0
--
0
--
0
--
ns
t
RSH
RAS
Hold Time
(27)
8
--
14
--
15
--
ns
t
CLZ
CAS
to Output in Low-Z
(15, 29)
3
--
3
--
3
--
ns
t
CRP
CAS
to
RAS
Precharge Time
(21)
5
--
5
--
5
--
ns
t
OD
Output Disable Time
(19, 28, 29)
3
12
3
12
3
12
ns
t
OE
Output Enable Time
(15, 16)
0
10
0
15
--
15
ns
t
OEHC
OE
HIGH Hold Time from
CAS
HIGH
10
--
10
--
10
--
ns
t
OEP
OE
HIGH Pulse Width
10
--
10
--
10
--
ns
t
OES
OE
LOW to
CAS
HIGH Setup Time
5
--
5
--
5
--
ns
t
RCS
Read Command Setup Time
(17, 20)
0
--
0
--
0
--
ns
t
RRH
Read Command Hold Time
0
--
0
--
0
--
ns
(referenced to
RAS
)
(12)
t
RCH
Read Command Hold Time
0
--
0
--
0
--
ns
(referenced to
CAS
)
(12, 17, 21)
t
WCH
Write Command Hold Time
(17, 27)
5
--
8
--
10
--
ns
t
WCR
Write Command Hold Time
30
--
40
--
50
--
ns
(referenced to
RAS
)
(17)
t
WP
Write Command Pulse Width
(17)
5
--
8
--
10
--
ns
t
WPZ
WE
Pulse Widths to Disable Outputs
10
--
10
--
10
--
ns
t
RWL
Write Command to
RAS
Lead Time
(17)
8
--
14
--
15
--
ns
t
CWL
Write Command to
CAS
Lead Time
(17, 21)
8
--
14
--
15
--
ns
t
WCS
Write Command Setup Time
(14, 17, 20)
0
--
0
--
0
--
ns
t
DHR
Data-in Hold Time (referenced to
RAS
)
30
--
40
--
40
--
ns
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
9
DR027-0A 09/05/2001
AC CHARACTERISTICS
(Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
35
-50
-60
Symbol
Parameter
Min. Max.
Min. Max.
Min. Max.
Units
t
ACH
Column-Address Setup Time to
CAS
15
--
15
--
15
--
ns
Precharge during WRITE Cycle
t
OEH
OE
Hold Time from
WE
during
8
--
10
--
15
--
ns
READ-MODIFY-WRITE cycle
(18)
t
DS
Data-In Setup Time
(15, 22)
0
--
0
--
0
--
ns
t
DH
Data-In Hold Time
(15, 22)
6
--
8
--
10
--
ns
t
RWC
READ-MODIFY-WRITE Cycle Time
80
--
125
--
140
--
ns
t
RWD
RAS
to
WE
Delay Time during
45
--
70
--
80
--
ns
READ-MODIFY-WRITE Cycle
(14)
t
CWD
CAS
to
WE
Delay Time
(14, 20)
25
--
34
--
36
--
ns
t
AWD
Column-Address to
WE
Delay Time
(14)
30
--
42
--
49
--
ns
t
PC
EDO Page Mode READ or WRITE
12
--
20
--
25
--
ns
Cycle Time
(24)
t
RASP
RAS
Pulse Width in EDO Page Mode
35
100K
50
100K
50
100K
ns
t
CPA
Access Time from
CAS
Precharge
(15)
--
21
--
27
--
34
ns
t
PRWC
EDO Page Mode READ-WRITE
40
--
47
--
56
--
ns
Cycle Time
(24)
t
COH
Data Output Hold after
CAS
LOW
5
--
5
--
5
--
ns
t
OFF
Output Buffer Turn-Off Delay from
3
15
3
15
3
15
ns
CAS
or
RAS
(13,15,19, 29)
t
WHZ
Output Disable Delay from
WE
3
15
3
15
3
15
ns
t
CLCH
Last
CAS
going LOW to First
CAS
10
--
10
--
10
--
ns
returning HIGH
(23)
t
CSR
CAS
Setup Time (CBR REFRESH)
(30, 20)
8
--
10
--
10
--
ns
t
CHR
CAS
Hold Time (CBR REFRESH)
(30, 21)
8
--
10
--
10
--
ns
t
ORD
OE
Setup Time prior to
RAS
during
0
--
0
--
0
--
ns
HIDDEN REFRESH Cycle
t
REF
Refresh Period (512 Cycles)
--
8
8
--
8
--
ms
t
T
Transition Time (Rise or Fall)
(2, 3)
1
50
1
50
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF (Vcc = 5.0V 10%)
One TTL Load and 50 pF (Vcc = 3.3V 10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V 10%);
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V 10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5V 10%, 3.3V 10%)
IC41C4100
IC41LV4100
10
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
Notes:
1. An initial pause of 200 s is required after power-up followed by eight
RAS
refresh cycle (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IH
and V
IL
(or between V
IL
and V
IH
) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
4. If
CAS
and
RAS
= V
IH
, data output is High-Z.
5. If
CAS
= V
IL
, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that t
RCD
t
RCD
(MAX). If t
RCD
is greater than the maximum recommended value shown in this table, t
RAC
will increase
by the amount that t
RCD
exceeds the value shown.
8. Assumes that t
RCD
t
RCD
(MAX).
9. If
CAS
is LOW at the falling edge of
RAS
, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer,
CAS
and
RAS
must be pulsed for t
CP
.
10. Operation with the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference point only; if t
RCD
is greater than the specified t
RCD
(MAX) limit, access time is controlled exclusively by t
CAC
.
11. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only; if t
RAD
is greater than the specified t
RAD
(MAX) limit, access time is controlled exclusively by t
AA
.
12. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
13. t
OFF
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
.
14. t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t
WCS
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
RWD
t
RWD
(MIN), t
AWD
t
AWD
(MIN) and t
CWD
t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until
CAS
and
RAS
or
OE
go back
to V
IH
) is indeterminate.
OE
held HIGH and
WE
taken LOW after
CAS
goes LOW result in a LATE WRITE (
OE
-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding
CAS
input.
16. During a READ cycle, if
OE
is LOW then taken HIGH before
CAS
goes HIGH, I/O goes open. If
OE
is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as
WE
going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both t
OD
and t
OEH
met (
OE
HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if
CAS
remains LOW
and
OE
is taken back to LOW after t
OEH
is met.
19. The I/Os are in open during READ cycles once t
OD
or t
OFF
occur.
20. The first
CAS
edge to transition LOW.
21. The last
CAS
edge to transition HIGH.
22. These parameters are referenced to
CAS
leading edge in EARLY WRITE cycles and
WE
leading edge in LATE WRITE or READ-
MODIFY-WRITE cycles.
23. Last falling
CAS
edge to first rising
CAS
edge.
24. Last rising
CAS
edge to next cycle's last rising
CAS
edge.
25. Last rising
CAS
edge to first falling
CAS
edge.
26. Each
CAS
must meet minimum pulse width.
27. Last
CAS
to go LOW.
28. I/Os controlled, regardless
CAS
.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
11
DR027-0A 09/05/2001
READ CYCLE
Note:
1. t
OFF
is referenced from rising edge of
RAS
or
CAS
, whichever occurs last.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
Open
Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF
(1)
t
RAC
t
CLZ
t
OES
t
OE
t
OD
Undefined
Don't Care
IC41C4100
IC41LV4100
12
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
EARLY WRITE CYCLE
(
OE
= DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don't Care
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
13
DR027-0A 09/05/2001
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O
Open
Open
Valid D
OUT
Valid D
IN
Undefined
Don't Care
IC41C4100
IC41LV4100
14
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
EDO-PAGE-MODE READ CYCLE
Note:
1. t
PC
can be measured from falling edge of
CAS
to falling edge of
CAS
, or from rising edge of
CAS
to rising edge of
CAS
. Both
measurements must meet the t
PC
specifications.
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
(1)
t
ASR
t
RAH
t
RAD
t
AR
Column
Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Open
Open
Valid Data
t
AA
t
AA
t
CPA
t
CAC
t
CAC
t
RAC
t
COH
t
CLZ
t
OEP
t
OE
t
OES
t
OES
t
OD
t
OE
t
OEHC
Valid Data
t
RCH
t
RRH
t
AA
t
CPA
t
CAC
t
OFF
t
CLZ
Valid Data
t
OD
t
ASC
t
RCS
Undefined
Don't Care
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
15
DR027-0A 09/05/2001
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
t
ASR
t
RAH
t
RAD
t
AR
t
ACH
Column
Column
t
ACH
t
ACH
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Valid Data
t
ASC
t
WCS
t
WCH
t
CWL
t
WP
t
WCS
t
WCH
t
CWL
t
WP
t
DS
t
DH
t
DHR
t
WCR
t
WCS
t
WCH
t
CWL
t
WP
Valid Data
t
DS
t
DH
Valid Data
t
DS
t
RWL
t
DH
Don't Care
IC41C4100
IC41LV4100
16
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY WRITE Cycles)
Note:
1. t
PC
is for LATE write cycles only. t
PC
can be measured from falling edge of
CAS
to falling edge of
CAS
, or from rising edge of
CAS
to rising edge of
CAS
. Both measurements must meet the t
PC
specifications.
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
AR
t
ASR
Column
Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS,
t
CLCH
t
CAS,
t
CLCH
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open
Open
D
IN
D
OUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
D
IN
D
OUT
t
DH
t
DS
t
CAC
t
CLZ
D
IN
D
OUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
Undefined
Don't Care
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
17
DR027-0A 09/05/2001
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY WRITE)
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CRP
t
RCD
t
PC
t
CSH
t
CP
t
CAH
t
CAS
t
RAL
t
RSH
t
CP
t
CP
t
ACH
t
RAH
t
RAD
t
AR
t
ASR
Column (A)
Column (N)
t
CAH
t
CAH
Column (B)
t
ASC
t
ASC
t
CAS
t
CAS
OE
I/O
WE
t
ASC
t
CAC
t
RCH
t
DH
Open
Open
Valid Data (A)
t
OE
t
WCS
t
CAC
t
COH
D
IN
t
CPA
t
WCH
t
RAC
t
AA
t
PC
Valid Data (B)
t
WHZ
t
DS
t
RCS
t
AA
Don't Care
IC41C4100
IC41LV4100
18
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
AC WAVEFORMS
READ CYCLE
(With
WE
-Controlled Disable)
RAS
RAS
RAS
RAS
RAS-ONLY REFRESH CYCLE
(
OE
,
WE
= DON'T CARE)
t
AR
t
CAH
t
ASC
t
ASC
t
RAD
OE
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Open
Open
Valid Data
t
CSH
t
CAS
t
CRP
t
RCD
t
CP
t
RAH
t
ASR
t
RCH
t
RCS
t
WPZ
t
RCS
t
AA
t
CAC
t
WHZ
t
RAC
t
CLZ
t
CLZ
t
OE
t
OD
Column
t
RAS
t
RC
t
RP
I/O
ADDRESS
CAS
RAS
Row
Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Undefined
Don't Care
Don't Care
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
19
DR027-0A 09/05/2001
HIDDEN REFRESH CYCLE
(1)
(
WE
= HIGH;
OE
= LOW)
CBR REFRESH CYCLE
(Addresses;
WE
,
OE
= DON'T CARE)
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case,
WE
= LOW and
OE
= HIGH.
2. t
OFF
is referenced from rising edge of
RAS
or
CAS
, whichever occurs last.
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS
Row
Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O
Open
Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Undefined
Don't Care
IC41C4100
IC41LV4100
20
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
ORDERING INFORMATION
IC41C4100
Commercial Range: 0C to 70C
Speed (ns) Order Part No.
PacJage
35
IC41C4100-35J
300mil SOJ
IS41C4100-35T
300mil TSOP-2
50
IC41C4100-50J
300mil SOJ
IC41C4100-50T
300mil TSOP-2
60
IC41C4100-60J
300mil SOJ
IC41C4100-60T
300mil TSOP-2
ORDERING INFORMATION:
IC41LV4100
Commercial Range: 0C to 70C
Speed (ns) Order Part No.
Package
35
IC41LV4100-35J
300mil SOJ
IC41LV4100-35T
300mil TSOP-2
50
IC41LV4100-50J
300mil SOJ
IC41LV4100-50T
300mil TSOP-2
60
IC41LV4100-60J
300mil SOJ
IC41LV4100-60T
300mil TSOP-2
Industrial Range: -40C to 85C
Speed (ns) Order Part No.
Package
35
IC41C4100-35JI
300mil SOJ
IC41C4100-35TI
300mil TSOP-2
50
IC41C4100-50JI
300mil SOJ
IC41C4100-50TI
300mil TSOP-2
60
IC41C4100-60JI
300mil SOJ
IC41C4100-60TI
300mil TSOP-2
Industrial Range: -40C to 85C
Speed (ns) Order Part No.
Package
35
IC41LV4100-35J
300mil SOJ
IC41LV4100-35T
300mil TSOP-2
50
IC41LV4100-50JI
300mil SOJ
IC41LV4100-50TI
300mil TSOP-2
60
IC41LV4100-60JI
300mil SOJ
IC41LV4100-60TI
300mil TSOP-2
IC41C4100
IC41LV4100
Integrated Circuit Solution Inc.
21
DR027-0A 09/05/2001
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw