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Электронный компонент: IC41LV82002-50T

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.EATURES
Extended Data-Out (EDO) Page Mode
access cycle
TTL compatible inputs and outputs
Refresh Interval:
-- 2,048 cycles/32 ms
Refresh Mode: 4)5-Only,
+)5-before-4)5 (CBR), and Hidden
JEDEC standard pinout
Single power supply:
5V10% or 3.3V 10%
Byte Write and Byte Read operation via
+)5
DESCRIPTION
The
1+51
82002 Series is a 2,097,152 x 8-bit high-performance
CMOS Dynamic Random Access Memory. The EDO Page
Mode allows 2,048 random accesses within a single row with
access cycle time as short as 20 ns per 8-bit word.
These features make the 82002 Series ideally suited for high-
bandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 82002 Series is packaged in a 28-pin 300mil SOJ and a 28
pin TSOP-2
IC41C82002
IC41LV82002
2M x 8 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
Integrated Circuit Solution Inc.
1
DR017-0A 06/22/2001
KEY TIMING PARAMETERS
Parameter
-50
-60 Unit
RAS Access Time (t
RAC
)
50
60
ns
CAS Access Time (t
CAC
)
13
15
ns
Column Address Access Time (t
AA
)
25
30
ns
EDO Page Mode Cycle Time (t
PC
)
20
25
ns
Read/Write Cycle Time (t
RC
)
84
104
ns
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
PRODUCT SERIES OVERVIEW
Part No.
Refresh
Voltage
IC41C82002
2K
5V 10%
IC41LV82002
2K
3.3V 10%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
WE
RAS
NC
A10
A0
A1
A2
A3
VCC
GND
I/O7
I/O6
I/O5
I/O4
CAS
OE
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A10
Address Inputs
I/O0-7
Data Inputs/Outputs
WE
Write Enable
OE
Output Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Vcc
Power
GND
Ground
NC
No Connection
PIN CON.IGURATION
28 Pin SOJ, TSOP-2
IC41C82002
IC41LV82002
2
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
.UNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
MEMORY ARRAY
2,097,152 x 8
ROW DECODER
DATA I/O BUFFERS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
I/O0-I/O7
RAS
RAS
A0-A10
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
TRUTH TABLE
.unction
RAS
RAS
RAS
RAS
RAS
CAS
CAS
CAS
CAS
CAS
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Address t
R
/t
C
I/O
Standby
H
H
X
X
X
High-Z
Read
L
L
H
L
ROW/COL
D
OUT
Write: Word (Early Write)
L
L
L
X
ROW/COL
D
IN
Read-Write
L
L
H
L
L
H
ROW/COL
D
OUT
, D
IN
Hidden Refresh
Read
L
H
L
L
H
L
ROW/COL
D
OUT
Write
(1)
L
H
L
L
L
X
ROW/COL
D
OUT
RAS-Only Refresh
L
H
X
X
ROW/NA
High-Z
CBR Refresh
H
L
L
X
X
X
High-Z
Note:
1. EARLY WRITE only.
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
3
DR017-0A 06/22/2001
.unctional Description
The IC41C82002 and IC41LV82002 are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 address bits. These
are entered 11 bits (A0-A10) at a time for the 2K refresh
device. The row address is latched by the Row Address
Strobe (RAS). The column address is latched by the
Column Address Strobe (CAS). RAS is used to latch the
first nine bits and CAS is used the latter ten bits.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OEA
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
Refresh Cycle
To retain data, 2,048 refresh cycles are required in each
32 ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) with RAS at least once every 32 ms. Any
read, write, read-modify-write or RAS-only cycle re-
freshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-
RAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 11-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the V
CC
supply, an initial pause of
200 s is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
V
CC
or be held at a valid V
IH
to avoid current surges.
IC41C82002
IC41LV82002
4
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
T
Voltage on Any Pin Relative to GND5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
V
CC
Supply Voltage
5V
1.0 to +7.0
V
3.3V
0.5 to +4.6
I
OUT
Output Current
50
mA
P
D
Power Dissipation
1
W
T
A
Commercial Operation Temperature
0 to +70
C
T
STG
Storage Temperature
55 to +125
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltages are referenced to GND.)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
5V
4.5
5.0
5.5
V
3.3V
3.0
3.3
3.6
V
IH
Input High Voltage
5V
2.4
V
CC
+ 1.0
V
3.3V
2.0
V
CC
+ 0.3
V
IL
Input Low Voltage
5V
1.0
0.8
V
3.3V
0.3
0.8
T
A
Commercial Ambient Temperature
0
70
C
CAPACITANCE
(1,2)
Symbol
Parameter
Max.
Unit
C
IN
1
Input Capacitance: A0-A10
5
p.
C
IN
2
Input Capacitance: RAS, CAS, WE, OE
7
p.
C
IO
Data Input/Output Capacitance: I/O0-I/O7
7
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz.
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
5
DR017-0A 06/22/2001
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
Test Condition
Speed Min.
Max.
Unit
I
IL
Input Leakage Current
Any input 0V < V
IN
< Vcc
5
5
A
Other inputs not under test = 0V
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
5
5
A
0V < V
OUT
< Vcc
V
OH
Output High Voltage Level
I
OH
= 5.0 mA with V
CC
=5V
2.4
V
I
OH
= 2.0 mA with V
CC
=3.3V
V
OL
Output Low Voltage Level
I
OL
= 4.2 mA with V
CC
=5V
0.4
V
I
OL
= 2 mA with V
CC
=3.3V
I
CC
1
Standby Current: TTL
RAS, CAS > V
IH
5V
2
mA
3.3V
0.5
I
CC
2
Standby Current: CMOS
RAS, CAS > V
CC
0.2V
5V
1
mA
3.3V
0.5
I
CC
3
Operating Current:
RAS, CAS,
-50
120
mA
Random Read/Write
(2,3,4)
Address Cycling, t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
I
CC
4
Operating Current:
RAS = V
IL
, CAS,
-50
90
mA
EDO Page Mode
(2,3,4)
t
RC
= t
RC
(min.)
-60
80
Average Power Supply Current
I
CC
5
Refresh Current:
RAS Cycling, CAS > V
IH
-50
120
mA
RAS-Only
(2,3)
t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
I
CC
6
Refresh Current:
RAS, CAS Cycling
-50
120
mA
CBR
(2,3,5)
t
RC
= t
RC
(min.)
-60
110
Average Power Supply Current
Notes:
1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
RE.
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
IC41C82002
IC41LV82002
6
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
AC CHARACTERISTICS
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
RC
Random READ or WRITE Cycle Time
84
104
ns
t
RAC
Access Time from RAS
(6, 7)
50
60
ns
t
CAC
Access Time from CAS
(6, 8, 15)
13
15
ns
t
AA
Access Time from Column-Address
(6)
25
30
ns
t
RAS
RAS Pulse Width
50
10K
60
10K
ns
t
RP
RAS Precharge Time
30
40
ns
t
CAS
CAS Pulse Width
(23)
8
10K
10
10K
ns
t
CP
CAS Precharge Time
(9)
9
9
ns
t
CSH
CAS Hold Time
(21)
38
40
ns
t
RCD
RAS to CAS Delay Time
(10, 20)
12
37
14
45
ns
t
ASR
Row-Address Setup Time
0
0
ns
t
RAH
Row-Address Hold Time
7
10
ns
t
ASC
Column-Address Setup Time
(20)
0
0
ns
t
CAH
Column-Address Hold Time
(20)
8
10
ns
t
AR
Column-Address Hold Time
30
40
ns
(referenced to RAS)
t
RAD
RAS to Column-Address Delay Time
(11)
10
25
12
30
ns
t
RAL
Column-Address to RAS Lead Time
25
30
ns
t
RPC
RAS to CAS Precharge Time
5
5
ns
t
RSH
RAS Hold Time
8
10
ns
t
RHCP
RAS Hold Time from CAS Precharge
30
35
ns
t
CLZ
CAS to Output in Low-Z
(15, 24)
0
0
ns
t
CRP
CAS to RAS Precharge Time
(21)
5
5
ns
t
OD
Output Disable Time
(19, 24)
3
15
3
15
ns
t
OE
Output Enable Time
(15, 16)
12
15
ns
t
OED
Output Enable Data Delay (Write)
12
15
ns
t
OEHC
OE HIGH Hold Time from CAS HIGH
5
5
ns
t
OEP
OE HIGH Pulse Width
10
10
ns
t
OES
OE LOW to CAS HIGH Setup Time
5
5
ns
t
RCS
Read Command Setup Time
(17, 20)
0
0
ns
t
RRH
Read Command Hold Time
0
0
ns
(referenced to RAS)
(12)
t
RCH
Read Command Hold Time
0
0
ns
(referenced to CAS)
(12, 17, 21)
t
WCH
Write Command Hold Time
(17)
8
10
ns
t
WCR
Write Command Hold Time
40
50
ns
(referenced to RAS)
(17)
t
WP
Write Command Pulse Width
(17)
8
10
ns
t
WPZ
WE Pulse Widths to Disable Outputs
7
7
ns
t
RWL
Write Command to RAS Lead Time
(17)
13
15
ns
t
CWL
Write Command to CAS Lead Time
(17, 21)
8
10
ns
t
WCS
Write Command Setup Time
(14, 17, 20)
0
0
ns
t
DHR
Data-in Hold Time (referenced to RAS)
39
39
ns
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
7
DR017-0A 06/22/2001
AC CHARACTERISTICS (Continued)
(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
-60
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
t
ACH
Column-Address Setup Time to CAS
15
15
ns
Precharge during WRITE Cycle
t
OEH
OE Hold Time from WE during
8
10
ns
READ-MODI.Y-WRITE cycle
(18)
t
DS
Data-In Setup Time
(15, 22)
0
0
ns
t
DH
Data-In Hold Time
(15, 22)
8
10
ns
t
RWC
READ-MODI.Y-WRITE Cycle Time
108
133
ns
t
RWD
RAS to WE Delay Time during
64
77
ns
READ-MODI.Y-WRITE Cycle
(14)
t
CWD
CAS to WE Delay Time
(14, 20)
26
32
ns
t
AWD
Column-Address to WE Delay Time
(14)
39
47
ns
t
PC
EDO Page Mode READ or WRITE
20
25
ns
Cycle Time
t
RASP
RAS Pulse Width in EDO Page Mode
50
100K
60
100K
ns
t
CPA
Access Time from CAS Precharge
(15)
30
35
ns
t
PRWC
EDO Page Mode READ-WRITE
56
68
ns
Cycle Time
t
COH
Data Output Hold after CAS LOW
5
5
ns
t
O..
Output Buffer Turn-Off Delay from
0
12
0
15
ns
CAS or RAS
(13,15,19, 24)
t
WHZ
Output Disable Delay from WE
3
10
3
10
ns
t
CSR
CAS Setup Time (CBR RE.RESH)
(20, 25)
5
5
ns
t
CHR
CAS Hold Time (CBR RE.RESH)
( 21, 25)
8
10
ns
t
ORD
OE Setup Time prior to RAS during
0
0
ns
HIDDEN RE.RESH Cycle
t
RE.
Auto Refresh Period
2,048 Cycles
32
32
ms
t
T
Transition Time (Rise or .all)
(2, 3)
1
50
1
50
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 p. (Vcc = 5.0V + 10%)
One TTL Load and 50 p. (Vcc = 3.3V + 10%)
Input timing reference levels: V
IH
= 2.4V, V
IL
= 0.8V (Vcc = 5.0V + 10%)
V
IH
= 2.0V, V
IL
= 0.8V (Vcc = 3.3V + 10%)
Output timing reference levels: V
OH
= 2.0V, V
OL
= 0.8V (Vcc = 5.0V + 10%, 3.3V + 10%)
IC41C82002
IC41LV82002
8
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
Notes:
1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the t
RE.
refresh requirement is exceeded.
2. V
IH
(MIN) and V
IL
(MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V
IH
and V
IL
(or between V
IL
and V
IH
) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between V
IH
and V
IL
(or between V
IL
and V
IH
)
in a monotonic manner.
4. If CAS and RAS = V
IH
, data output is High-Z.
5. If CAS = V
IL
, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 p..
7. Assumes that t
RCD
< t
RCD
(MAX). If t
RCD
is greater than the maximum recommended value shown in this table, t
RAC
will increase
by the amount that t
RCD
exceeds the value shown.
8. Assumes that t
RCD
> t
RCD
(MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for t
CP
.
10. Operation with the t
RCD
(MAX) limit ensures that t
RAC
(MAX) can be met. t
RCD
(MAX) is specified as a reference point only; if t
RCD
is greater than the specified t
RCD
(MAX) limit, access time is controlled exclusively by t
CAC
.
11. Operation within the t
RAD
(MAX) limit ensures that t
RCD
(MAX) can be met. t
RAD
(MAX) is specified as a reference point only; if t
RAD
is greater than the specified t
RAD
(MAX) limit, access time is controlled exclusively by t
AA
.
12. Either t
RCH
or t
RRH
must be satisfied for a READ cycle.
13. t
O..
(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
.
14. t
WCS
, t
RWD
, t
AWD
and t
CWD
are restrictive operating parameters in LATE WRITE and READ-MODI.Y-WRITE cycle only. If t
WCS
> t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t
RWD
> t
RWD
(MIN), t
AWD
> t
AWD
(MIN) and t
CWD
> t
CWD
(MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to V
IH
) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODI.Y-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODI.Y-WRITE cycles must have both t
OD
and t
OEH
met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after t
OEH
is met.
19. The I/Os are in open during READ cycles once t
OD
or t
O..
occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-
MODI.Y-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
9
DR017-0A 06/22/2001
READ CYCLE
Note:
1. t
O..
is referenced from rising edge of RAS or CAS, whichever occurs last.
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
OE
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
Open
Open
Valid Data
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RRH
t
RCH
t
RCS
t
AA
t
CAC
t
OFF
(1)
t
RAC
t
CLC
t
OES
t
OE
t
OD
Don't Care
IC41C82002
IC41LV82002
10
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
READ WRITE CYCLE
(LATE WRITE and READ-MODI.Y-WRITE Cycles)
t
RAS
t
RWC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
WE
OE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
RWD
t
CWL
t
CWD
t
RWL
t
AWD
t
WP
t
RCS
t
CAC
t
CLZ
t
DS
t
DH
t
OEH
t
OD
t
OE
t
RAC
t
AA
I/O
Open
Open
Valid D
OUT
Valid D
IN
Don't Care
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
11
DR017-0A 06/22/2001
EARLY WRITE CYCLE
(OE = DON'T CARE)
t
RAS
t
RC
t
RP
t
AR
t
CAH
t
ASC
t
RAD
t
RAL
t
ACH
I/O
WE
ADDRESS
CAS
RAS
Row
Column
Row
t
CSH
t
CAS
t
RSH
t
CRP
t
CLCH
t
RCD
t
RAH
t
ASR
t
CWL
t
WCR
t
WCH
t
RWL
t
WP
t
WCS
t
DH
t
DS
t
DHR
Valid Data
Don't Care
IC41C82002
IC41LV82002
12
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
EDO-PAGE-MODE READ CYCLE
Don't Care
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CAS,
t
CLCH
t
CRP
t
RCD
t
CSH
t
CP
t
CAS,
t
CLCH
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
PC
(1)
t
ASR
t
RAH
t
RAD
t
AR
Column
Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
OE
I/O
WE
Open
Open
Valid Data
t
AA
t
AA
t
CPA
t
CAC
t
CAC
t
RAC
t
COH
t
CLZ
t
OEP
t
OE
t
OES
t
OES
t
OD
t
OE
t
OEHC
Valid Data
t
RCH
t
RRH
t
AA
t
CPA
t
CAC
t
OFF
t
CLZ
Valid Data
t
OD
t
ASC
t
RCS
Note:
1. t
PC
can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the t
PC
specifications.
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
13
DR017-0A 06/22/2001
EDO-PAGE-MODE EARLY-WRITE CYCLE
Don't Care
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CRP
t
RCD
t
PC
t
CSH
t
CP
t
CAH
t
CAS
t
RAL
t
RSH
t
CP
t
CP
t
ACH
t
RAH
t
RAD
t
AR
t
ASR
Column (A)
Column (N)
t
CAH
t
CAH
Column (B)
t
ASC
t
ASC
t
CAS
t
CAS
OE
I/O
WE
t
ASC
t
CAC
t
RCH
t
DH
Open
Open
Valid Data (A)
t
OE
t
WCS
t
CAC
t
COH
D
IN
t
CPA
t
WCH
t
RAC
t
AA
t
PC
Valid Data (B)
t
WHZ
t
DS
t
RCS
t
AA
IC41C82002
IC41LV82002
14
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODI.Y WRITE Cycles)
Don't Care
t
RASP
t
RP
ADDRESS
CAS
RAS
Row
Row
t
CRP
t
RCD
t
CSH
t
CP
t
CAH
t
CAS,
t
CLCH
t
RAL
t
RSH
t
CP
t
CP
t
RAH
t
RAD
t
AR
t
ASR
Column
Column
t
CAH
t
CAH
Column
t
ASC
t
ASC
t
CAS,
t
CLCH
t
CAS,
t
CLCH
OE
I/O
WE
t
ASC
t
RWD
t
RCS
t
CWL
t
WP
t
AWD
t
CWD
t
DH
t
DS
t
CAC
t
CLZ
t
AWD
t
CWD
t
CWL
t
WP
t
AWD
t
CWD
t
CWL
t
RWL
t
WP
Open
Open
D
IN
D
OUT
t
OE
t
OE
t
OE
t
OD
t
OEH
t
OD
t
OD
t
DH
t
DS
t
CPA
t
AA
t
CAC
t
CLZ
D
IN
D
OUT
t
DH
t
DS
t
CAC
t
CLZ
D
IN
D
OUT
t
CPA
t
AA
t
RAC
t
AA
t
PC
/ t
PRWC
(1)
Note:
1. t
PC
can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the t
PC
specifications.
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
15
DR017-0A 06/22/2001
AC WAVE.ORMS
4)5
4)5
4)5
4)5
4)5-ONLY RE.RESH CYCLE
(OE, WE = DON'T CARE)
t
RAS
t
RC
t
RP
I/O
ADDRESS
CAS
RAS
Row
Row
Open
t
CRP
t
RAH
t
ASR
t
RPC
Don't Care
IC41C82002
IC41LV82002
16
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
HIDDEN RE.RESH CYCLE
(WE = HIGH; OE = LOW)
+*4
+*4
+*4
+*4
+*4 RE.RESH CYCLE
(Addresses; WE, OE = DON'T CARE)
t
RAS
t
RAS
t
RP
t
RP
I/O
CAS
RAS
Open
t
CP
t
RPC
t
CSR
t
CHR
t
RPC
t
CSR
t
CHR
t
RAS
t
RAS
t
RP
CAS
RAS
t
CRP
t
RCD
t
RSH
t
CHR
t
AR
t
ASC
t
RAD
ADDRESS
Row
Column
t
RAH
t
ASR
t
RAL
t
CAH
I/O
Open
Open
Valid Data
t
AA
t
CAC
t
RAC
t
CLZ
t
OFF
(2)
OE
t
OE
t
ORD
t
OD
Don't Care
Don't Care
IC41C82002
IC41LV82002
Integrated Circuit Solution Inc.
17
DR017-0A 06/22/2001
ORDERING IN.ORMATION
Commercial Range: 0C to 70C
Voltage: 5V
Speed (ns) Order Part No. Refresh
Package
50
IC41C82002-50J
2K
300mil SOJ
50
IC41C82002-50T
2K
400mil TSOP-2
60
IC41C82002-60J
2K
300mil SOJ
60
IC41C82002-60T
2K
400mil TSOP-2
Voltage: 3.3V
Speed (ns)
Order Part No.
Refresh
Package
50
IC41LV82002-50J
2K
300mil SOJ
50
IC41LV82002-50T
2K
400mil TSOP-2
60
IC41LV82002-60J
2K
300mil SOJ
60
IC41LV82002-60T
2K
400mil TSOP-2
IC41C82002
IC41LV82002
18
Integrated Circuit Solution Inc.
DR017-0A 06/22/2001
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
.ax: 886-3-5783000
BRANCH O..ICE:
7., NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
.AX: 886-2-26962252
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