ChipFind - документация

Электронный компонент: IC42S16100-7T

Скачать:  PDF   ZIP
IC42S16100
Integrated Circuit Solution Inc.
1
DR024-0D 06/25/2004
Document Title
512K x 16 Bit x 2 Banks (16-MBIT) SDRAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
August 28,2001
0B
revise for typo on page 17
January 10,2002
0C
Add Pb-free package
December 02,2003
0D
Add speed grade -5ns
June 25,2004
Obselte speed grade -8ns
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
IC42S16100
2
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
Clock frequency: 200, 166, 143 MHz
Fully synchronous; all signals referenced to a
positive clock edge
Two banks can be operated simultaneously and
independently
Dual internal bank controlled by A11 (bank select)
Single 3.3V power supply
LVTTL interface
Programmable burst length
(1, 2, 4, 8, full page)
Programmable burst sequence:
Sequential/Interleave
Auto refresh, self refresh
4096 refresh cycles every 64 ms
Random column address every clock cycle
Programmable CAS latency (2, 3 clocks)
Burst read/write and burst read/single write
operations capability
Burst termination by burst stop and precharge
command
Byte controlled by LDQM and UDQM
Package 400mil 50-pin TSOP-2
Pb(lead)-free package is available
DESCRIPTION
ICSI
's 16Mb Synchronous DRAM IC42S16100 is organized
as a 524,288-word x 16-bit x 2-bank for improved
performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and
outputs signals refer to the rising edge of the clock input.
512K x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
PIN CONFIGURATIONS
50-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VCC
I/O0
I/O1
GNDQ
I/O2
I/O3
VCCQ
I/O4
I/O5
GNDQ
I/O6
I/O7
VCCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VCC
GND
I/O15
I/O14
GNDQ
I/O13
I/O12
VCCQ
I/O11
I/O10
GNDQ
I/O9
I/O8
VCCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
PIN DESCRIPTIONS
A0-A11
Address Input
A0-A10
Row Address Input
A11
Bank Select Address
A0-A7
Column Address Input
I/O0 to I/O15
Data I/O
CLK
System Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe Command
CAS
Column Address Strobe Command
WE
Write Enable
LDQM
Lower Bye, Input/Output Mask
UDQM
Upper Bye, Input/Output Mask
Vcc
Power
GND
Ground
VccQ
Power Supply for I/O Pin
GNDQ
Ground for I/O Pin
NC
No Connection
IC42S16100
Integrated Circuit Solution Inc.
3
DR024-0D 06/25/2004
PIN FUNCTIONS
Pin No.
Symbol
Type
Function (In Detail)
20 to 24
A0-A10
Input Pin
A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32
command input and A0-A7 as column address inputs during read or write command
input. A10 is also used to determine the precharge mode during other commands. If
A10 is LOW during precharge command, the bank selected by A11 is precharged,
but if A10 is HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automati-
cally after the burst access.
These signals become part of the OP CODE during mode register set command
input.
19
A11
Input Pin
A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when
high, bank 1 is selected. This signal becomes part of the OP CODE during mode
register set command input.
16
CAS
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
34
CKE
Input Pin
The CKE input determines whether the CLK input is enabled within the device.
When is CKE HIGH, the next rising edge of the CLK signal will be valid, and when
LOW, invalid. When CKE is LOW, the device will be in either the power-down mode,
the clock suspend mode, or the self refresh mode. The CKE is an asynchronous input.
35
CLK
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
18
CS
Input Pin
The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9, 11 I/O0 to
I/O Pin
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
12, 39, 40, 42, 43,
I/O15
using the LDQM and UDQM pins.
45, 46, 48, 49
14, 36
LDQM,
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
UDQM
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW,
the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go
to the HIGH impedance state when LDQM/UDQM is HIGH. This function corre-
sponds to OE in conventional DRAMs. In write mode, LDQM and UDQM control the
input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is
enabled, and data can be written to the device. When LDQM or UDQM is HIGH,
input data is masked and cannot be written to the device.
17
RAS
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
15
WE
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.
7, 13, 38, 44
V
CC
Q
Power Supply Pin
V
CC
Q is the output buffer power supply.
1, 25
V
CC
Power Supply Pin
V
CC
is the device internal power supply.
4, 10, 41, 47
GNDQ
Power Supply Pin
GNDQ is the output buffer ground.
26, 50
GND
Power Supply Pin
GND is the device internal ground.
IC42S16100
4
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MUL
TIPLEXER
ROW
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
COLUMN
ADDRESS LA
TCH
BURST
COUNTER
COLUMN
ADDRESS BUFFER
ROW DECODER
ROW DECODER
MEMORY CELL
ARRAY
BANK 0
COLUMN DECODER
MEMORY CELL
ARRAY
BANK 1
DATA IN
BUFFER
DATA OUT
BUFFER
SENSE AMP I/O GATE
SENSE AMP I/O GATE
2048
2048
DQM
I/O 0-15
Vcc/VccQ
GND/GNDQ
11
11
11
11
8
11
11
8
16
16
16
16
256
256
S16BLK.eps
IC42S16100
Integrated Circuit Solution Inc.
5
DR024-0D 06/25/2004
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameters
Rating
Unit
V
CC
MAX
Maximum Supply Voltage
1.0 to +4.6
V
V
CCQ
MAX
Maximum Supply Voltage for Output Buffer
1.0 to +4.6
V
V
IN
Input Voltage
1.0 to +4.6
V
V
OUT
Output Voltage
1.0 to +4.6
V
P
D
MAX
Allowable Power Dissipation
1
W
I
CS
Output Shorted Current
50
mA
T
OPR
Operating Temperature
0 to +70
C
T
STG
Storage Temperature
55 to +150
C
DC RECOMMENDED OPERATING CONDITIONS
(2)
(
At T
A
= 0 to +70C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
, V
CC
Q
Supply Voltage
3.0
3.3
3.6
V
V
IH
Input High Voltage
(3)
2.0
--
V
DD
+ 0.3
V
V
IL
Input Low Voltage
(4)
-0.3
--
+0.8
V
CAPACITANCE CHARACTERISTICS
(1,2)
(At T
A
= 0 to +25C, Vcc = VccQ = 3.3 0.3V, f = 1 MHz)
Symbol
Parameter
Typ.
Max.
Unit
C
IN
1
Input Capacitance: A0-A11
--
4
pF
C
IN
2
Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM)
--
4
pF
CI/O
Data Input/Output Capacitance: I/O0-I/O15
--
5
pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All voltages are referenced to GND.
3. V
IH
(max) = V
CCQ
+ 2.0V with a pulse width
3 ns.
4. V
IL
(min) = GND 2.0V with a pulse < 3 ns and -1.5V with a pulse < 5ns.