ChipFind - документация

Электронный компонент: IC61C256AH-20NI

Скачать:  PDF   ZIP
IC61C256AH
Integrated Circuit Solution Inc.
1
AHSR010-0D 4/19/2002
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Document Title
32K x 8 High Speed SRAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
March 23,2001
0B
Revise typo of t
HA
on page 7
October 18,2001
0C
Add SOP package type
February 18,2002
0D
Revise typo of sop size at page 2,9
April 19,2002
IC61C256AH
2
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
High-speed access times: 10, 12, 15, 20, 25 ns
Low active power: 400 mW (typical)
Low standby power
-- 250
W (typical) CMOS standby
-- 55 mW (typical) TTL standby
Fully static operation: no clock or refresh
required
TTL compatible interface and outputs
Single 5V power supply
DESCRIPTION
The
ICSI
IC61C256AH is very high-speed, low power, 32,768
word by 8-bit static RAMs. They are fabricated using
ICSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50
W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (
CE
). The active LOW Write Enable (
WE
) controls
both writing and reading of the memory.
The IC61C256AH is pin compatible with other 32k x
8
SRAMs
and are available in 28-pin 300mil PDIP, 300mil SOJ, and
8*13.4mm TSOP-1 package, 330 mil SOP.
32K x 8 HIGH-SPEED CMOS STATIC RAM
FUNCTIONAL BLOCK DIAGRAM
A0-A14
CE
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
IC61C256AH
Integrated Circuit Solution Inc.
3
AHSR010-0D 4/19/2002
PIN CONFIGURATION
28-Pin DIP and SOJ and SOP
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
PIN DESCRIPTIONS
A0-A14
Address Inputs
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE
CE
CE
CE
CE
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
High-Z
I
SB
1
, I
SB
2
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
1
,I
CC
2
Read
H
L
L
D
OUT
I
CC
1
, I
CC
2
Write
L
L
X
D
IN
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
D
Power Dissipation
1.5
W
I
OUT
DC Output Current (LOW)
20
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
IC61C256AH
4
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
-15
-20
-25
Sym. Parameter
Test Conditions
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
I
CC
Vcc Dynamic Operating V
CC
= Max.,
CE
= V
IL
Com.
-- 145
-- 135
-- 125
-- 120
-- 120
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
-- 180
-- 170
-- 160
-- 150
-- 140
I
SB
1
TTL Standby Current
V
CC
= Max.,
Com.
-- 25
-- 25
-- 25
-- 25
-- 25
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
-- 30
-- 30
-- 30
-- 30
-- 30
CE
V
IH
, f = 0
I
SB
2
CMOS Standby
V
CC
= Max.,
Com.
-- 2
-- 2
-- 2
-- 2
-- 2
mA
Current (CMOS Inputs)
CE
V
CC
0.2V,
Ind.
-- 10
-- 10
-- 10
-- 10
-- 10
V
IN
V
CC
0.2V, or
V
IN
0.2V, f = 0
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 4.0 mA
2.4
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 8.0 mA
--
0.4
V
V
IH
Input HIGH Voltage
(1)
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
(2)
0.5
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
5
5
A
Ind.
10
10
I
LO
Output Leakage
GND
V
OUT
V
CC
,
Com.
5
5
A
Outputs Disabled
Ind.
10
10
Notes:
1. V
IH
=V
CC
+3.0V for pulse width less than 10ns.
2. V
IL
= 3.0V for pulse width less than 10 ns.
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
10
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 5V.
OPERATING RANGE
Range
Ambient Temperature
Speed
V
CC
Commercial
0C to +70C
-10, -12
5V, 5%
-15, -20
5V 10%
Industrial
40C to +85C
-12
5V 5%
-15, -20, -25
5V 10%
Notes:
1. 8 ns is preliminary.
IC61C256AH
Integrated Circuit Solution Inc.
5
AHSR010-0D 4/19/2002
AC TEST LOADS
Figure 1.
Figure 2.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and Fall Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See Figures 1 and 2
480
30 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10
-12
-15
-20
-25
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
10
--
12
--
15
--
20
--
25
--
ns
t
AA
Address Access Time
--
10
--
12
--
15
--
20
--
25
ns
t
OHA
Output Hold Time
2
--
2
--
2
--
2
--
2
--
ns
t
ACE
CE
Access Time
--
10
--
12
--
15
--
20
--
25
ns
t
DOE
OE
Access Time
--
5
--
5
--
7
--
8
--
9
ns
t
LZOE
(2)
OE
to Low-Z Output
0
--
0
--
0
--
0
--
0
--
ns
t
HZOE
(2)
OE
to High-Z Output
--
5
--
6
--
7
--
9
--
10
ns
t
LZCE
(2)
CE
to Low-Z Output
2
--
3
--
3
--
3
--
3
--
ns
t
HZCE
(2)
CE
to High-Z Output
--
5
--
7
--
8
--
9
--
10
ns
t
PU
(3)
CE
to Power-Up
0
--
0
--
0
--
0
--
0
--
ns
t
PD
(3)
CE
to Power-Down
--
10
--
12
--
15
--
18
--
20
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.