IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

Document Title

256K x 8 Hight Speed SRAM with 3.3V

Revision History

Revision No

History

Draft Date

Remark

Initial Draft

September 12,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution, Inc.

FEATURES

· High-speed access times:

-- 8, 10, 12 and 15 ns

· High-preformance, lower-power CMOS process
· Multiple center power and ground pins for

greater noise immunity

· Easy memory expansion with

and

options

power-down

· CMOS power: 540 mW @ 10 ns

36 mW standby mode

· TTL compatible inputs and outputs
· Single 3.3V

10% power supply

· Packages available:

-- 36-pin 400mil SOJ
-- 44-pin TSOP-2

DESCRIPTION

The

ICSI

IC61LV2568 is a very high-speed, low power,

262,144-word by 8-bit COMS static RAM. The IC61LV2568 is
fabricated using

ICSI

's high-performance CMOS technology.

This highly reliable process coupled with innovative circuit
design techniques, yields higher preformance and low power
consumotion devices.

When

is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down to
36 mW (max.) with CMOS input levels.

The IC61LV2568 operates from a single 3.3V power supply and
all inputs are TTL-compatible.

The IC61LV2568 is available in 36-pin, 400mil SOJ and 44-pin
TSOP-2 package.

256K x 8 HIGH-SPEED CMOS STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

A0-A17

256K X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

PIN CONFIGURATION

36-Pin SOJ

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

NC
NC

A4
A3
A2
A1
A0

I/O0
I/O1

Vcc

GND

I/O2
I/O3

A17
A16
A15
A14
A13

NC
NC

NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC

I/O0

I/O1

Vcc

GND

I/O2

I/O3

A17

A16

A15

A14

A13

I/O7

I/O6

GND

Vcc

I/O5

I/O4

A10

A11

A12

PIN CONFIGURATION

44-Pin TSOP-2

PIN DESCRIPTIONS

A0-A17

Address Inputs

Chip Enable Input

Output Enable Input

Write Enable Input

I/O0-I/O7

Input/Output

Vcc

Power

GND

Ground

No Connection

TRUTH TABLE

Mode

I/O Operation

Vcc Current

Not Selected

High-Z

, I

(Power-down)
Output Disabled

High-Z

Read

OUT

Write

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

Power Supply Voltage Relative to GND

0.5 to +4.6

TERM

Terminal Voltage with Respect to GND

0.5 to Vcc + 0.5 V

BIAS

Temperature Under Bias

Com.

10 to +85

°C

Ind.

45 to +90

STG

Storage Temperature

65 to +150

°C

Power Dissipation

OUT

DC Output Current

±20

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 4.0 mA

2.4

Output LOW Voltage

= Min., I

= 8.0 mA

0.4

Input HIGH Voltage

2.0

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, Outputs Disabled

Com.

µA

Ind.

Notes:

1. V

(min.) = 0.3V (DC); V

(min.) = 2.0V (pulse width

2.0 ns).

(max.) = V

+ 0.3V (DC); V

(max.) = Vcc + 2.0V (pulse width

2.0 ns).

2. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V

10%

Industrial

40°C to +85°C

3.3V

10%

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Sym.

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Vcc Dynamic Operating V

= Max.,

= V

Com. --

170

150

140

130

Supply Current

OUT

= 0 mA, f = f

MAX

Ind. --

180

160

150

140

TTL Standby Current

= Max.,

Com. --

(TTL Inputs)

= V

or V

Ind. --

, f = 0

CMOS Standby

= Max.,

Com. --

Current (CMOS Inputs)

0.2V,

Ind. --

0.2V, or

0.2V, f = 0

Notes:

1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

AC TEST LOADS

Figure 1.

Figure 2.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels
Output Load

See Figures 1 and 2

Notes:

1. The Vcc operating range for 8 ns is 3.3V +10%, -5%.

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min. Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

LZOE

(2)

to Low-Z Output

HZOE

(2)

to High-Z Output

LZCE

(2)

to Low-Z Output

HZCE

(2)

to High-Z Output

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V,

input pulse levels of 0 to 3.0V and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not

100% tested.

319

30 pF

Including

jig and

scope

353

OUTPUT

3.3V

319

5 pF

Including

jig and

scope

353

OUTPUT

3.3V

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

DATA VALID

PREVIOUS DATA VALID

OHA

OUT

ADDRESS

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

ADDRESS

OUT

HZCE

READ CYCLE NO. 2

(1,3)

Notes:

is HIGH for a Read Cycle.

2. The device is continuously selected.

= V

3. Address is valid prior to or coincident with

LOW transitions.

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

AC WAVEFORMS
WRITE CYCLE NO. 1

(1,2 )

(

Controlled,

is HIGH or LOW)

DATA UNDEFINED

VALID ADDRESS

SCE

PWE1

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,2)

(Over Operating Range)

-8 ns

-10 ns

-12 ns

-15 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time

to Write End

Address Hold

from Write End

Address Setup Time

PWE

(4)

Pulse Width

Data Setup to Write End

4.5

Data Hold from Write End

HZWE

(3)

LOW to High-Z Output

LZWE

(3)

HIGH to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse

levels of 0 to 3.0V and output loading specified in Figure 1.

2. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states

to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing

are referenced to the rising or falling edge of the signal that terminates the Write.

3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100%

tested.

4.Tested with

Hith.

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

DATA UNDEFINED

LOW

VALID ADDRESS

PWE1

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

WRITE CYCLE NO. 2

(

Controlled,

is HIGH During Write Cycle)

(1,2)

WRITE CYCLE NO. 3

(

Controlled,

is LOW During Write Cycle)

(1)

DATA UNDEFINED

VALID ADDRESS

LOW

PWE2

HIGH-Z

HZWE

ADDRESS

OUT

DATA

VALID

LZWE

Notes:

1. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

> V

IC61LV2568

Integrated Circuit Solution, Inc.

AHSR023-0A

09/12/2001

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IC61LV2568-8T

400mil T SOP-2

IC61LV2568-8K

400mil SOJ

IC61LV2568-10T

400mil T SOP-2

IC61LV2568-10K

400mil SOJ

IC61LV2568-12T

400mil T SOP-2

IC61LV2568-12K

400mil SOJ

IC61LV2568-15T

400mil T SOP-2

IC61LV2568-15K

400mil SOJ

ORDERING INFORMATION
Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IC61LV2568-8TI

400mil T SOP-2

IC61LV2568-8KI

400mil SOJ

IC61LV2568-10TI

400mil T SOP-2

IC61LV2568-10KI

400mil SOJ

IC61LV2568-12TI

400mil T SOP-2

IC61LV2568-12KI

400mil SOJ

IC61LV2568-15TI

400mil T SOP-2

IC61LV2568-15KI

400mil SOJ

Integrated Circuit Solution, Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5

ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw

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