Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

· Internal self-timed write cycle
· Individual Byte Write Control and Global Write
· Clock controlled, registered address, data and

control

· PentiumTM or linear burst sequence control

using MODE input

· Three chip enables for simple depth expansion

and address pipelining

· Common data inputs and data outputs
· 100-Pin TQFP (JEDEC LQFP) and

119-pin PBGA package

· Single +3.3V, +10%, 5% power supply
· Power-down snooze mode

DESCRIPTION

The

ICSI

IC61SP12832,IC61SP12836 are high-speed, low-

power synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the PentiumTM, 680X0TM,
and PowerPCTM microprocessors. It is organized as 131,072
words by 32 bits, fabricated with

ICSI

's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.

Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1

controls DQa,

BW2

controls DQb,

BW3

controls DQc,

BW4

controls DQd, conditioned by

BWE

being LOW. A LOW

input would cause all bytes to be written.

Bursts can be initiated with either

ADSP

(Address Status

Processor) or

ADSC

(Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally
by the IC61SP12832,IC61SP12836 and controlled by the

ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.

128K x 32, 128K x 36 SYNCHRONOUS

PIPELINED STATIC RAM

FAST ACCESS TIME

Symbol

Parameter

-166

-150

-133

-117

-5

Units

Clock Access Time

3.5

3.8

Cycle Time

6.7

7.5

8.5

Frenquency

166

150

133

117

100

MHz

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

BLOCK DIAGRAM

BINARY

COUNTER

A16-A0

BW1

CLR

CLK

MODE

A0'

A1'

CLK

ADV

ADSC

ADSP

ADDRESS

REGISTER

CLK

DQd

BYTE WRITE

REGISTERS

CLK

DQc

BYTE WRITE

REGISTERS

CLK

DQb

BYTE WRITE

REGISTERS

CLK

DQa

BYTE WRITE

REGISTERS

CLK

ENABLE

REGISTER

CLK

ENABLE

DELAY

REGISTER

CLK

BWE

BW4

CE2

BW2

BW3

128K x 32, 128K x 36

MEMORY

ARRAY

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

DQ[31:0]

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin LQFP

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

A2-A16

Synchronous Address Inputs

CLK

Synchronous Clock

ADSP

Synchronous Processor Address
Status

ADSC

Synchronous Controller Address
Status

ADV

Synchronous Burst Address Advance

BW1

BW4

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

Synchronous Global Write Enable

CE2

, CE2 Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

MODE

Burst Sequence Mode Selection

+3.3V Power Supply

GND

Ground

CCQ

Isolated Output Buffer Supply:
+3.3V

Snooze Enable

GND

Isolated Output Buffer Ground

VCCQ

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

VCCQ

CE2

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

GND

BW3

GND

BW4

GND

MODE

A10

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

A11

A12

GND

BW2

GND

BW1

GND

A14

A16

CE2

A15

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

A13

VCCQ

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

VCCQ

1 2 3 4 5 6 7

NC
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
NC

CE2

BW4

BW3

BW2

BW1

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQc1
DQc2

VCCQ

GND

DQc3
DQc4
DQc5
DQc6

GND

VCCQ

DQc7
DQc8

VCC

GND

DQd1
DQd2

VCCQ

GND

DQd3
DQd4
DQd5
DQd6

GND

VCCQ

DQd7
DQd8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

128K x 32

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

PIN CONFIGURATION

119-pin PBGA (Top View) and 100-Pin LQFP

PIN DESCRIPTIONS

A0, A1

Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.

A2-A16

Synchronous Address Inputs

CLK

Synchronous Clock

ADSP

Synchronous Processor Address
Status

ADSC

Synchronous Controller Address
Status

ADV

Synchronous Burst Address Advance

BW1

BW4

Synchronous Byte Write Enable

BWE

Synchronous Byte Write Enable

Synchronous Global Write Enable

CE2

, CE2 Synchronous Chip Enable

Output Enable

DQa-DQd

Synchronous Data Input/Output

MODE

Burst Sequence Mode Selection

+3.3V Power Supply

GND

Ground

CCQ

Isolated Output Buffer Supply: +3.3V

Snooze Enable

GND

Isolated Output Buffer Ground

DQPa-DQPd

Parity Data I/O

VCCQ

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

VCCQ

CE2

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

GND

BW3

GND

BW4

GND

MODE

A10

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

A11

A12

GND

BW2

GND

BW1

GND

A14

A16

CE2

A15

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

A13

VCCQ

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

VCCQ

1 2 3 4 5 6 7

DQPb
DQb8
DQb7
VCCQ
GND
DQb6
DQb5
DQb4
DQb3
GND
VCCQ
DQb2
DQb1
GND
NC
VCC
ZZ
DQa8
DQa7
VCCQ
GND
DQa6
DQa5
DQa4
DQa3
GND
VCC
DQa2
DQa1
DQPa

CE2

BW4

BW3

BW2

BW1

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQPc

DQc1
DQc2

VCCQ

GND

DQc3
DQc4
DQc5
DQc6

GND

VCCQ

DQc7
DQc8

VCC

GND

DQd1
DQd2

VCCQ

GND

DQd3
DQd4
DQd5
DQd6

GND

VCCQ

DQd7
DQd8

DQPd

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

128K x 36

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

TRUTH TABLE

Address

Operation

Used

CE2

CE2

ADSP

ADSP ADSC

ADSC

ADV

ADV WRITE

WRITE

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Deselected, Power-down

None

High-Z

Read Cycle, Begin Burst External

High-Z

Read Cycle, Begin Burst External

Read

High-Z

Write Cycle, Begin Burst External

Write

High-Z

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Read Cycle, Continue Burst

Read

Read Cycle, Continue Burst

Read

High-Z

Write Cycle, Continue Burst

Write

High-Z

Write Cycle, Continue Burst

Write

High-Z

Read Cycle, Suspend Burst Current

Read

Read Cycle, Suspend Burst Current

Read

High-Z

Read Cycle, Suspend Burst Current

Read

Read Cycle, Suspend Burst Current

Read

High-Z

Write Cycle, Suspend Burst Current

Write

High-Z

Write Cycle, Suspend Burst Current

Write

High-Z

PARTIAL TRUTH TABLE

Function

BWE

BW1

BW2

BW3

BW3 BW4

BW4

Read

Write Byte 1

Write All Bytes

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

INTERLEAVED BURST ADDRESS TABLE (MODE = V

CCQ

or No Connect)

External Address

1st Burst Address

2nd Burst Address

3rd Burst Address

A1 A0

LINEAR BURST ADDRESS TABLE (MODE = GND

)

0,0

1,0

0,1

A1', A0' = 1,1

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

BIAS

Temperature Under Bias

40 to +85

°C

STG

Storage Temperature

55 to +150

°C

Power Dissipation

1.6

OUT

Output Current (per I/O)

100

, V

OUT

Voltage Relative to GND for I/O Pins

0.5 to V

CCQ

+ 0.3

Voltage Relative to GND for

0.5 to V

+ 0.5

for Address and Control Inputs

Voltage on Vcc Supply Relatiive to GND

0.5 to 4.6

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

2. This device contains circuity to protect the inputs against damage due to high static voltages

or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V,

+10%, 5%

Industrial

40°C to +85°C

3.3V,

+10%, 5%

DC ELECTRICAL CHARACTERISTICS

(1)

(Over Operating Range)

Symbol Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= 4.0 mA

2.4

Output LOW Voltage

= 8.0 mA

0.4

Input HIGH Voltage

2.0

CCQ

+ 0.3

Input LOW Voltage

0.3

0.8

Input Leakage Current

GND

CCQ

(2)

Com.

µA

Ind.

Output Leakage Current

GND

OUT

CCQ

= V

Com.

µA

Ind.

POWER SUPPLY CHARACTERISTICS

(Over Operating Range)

-166

-150

-133

-117

-5

Symbol Parameter

Test Conditions

Typ. Max.

Typ. Max. Typ. Max.

Typ. Max

Typ. Max.

Unit

AC Operating

Device Selected,

Com.

200 230

190 220

180 210

175 205

170 200

Supply Current

All Inputs = V

or V

Ind.

200 230

190 220

185 215

180 210

= V

, Vcc = Max.

Cycle Time

min.

Standby Current

Device Deselected,

Com.

= Max.,

Ind.

All Inputs = V

or V

CLK Cycle Time

min.

Power-down Mode

ZZ = V

CCQ

Com.

Current

Clock Running

Ind.

All Inputs

GND + 0.2V

Vcc 0.2V

Notes:

1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to V

CCQ

2. The MODE pin should be tied to Vcc or GND. It exhibits

10 µA maximum leakage current when tied to

GND + 0.2V

Vcc 0.2V.

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Input/Output Capacitance

OUT

= 0V

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

1.5 ns

Input and Output Timing

1.5V

and Reference Level
Output Load

See Figures 1 and 2

AC TEST LOADS

Output
Buffer

= 50

1.5V

30 pF

Figure 2

317

5 pF

Including

jig and

scope

351

OUTPUT

3.3V

Figure 1

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

READ/WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

166

-150

-133

-117

-5

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

MAX

Clock Frequency

166

150

133

117

100

MHz

Cycle Time

6.7

7.5

8.5

Clock High Time

2.4

2.6

2.8

3.4

Clock Low Time

2.4

2.6

2.8

3.4

Clock Access Time

3.5

3.8

KQX

(1)

Clock High to Output Invalid

1.5

2.5

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

1.5

6.7

1.5

7.5

1.5

8.5

1.5

OEQ

Output Enable to Output Valid

3.5

3.8

OEQX

(1)

Output Disable to Output Invalid

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Disable to Output High-Z

3.5

3.8

Address Setup Time

1.5

Address Status Setup Time

1.5

Write Setup Time

1.5

CES

Chip Enable Setup Time

1.5

AVS

Address Advance Setup Time

1.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

READ/WRITE CYCLE TIMING

Single Read

Single Write

High-Z

DATA

OUT

DATA

CE2

BW4-BW1

BWE

A16-A0

ADV

ADSC

ADSP

CLK

RD1

WR1

Unselected

Burst Read

KQX

ADSP is blocked by CE inactive

RD2

RD3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

OEQ

OEQX

OELZ

KQLZ

OEHZ

KQX

KQHZ

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

WRITE CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

166

-150

-133

-117

-5

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Cycle Time

6.7

7.5

8.5

Clock High Time

2.4

2.6

2.8

3.4

Clock Low Time

2.4

2.6

2.8

3.4

Address Setup Time

1.5

Address Status Setup Time

1.5

Write Setup Time

1.5

Data In Setup Time

1.5

CES

Chip Enable Setup Time

1.5

AVS

Address Advance Setup Time

1.5

Address Hold Time

0.5

Address Status Hold Time

0.5

Data In Hold Time

0.5

Write Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

AVH

Address Advance Hold Time

0.5

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

WRITE CYCLE TIMING

Single Write

DATA

OUT

DATA

CE2

BW4-BW1

BWE

A16-A0

ADV

ADSC

ADSP

CLK

WR1

WR2

Unselected

Burst Write

WR3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

ADSC initiate Write

ADSP is blocked by CE inactive

AVH

AVS

ADV must be inactive for ADSP Write

WR1

WR2

WR3

High-Z

BW4-BW1 only are applied to first cycle of WR2

Write

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

166

-150

-133

-117

-5

Symbol Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Cycle Time

6.7

7.5

8.5

Clock High Time

2.4

2.6

2.8

3.4

Clock Low Time

2.4

2.6

2.8

3.4

Clock Access Time

3.5

3.8

KQX

(1)

Clock High to Output Invalid

1.5

2.5

KQLZ

(1,2)

Clock High to Output Low-Z

KQHZ

(1,2)

Clock High to Output High-Z

1.5

3.6

1.5

6.7

1.5

7.5

1.5

8.5

1.5

OEQ

Output Enable to Output Valid

3.5

3.9

OEQX

(1)

Output Disable to Output Invalid

OELZ

(1,2)

Output Enable to Output Low-Z

OEHZ

(1,2)

Output Disable to Output High-Z

3.5

3.8

Address Setup Time

1.5

Address Status Setup Time

1.5

CES

Chip Enable Setup Time

1.5

Address Hold Time

0.5

Address Status Hold Time

0.5

CEH

Chip Enable Hold Time

0.5

ZZS

ZZ Standby

cyc

ZZREC

ZZ Recovery

cyc

Notes:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.

Integrated Circuit Solution Inc.

SSR019-0A

09/17/2001

IC61SP12832
IC61SP12836

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed

Order Part Number

Package

166 MHz

IC61SP12832-166TQ

14x20x1.4mm LQFP

IC61SP12832-166B

14*22mm PBGA

150 MHz

IC61SP12832-150TQ

14*20*1.4mm LQFP

IC61SP12832-150B

14*22mm PBGA

133 MHz

IC61SP12832-133TQ

14*20*1.4mm LQFP

IC61SP12832-133B

14*22mm PBGA

117 MHz

IC61SP12832-117TQ

14*20*1.4mm LQFP

IC61SP12832-117B

14*22mm PBGA

100 MHz

IC61SP12832-5TQ

14*20*1.4mm LQFP

IC61SP12832-5B

14*22mm PBGA

Speed

Order Part Number

Package

166 MHz

IC61SP12836-166TQ

14x20x1.4mm LQFP

IC61SP12836-166B

14*22mm PBGA

150 MHz

IC61SP12836-150TQ

14*20*1.4mm LQFP

IC61SP12836-150B

14*22mm PBGA

133 MHz

IC61SP12836-133TQ

14*20*1.4mm LQFP

IC61SP12836-133B

14*22mm PBGA

117 MHz

IC61SP12836-117TQ

14*20*1.4mm LQFP

IC61SP12836-117B

14*22mm PBGA

100 MHz

IC61SP12836-5TQ

14*20*1.4mm LQFP

IC61SP12836-5B

14*22mm PBGA

Integrated Circuit Solution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5

ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw

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