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Электронный компонент: IC62C256-70UI

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Integrated Circuit Solution Inc.
1
ALSR010-0A 05/23/2001
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
.EATURES
Access time: 45, 70 ns
Low active power: 200 mW (typical)
Low standby power
250 W (typical) CMOS standby
28 mW (typical) TTL standby
.ully static operation: no clock or refresh
required
TTL compatible inputs and outputs
Single 5V power supply
DESCRIPTION
The
1+51
IC62C256 is a low power, 32,768 word by 8-bit
CMOS static RAM. It is fabricated using
1+51
's high-
performance, low power CMOS technology.
When CS is HIGH (deselected), the device assumes a standby
mode at which the power dissipation can be reduced down to
250 W (typical) at CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Select (CS) input and an active LOW Output Enable (OE)
input. The active LOW Write Enable (WE) controls both writing
and reading of the memory.
The IC62C256 is pin compatible with other 32K x 8 SRAMs in
330mil SOP or 8*13.4mm TSOP-1 package.
1+$ + #$
32K x 8 LOW POWER CMOS STATIC RAM
.UNCTIONAL BLOCK DIAGRAM
A0-A14
CS
OE
WE
32K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
1+$ + #$
2
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
PIN CON.IGURATION
28-Pin SOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
A13
A8
A9
A11
OE
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to +7.0
V
T
BIAS
Temperature Under Bias
55 to +125
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
0.5
W
I
OUT
DC Output Current (LOW)
20
mA
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CS
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN CON.IGURATION
8x13.4mm TSOP-1
PIN DESCRIPTIONS
A0-A14
Address Inputs
CS
Chip Select Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CS
CS
CS
CS
CS
OE
OE
OE
OE
OE I/O Operation Vcc Current
Not Selected
X
H
X
High-Z
I
SB
, I
SB
(Power-down)
Output Disabled
H
L
H
High-Z
I
CC
, I
CC
Read
H
L
L
D
OUT
I
CC
, I
CC
Write
L
L
X
D
IN
I
CC
, I
CC
1+$ + #$
Integrated Circuit Solution Inc.
3
ALSR010-0A 05/23/2001
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
5V 10%
Industrial
40C to +85C
5V 10%
CAPACITANCE
(1,2)
Symbol
Parameter
Conditions
Max.Unit
C
IN
Input Capacitance
V
IN
= 0V
8
p.
C
OUT
Output Capacitance
V
OUT
= 0V
10
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25C, f = 1 MHz, Vcc = 5.0V.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns
-70 ns
Symbol
Parameter
Test Conditions
Min.Max.
Min.Max.
Unit
I
CC
Vcc Operating
V
CC
= Max., CS = V
IL
Com.
60
60
mA
Supply Current
I
OUT
= 0 mA, f = 0
Ind.
70
70
I
CC
Vcc Dynamic Operating
V
CC
= Max., CS = V
IL
Com.
70
65
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
80
75
I
SB
TTL Standby Current
V
CC
= Max.,
Com.
5
5
mA
(TTL Inputs)
V
IN
= V
IH
or V
IL
Ind.
10
10
CS
V
IH
, f = 0
I
SB
CMOS Standby
V
CC
= Max.,
Com.
0.5
0.5
mA
Current (CMOS Inputs)
CS
V
CC
0.2V,
Ind.
1.0
1.0
V
IN
V
CC
0.2V, or
V
IN
0.2V, f = 0
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter
Test Conditions
Min.Max.Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1.0 mA
2.4
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
0.4
V
V
IH
Input HIGH Voltage
2.2
V
CC
+ 0.5
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
LI
Input Leakage
GND
V
IN
V
CC
Com.
2
2
A
Ind.
10
10
I
LO
Output Leakage
GND
V
OUT
V
CC
,
Com.
2
2
A
Outputs Disabled
Ind.
10
10
Note:
1. V
IH
=V
CC
+3.0V for pulse width less than 10ns.
2. V
IL
= 3.0V for pulse width less than 10 ns.
1+$ + #$
4
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0V to 3.0V
Input Rise and .all Times
3 ns
Input and Output Timing
1.5V
and Reference Levels
Output Load
See .igures 1 and 2
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-45 ns
-70 ns
Symbol Parameter
Min.Max.
Min. Max.
Unit
t
RC
Read Cycle Time
45
70
ns
t
AA
Address Access Time
45
70
ns
t
OHA
Output Hold Time
2
2
ns
t
ACS
CS Access Time
45
70
ns
t
DOE
OE Access Time
25
35
ns
t
LZOE
OE to Low-Z Output
0
0
ns
t
HZOE
OE to High-Z Output
0
20
0
25
ns
t
LZCS
CS to Low-Z Output
3
3
ns
t
HZCS
CS to High-Z Output
0
20
0
25
ns
t
PU
!
CS to Power-Up
0
0
ns
t
PD
!
CS to Power-Down
30
50
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
.igure 1..igure 2.
480
100 pF
Including
jig and
scope
255
OUTPUT
5V
480
5 pF
Including
jig and
scope
255
OUTPUT
5V
AC TEST LOADS
1+$ + #$
Integrated Circuit Solution Inc.
5
ALSR010-0A 05/23/2001
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
READ CYCLE NO. 2
(1,3)
AC WAVE.ORMS
READ CYCLE NO. 1
(1,2)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS
t
LZCS
t
HZOE
HIGH-Z
DATA VALID
ADDRESS
OE
CS
D
OUT
t
HZCS
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CS = V
IL
.
3. Address is valid prior to or coincident with CS LOW transitions.
1+$ + #$
6
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-45 ns
-70ns
Symbol Parameter
Min.Max.
Min. Max.
Unit
t
WC
Write Cycle Time
45
70
ns
t
SCS
CS to Write End
35
60
ns
t
AW
Address Setup Time to Write End
25
60
ns
t
HA
Address Hold from Write End
1
1
ns
t
SA
Address Setup Time
0
0
ns
t
PWE
"
WE Pulse Width
25
55
ns
t
SD
Data Setup to Write End
20
30
ns
t
HD
Data Hold from Write End
0
0
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVE.ORMS
WRITE CYCLE NO. 1
(CS Controlled, OE is HIGH or LOW)
(1 )
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCS
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
1+$ + #$
Integrated Circuit Solution Inc.
7
ALSR010-0A 05/23/2001
AC WAVE.ORMS
WRITE CYCLE NO. 2
(OE is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE NO. 3
(OE is LOW During Write Cycle)
(1)
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CS
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of Cs LOW and WE LOW. All signals must be in valid states to initiate a
Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
2. I/O will assume the High-Z state if OE
V
IH
.
1+$ + #$
8
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.Max. Unit
V
DR
Vcc for Data Retention
See Data Retention Waveform
2.0
5.5
V
I
DR
Data Retention Current
Vcc =2.0V, CE
Vcc 0.2V
Com.
250
A
Ind.
500
t
SDR
Data Retention Setup Time See Data Retention Waveform
0
ns
t
RDR
Recovery Time
See Data Retention Waveform
5
ns
DATA RETENTION WAVE.ORM
(CE Controlled)
V
CC
CE
V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE
GND
5.0V
3.0V
Data Retention Mode
1+$ + #$
Integrated Circuit Solution Inc.
9
ALSR010-0A 05/23/2001
ORDERING IN.ORMATION
Commerical Range: 0C to +70C
Speed
(ns)
Order Part No.Package
45
IC62C256-45T
8*13.4mm TSOP-1
IC62C256-45U
330mil SOP
70
IC62C256-70T
8*13.4mm TSOP-1
IC62C256-70U
330mil SOP
ORDERING IN.ORMATION
Industrial Range: 40C to +85C
Speed
(ns)
Order Part No.Package
45
IC62C256-45TI
8*13.4mm TSOP-1
IC62C256-45UI
330mil SOP
70
IC62C256-70TI
8*13.4mm TSOP-1
IC62C256-70UI
330mil SOP
1+$ + #$
10
Integrated Circuit Solution Inc.
ALSR010-0A 05/23/2001
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
.ax: 886-3-5783000
BRANCH O..ICE:
7., NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
.AX: 886-2-26962252
http://www.icsi.com.tw