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Электронный компонент: IC62LV1008LL-70DI

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Integrated Circuit Solution Inc.
1
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
January 3,2002
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
2
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The
ICSI
IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using
ICSI
's low voltage, six transistor (6T), CMOS technology. The
device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (
WE
)
controls both writing and reading of the memory.
The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
1M x 8
LOW POWER and LOW V
CC
CMOS STATIC RAM
FEATURES
Access times of 55, 70, 100 ns
CMOS Low power operation:
I
CC
=15mA (typical)* operation
I
SB
2
=2
A
(typical)* standby
Low data retention voltage: 1.5V (min.)
Output Enable (
OE
) and Two Chip Enables
(CE1, CE2) inputs for ease in applications
TTL compatible inputs and outputs
Fully static operation:
--
No clock or refresh reguired
Single 2.7V-3.6V power supply
Wafer level burn in test mode
Available in the know good die form and
48-pin 8*10mm TF-BGA
* Typical values are measured at V
CC
=3.0V, T
A
=25C
Preliminary
A0-A19
CE1
OE
WE
1024K x 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
CE2
Integrated Circuit Solution Inc.
3
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
PIN DESCRIPTIONS
A0-A19
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Data Input/Output
NC
No Connection
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
2.7V - 3.6V
Industrial
40C to +85C
2.7V - 3.6V
TRUTH TABLE
Mode
WE
WE
WE
WE
WE
CE1
CE1
CE1
CE1
CE1
CE2
OE
OE
OE
OE
OE
I/O Operation
Vcc Current
Not Selected
X
H
X
X
High-Z
I
SB
1
, I
SB
2
(P
OWER
-D
OWN
)
X
X
L
X
High-Z
I
SB
1
, I
SB
2
Output Disabled
H
L
H
H
High-Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
PIN CONFIGURATIONS
48
-
Pin 8*10mm TF
-
BGA (TOP View)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
NC
OE
A0
A1
A2
CE2
NC
NC
A3
A4
CE1
NC
I/O
0
A5
A6
I/O
4
GND
Vcc
Vcc
GND
I/O
3
A14
A15
I/O
7
NC
NC
A12
A13
WE
NC
A18
A8
A9
A10
A11
A19
NC
I/O
1
I/O
2
NC
A17
Vcc
A7
A16
NC
I/O
5
I/O
6
NC
4
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.5
V
V
CC
Vcc related to GND
0.3 to +4.0
V
T
BIAS
Temperature Under Bias
40 to +85
C
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)(2)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz, V
CC
= 3.0 V
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
V
CC
= Min., I
OH
= 1.0 mA
2.0
--
V
V
OL
Output LOW Voltage
V
CC
= Min., I
OL
= 2.1 mA
--
0.4
V
V
IH
Input HIGH Voltage
(1)
2.2
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
(2)
0.2
0.4
V
I
LI
Input Leakage
GND
V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
CC
1
1
A
Notes:
1. V
IH(max.)
= V
CC
+2.0V for pulse width less than 10 ns.
1. V
IL(min.)
= 2.0V for pulse width less than 10 ns.
Integrated Circuit Solution Inc.
5
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
IC62LV1008L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-
55
-
70
-
100
Symbol Parameter
Test Conditions
Min.
Max. Min.
Max. Min.
Max. Unit
I
CC
Vcc Dynamic Operating V
CC
= 3.0V, CE1 = V
IL
,CE2=V
IH
Com. --
30
--
25 --
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
35
--
30 --
25
I
SB
1
TTL Standby Current
V
CC
= Max., f = 0
Com. --
0.2
--
0.2 --
0.2
mA
(TTL Inputs)
CE1
V
IH
or CE2
V
IL
,
Ind.
--
0.3
--
0.3 --
0.3
V
IN
= V
IH
or V
IL
,
I
SB
2
CMOS Standby
V
CC
= Max., f = 0
Com. --
35
--
35 --
35
A
Current (CMOS Inputs)
CE1
V
CC
0.2V
Ind.
--
50
--
50 --
50
or CE2
0.2V,
V
IN
V
CC
0.2V, V
IN
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV1008LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-
55
-
70
-
100
Symbol Parameter
Test Conditions
Min.
Max. Min.
Max. Min.
Max. Unit
I
CC
Vcc Dynamic Operating V
CC
= 3.0V, CE1 = V
IL
,CE2=V
IH
Com. --
30
--
25 --
20
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
35
--
30 --
25
I
SB
1
TTL Standby Current
V
CC
= Max., f = 0
Com. --
0.2
--
0.2 --
0.2
mA
(TTL Inputs)
CE1
V
IH
or CE2
V
IL
,
Ind.
--
0.3
--
0.3 --
0.3
V
IN
= V
IH
or V
IL
,
I
SB
2
CMOS Standby
V
CC
= Max., f = 0
Com. --
20
--
20 --
20
A
Current (CMOS Inputs)
CE1
V
CC
0.2V
Ind.
--
25
--
25 --
25
or CE2
0.2V,
V
IN
V
CC
0.2V, V
IN
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-55
-70
-100
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
55
--
70
--
100
--
ns
t
AA
Address Access Time
--
55
--
70
--
100
ns
t
OHA
Output Hold Time
10
--
10
--
15
--
ns
t
ACE
1
CE1 Access Time
--
55
--
70
--
100
ns
t
ACE
2
CE2 Access Time
--
55
--
70
--
100
ns
t
DOE
OE
Access Time
--
30
--
35
--
50
ns
t
LZOE
(2)
OE
to Low-Z Output
5
--
5
--
5
--
ns
t
HZOE
(2)
OE
to High-Z Output
--
20
0
25
0
30
ns
t
LZCE
1
(2)
CE1 to Low-Z Output
10
--
10
--
10
--
ns
t
LZCE
2
(2)
CE2 to Low-Z Output
10
--
10
--
10
--
ns
t
HZCE
(2)
CE1 or CE2 to Low-Z Output
0
20
0
25
0
30
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output
loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Times
5 ns
Input Reference Level
1.3V
Output Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
5 pF
Including
jig and
scope
OUTPUT
1 TTL
100 pF
Including
jig and
scope
OUTPUT
1 TTL
Integrated Circuit Solution Inc.
7
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
AC TEST LOADS
READ CYCLE NO.1
(1,2)
(Address controlled, CE1 =
OE
OE
OE
OE
OE = V
IL
, CE2 = V
IH
)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
, CE1 = V
IL
,
CE2
= V
IH
.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(CE1,
OE
OE
OE
OE
OE, CE2 controlled)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCE
ADDRESS
OE
CE1
CE2
DOUT
8
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
-55
-70
-100
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max
Unit
t
WC
Write Cycle Time
55
--
70
--
100
--
ns
t
SCE
1
CE1
to Write End
50
--
65
--
80
--
ns
t
SCE
2
CE2 to Write End
50
--
65
--
80
--
ns
t
AW
Address Setup Time to Write End
50
--
65
--
80
--
ns
t
HA
Address Hold from Write End
0
--
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
0
--
ns
t
PWE
(4)
WE
Pulse Width
45
--
55
--
80
--
ns
t
SD
Data Setup to Write End
25
--
30
--
40
--
ns
t
HD
Data Hold from Write End
0
--
0
--
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
30
--
30
--
40
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
5
--
5
--
5
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 2.2V and output loading specified in
Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW , CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with
OE
HIGH.
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range, Standard and Low Power)
AC WAVEFORMS
WRITE CYCLE NO. 1
(WE
Controlled)
(1,2)
DATA-IN VALID
DATA UNDEFINED
t
WC
t
SCE1
t
SCE2
t
AW
t
HA
t
PWE
t
HZWE
HIGH-Z
t
LZWE
t
SA
t
SD
t
HD
ADDRESS
CE1
CE2
WE
DOUT
DIN
Integrated Circuit Solution Inc.
9
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
WRITE CYCLE NO. 2
(
CE1
, CE2 Controlled)
(1,2)
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the HIGH-z state if
OE
=V
IH
.
HIGH-Z
DATA UNDEFINED
DATA-IN VALID
t
WC
t
SCE1
t
SA
t
HA
t
SCE2
t
PWE
t
AW
t
HZWE
t
SD
t
HD
t
LZWE
ADDRESS
DIN
CE1
CE2
WE
DOUT
10
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
V
DR
Vcc for Data Retention
See Data Retention Waveform
1.5
3.6
V
I
DR
Data Retention Current
Vcc = 1.5V,
CE1
Vcc 0.2V
Com. (-L)
--
15
A
Com. (-LL)
--
6
A
Ind. (-L)
--
20
A
Ind. (-LL)
--
9
A
t
SDR
Data Retention Setup Time See Data Retention Waveform
0
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
10
--
ns
DATA RETENTION WAVEFORM
(CE1 Controlled)
V
CC
CE1
V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
3.0V
2.2V
Data Retention Mode
Integrated Circuit Solution Inc.
11
LPSR015-0A 1/3/2002
IC62LV1008L
IC62LV1008LL
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns) Order Part No.
Package
55
IC62LV1008L-55B
8*10mm TF-BGA
70
IC62LV1008L-70B
8*10mm TF-BGA
100
IC62LV1008L-100B
8*10mm TF-BGA
Industrial Range:
-
40C to +85C
Speed (ns) Order Part No.
Package
55
IC62LV1008L-55BI
8*10mm TF-BGA
70
IC62LV1008L-70BI
8*10mm TF-BGA
100
IC62LV1008L-100BI
8*10mm TF-BGA
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns) Order Part No.
Package
55
IC62LV1008LL-55B
8*10mm TF-BGA
IC62LV1008LL-55D
know good die
70
IC62LV1008LL-70B
8*10mm TF-BGA
IC62LV1008LL-70D
know good die
100
IC62LV1008LL-100B 8*10mm TF-BGA
IC62LV1008LL-100D know good die
Industrial Range:
-
40C to +85C
Speed (ns) Order Part No.
Package
55
IC62LV1008LL-55BI
8*10mm TF-BGA
IC62LV1008LL-55DI
know good die
70
IC62LV1008LL-70BI
8*10mm TF-BGA
IC62LV1008LL-70DI
know good die
100
IC62LV1008LL-100BI 8*10mm TF-BGA
IC62LV1008LL-100DI know good die