IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

Document Title

32K x 8 Low Power SRAM with 3.3V

Revision History

Revision No

History

Draft Date

Remark

Initial Draft

October 5,2001

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

FEATURES

· High-speed access time: 15, 20, 25 ns
· Automatic power-down when chip is deselected
· CMOS low power operation

-- 255 mW (max.) operating
-- 0.18 mW (max.) CMOS standby

· TTL compatible interface levels
· Single 3.3V power supply
· Fully static operation: no clock or refresh

required

· Three-state outputs

DESCRIPTION

The

ICSI

IC62LV256L is a very high-speed, low power,

32,768-word by 8-bit static RAM. It is fabricated using

ICSI

high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.

When

is HIGH (deselected), the device assumes a standby

mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.

Easy memory expansion is provided by using an active LOW
Chip Enable (

). The active LOW Write Enable (

) controls

both writing and reading of the memory.

The IC62LV256L is available in the JEDEC standard 28-pin
300mil SOJ and the 8*13.4mm TSOP-1 package.

32K x 8 LOW VOLTAGE
CMOS STATIC RAM

FUNCTIONAL BLOCK DIAGRAM

A0-A14

256 X 1024

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

PIN CONFIGURATION

28-Pin SOJ

22
23
24
25
26
27
28
1
2
3
4
5
6
7

21
20
19
18
17
16
15
14
13
12
11
10

9
8

A11

A9
A8

A13

VCC

A14
A12

A7
A6
A5
A4
A3

A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

A14

A12

I/O0

I/O1

I/O2

GND

VCC

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

PIN CONFIGURATION

8x13.4mm TSOP-1

PIN DESCRIPTIONS

A0-A14

Address Inputs

Chip Enable Input

Output Enable Input

Write Enable Input

I/O0-I/O7

Input/Output

Vcc

Power

GND

Ground

TRUTH TABLE

Mode

I/O Operation

Vcc Current

Not Selected

High-Z

, I

(Power-down)
Output Disabled

High-Z

, I

Read

OUT

, I

Write

, I

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

0.5 to +4.6

BIAS

Temperature Under Bias

55 to +125

°C

STG

Storage Temperature

65 to +150

°C

Power Dissipation

0.5

OUT

DC Output Current (LOW)

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

DC ELECTRICAL CHARACTERISTICS

(Over Operating Range)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Output HIGH Voltage

= Min., I

= 2.0 mA

2.4

Output LOW Voltage

= Min., I

= 4.0 mA

0.4

Input HIGH Voltage

2.2

+ 0.3

Input LOW Voltage

(1)

0.3

0.8

Input Leakage

GND

Com.

µA

Ind.

Output Leakage

GND

OUT

, Outputs Disabled

Com.

µA

Ind.

Notes:

1. V

= 3.0V for pulse width less than 10 ns.

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

CAPACITANCE

(1,2)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: T

= 25°C, f = 1 MHz, Vcc = 3.3V.

POWER SUPPLY CHARACTERISTICS

(1)

(Over Operating Range)

-15 ns

-20 ns -25 ns

Symbol Parameter

Test Conditions

Min. Max.

Unit

Vcc Operating

= Max.,

= V

Com.

-- 50

Supply Current

OUT

= 0 mA, f = 0

Ind.

-- 60

Vcc Dynamic Operating

= Max.,

= V

Com.

-- 50

Supply Current

OUT

= 0 mA, f = f

MAX

Ind.

-- 50

TTL Standby Current

= Max.,

Com.

(TTL Inputs)

= V

or V

Ind.

, f = 0

CMOS Standby

= Max.,

Com.

-- 50

µA

Current (CMOS Inputs)

0.2V,

Ind.

100

-- 100

0.2V, or

0.2V, f = 0

Note:

1. At f = f

MAX

, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.

OPERATING RANGE

Range

Ambient Temperature

Commercial

0°C to +70°C

3.3V +10%

Industrial

40°C to +85°C

3.3V

10%

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

READ CYCLE SWITCHING CHARACTERISTICS

(1)

(Over Operating Range)

-15 ns

-20 ns

-25 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Read Cycle Time

Address Access Time

OHA

Output Hold Time

ACE

Access Time

DOE

Access Time

LZOE

(2)

to Low-Z Output

HZOE

(2)

to High-Z Output

LZCE

(2)

to Low-Z Output

HZCE

(2)

to High-Z Output

(3)

to Power-Up

(3)

to Power-Down

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured

500 mV from steady-state voltage. Not 100% tested.

3. Not 100% tested.

AC TEST LOADS

AC TEST CONDITIONS

Parameter

Unit

Input Pulse Level

0V to 3.0V

Input Rise and Fall Times

3 ns

Input and Output Timing

1.5V

and Reference Levels
Output Load

See Figures 1 and 2

Figure 1.

Figure 2.

635

30 pF

Including

jig and

scope

702

OUTPUT

3.3V

635

5 pF

Including

jig and

scope

702

OUTPUT

3.3V

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

DATA VALID

OHA

OUT

ADDRESS

50%

OHA

DOE

LZOE

ACE

LZCE

HZOE

HIGH-Z

DATA VALID

HZCE

ISB

ADDRESS

OUT

SUPPLY

CURRENT

ICC

READ CYCLE NO. 2

(1,3)

Notes:

is HIGH for a Read Cycle.

2. The device is continuously selected.

= V

3. Address is valid prior to or coincident with

LOW transitions.

AC WAVEFORMS

READ CYCLE NO. 1

(1,2)

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

AC WAVEFORMS

WRITE CYCLE NO. 1 (

WE Controlled)

(1,2)

DATA-IN VALID

DATA UNDEFINED

SCE

PWE

HZWE

HIGH-Z

LZWE

ADDRESS

OUT

WRITE CYCLE SWITCHING CHARACTERISTICS

(1,3)

(Over Operating Range)

-15 ns

-20 ns

-25 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

SCE

to Write End

Address Setup Time to Write End

Address Hold from Write End

Address Setup Time

PWE

(4)

Pulse Width

Data Setup to Write End

Data Hold from Write End

HZWE

(2)

LOW to High-Z Output

LZWE

(2)

HIGH to Low-Z Output

Notes:

1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V

and output loading specified in Figure 1.

2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

4. Tested with

HIGH.

IC62LV256L

Integrated Circuit Solution Inc.

ALSR008-0A 10/5/2001

Notes:

1. The internal write time is defined by the overlap of

LOW and

LOW. All signals must be in valid states to initiate a Write,

but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling

edge of the signal that terminates the Write.

2. I/O will assume the High-Z state if

HIGH-Z

DATA UNDEFINED

DATA-IN VALID

SCE

PWE

HZWE

LZWE

ADDRESS

OUT

WRITE CYCLE NO. 2 (

CE Controlled)

(1,2)

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed (ns)

Order Part No.

Package

IC62LV256L-15T

8*13.4mm TSOP-1

IC62LV256L-15J

300mil SOJ

IC62LV256L-20T

8*13.4mm TSOP-1

IC62LV256L-20J

300mil SOJ

IC62LV256L-25T

8*13.4mm TSOP-1

IC62LV256L-25J

300mil SOJ

ORDERING INFORMATION
Industrial Range: 40°C to +85°C

Speed (ns)

Order Part No.

Package

IC62LV256L-15TI

8*13.4mm TSOP-1

IC62LV256L-15JI

300mil SOJ

IC62LV256L-20TI

8*13.4mm TSOP-1

IC62LV256L-20JI

300mil SOJ

IC62LV256L-25TI

8*13.4mm TSOP-1

IC62LV256L-25JI

300mil SOJ

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