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Электронный компонент: IC62VV51216L-70T

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Integrated Circuit Solution Inc.
1
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
Document Title
512K x 16 bit 1.8V and Ultra Low Power CMOS Static RAM
Revision History
Revision No
History
Draft Date
Remark
0A
Initial Draft
November 2,2001 Preliminary
0B
1.Remove the 55ns products
September 2,2002
2.Change for I
CC
1: 15mA to 20mA for 70ns Industrial product
10mA to 12mA for 100ns commercial product
10mA to 15mA for 100ns Industrial product
3.Change for I
CC
2: 2mA to 2.5mA
4.Change for I
SB
2: 20A to 25A for Industrial product
5.Change for V
DR
Min:1.0V to 1.2V
6.Cgange for I
DR
: 10A to 20A for commerical /L product
6A to 13A for commerical/LL product
15A to 30A for industrial/L product
8A to 23A for Industrial/LL product
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
2
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. Copyright 2000, Integrated Circuit Solution Inc.
DESCRIPTION
The
ICSI
IC62VV51216L and IC62VV51216LL are low-power,
8.388,608 bit static RAMs organized as 524,288 words by 16
bits. They are fabricated using
ICSI
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When CE1 is HIGH or CE2 is Low (deselected) or both
LB
and
UB
are HIGH, the device assumes a standby mode at which
the power dissipation can be reduced by using CMOS input
levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and
OE
. The active LOW
Write Enable (
WE
) controls both writing and reading of the
memory. A data byte allows Upper Byte (
UB
) and Lower Byte
(
LB
) access.
The IC62VV51216L and IC62VV51216LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
512K x 16
1.8V ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
High-speed access times: 70, 100 ns
CMOS low power operation
-- 20 mW (typical) operating
-- 5 W (typical) CMOS standby
TTL compatible interface levels
Single 1.65V-2.2V Vcc power supply
Fully static operation: no clock or refresh re-
quired
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the know good die form 44-pin
TSOP-2 and 48-pin 8*10mm TF-BGA
A0-A18
CE2
OE
WE
512K x 16
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
CE1
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
UB
LB
Integrated Circuit Solution Inc.
3
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
TRUTH TABLE
I/O PIN
Mode
WE
WE
WE
WE
WE
CE1
CE2
22
2
2
OE
OE
OE
OE
OE
LB
LB
LB
LB
LB
UB
UB
UB
UB
UB
I/O0/-I/O7
I/O8-I/O15
Power
Not Selected
X
H
X
X
X
X
High-Z
High-Z
Standby
X
X
L
X
X
X
High-Z
High-Z
Standby
X
X
X
X
H
H
High-Z
High-Z
Standby
Output Disabled H
L
H
H
L
X
High-Z
High-Z
Active
H
L
H
H
X
L
High-Z
High-Z
Active
Read
H
L
H
L
L
H
D
OUT
High-Z
Active
H
L
H
L
H
L
High-Z
D
OUT
Active
H
L
H
L
L
L
D
OUT
D
OUT
Active
Write
L
L
H
X
L
H
D
IN
High-Z
Active
L
L
H
X
H
L
High-Z
D
IN
Active
L
L
H
X
L
L
D
IN
D
IN
Active
48-Pin TF-BGA (TOP Veiw)
PIN CONFIGURATIONS
44-Pin TSOP-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A4
A3
A2
A1
A0
CE1
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A18
A17
A16
A15
A14
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
A8
A9
A10
A11
A12
A13
1 2 3 4 5 6
A
B
C
D
E
F
G
H
LB
OE
A0
A1
A2
CE2
I/O
8
UB
A3
A4
CE1
I/O
0
I/O
9
I/O
10
A5
A6
I/O
1
I/O
2
GND
I/O
11
A17
A7
I/O
3
Vcc
Vcc
I/O
12
NC
A16
I/O
4
GND
I/O
14
I/O
13
A14
A15
I/O
5
I/O
6
I/O
15
NC
A12
A13
WE
I/O
7
A18
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A18
Address Inputs
I/O0-I/O15
Data Input/Output
CE1
Chip Enable1 Input
CE2
Chip Enable2 Input, BGA only
OE
Output Enable Input
WE
Write Enable Input
LB
Lower-byte Control (l/O0-I/O7)
UB
Upper-byte Control (l/O8-I/O15)
NC
No Connection
Vcc
Power
GND
Ground
4
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Parameter
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
0.5 to Vcc + 0.4
V
T
BIAS
Temperature Under Bias
40 to +85
C
V
CC
Vcc related to GND
0.3 to +2.4
V
T
STG
Storage Temperature
65 to +150
C
P
T
Power Dissipation
1.0
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
V
OH
Output HIGH Voltage
I
OH
= 0.1 mA
1.4
--
V
V
OL
Output LOW Voltage
I
OL
= 0.1 mA
--
0.2
V
V
IH
(1)
Input HIGH Voltage
1.4
V
CC
+ 0.2
V
V
IL
(2)
Input LOW Voltage
(1)
0.2
0.4
V
I
LI
Input Leakage
GND
V
IN
V
CC
1
1
A
I
LO
Output Leakage
GND
V
OUT
V
CC
, O
UTPUTS
D
ISABLED
1
1
A
Notes:
1. V
IH
(max.) = Vcc + 0.2V for pulse width less than 10ns.
2. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
OPERATING RANGE
Range
Ambient Temperature
V
CC
Commercial
0C to +70C
1.65V- 2.2V
Industrial
40C to +85C
1.65V - 2.2V
Integrated Circuit Solution Inc.
5
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
IC62VV51216L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-70
-100
Symbol Parameter
Test Conditions
Min. Max.
Min.Max.
Unit
I
CC
1
Vcc Dynamic Operating V
CC
= 1.8V
Com.
--
15
--
12
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
20
--
15
I
CC
2
Vcc Dynamic Operating V
CC
= 1.8V
Com.
--
2.5
--
2.5
mA
Supply Current
I
OUT
= 0 mA, f = 1 MHz
Ind.
--
2.5
--
2.5
I
SB
2
CMOS Standby
V
CC
= Max., other input=0-V
CC
Com.
--
35
--
35
A
Current (CMOS Inputs)
1)
CE
1
V
CC
0.2V,
Ind.
--
50
--
50
(CE1 controlled) or
2) 0V
CE2
0.2V (CE2 controlled) or
3)
LB
/
UB
V
CC
0.2 (
LB
/
UB
controlled)
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter
Unit
Input Pulse Level
0.4V to 1.4V
Input Rise and Fall Times
5 ns
Input Reference Level
0.9V
Output Reference Level
0.9V
Output Load
See Figures 1 and 2
AC TEST LOADS
Figure 1
Figure 2
5 pF
Including
jig and
scope
OUTPUT
1 TTL
100 pF or 30 pF(for 55ns)
Including
jig and
scope
OUTPUT
1 TTL
6
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-70
-100
Symbol Parameter
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
70
--
100
--
ns
t
AA
Address Access Time
--
70
--
100
ns
t
OHA
Output Hold Time
10
--
15
--
ns
t
ACE
CE1 Low and CE2 HIGH Access Time
--
70
--
100
ns
t
DOE
OE
Access Time
--
35
--
50
ns
t
HZOE
(2)
OE
to High-Z Output
--
25
--
30
ns
t
LZOE
(2)
OE
to Low-Z Output
5
--
5
--
ns
t
HZCE
(2)
CE1 HIGH or CE2 LOW to High-Z Output
0
25
0
30
ns
t
LZCE
(2)
CE1 Low and CE2 HIGH to Low-Z Output
10
--
10
--
ns
t
BA
LB, UB
Access Time
--
70
--
100
ns
t
HZB
LB, UB
o High-Z Output
0
25
0
30
ns
t
LZB
LB. UB
to Low-Z Output
0
--
0
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels
of 0.4V to 1.4V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
IC62VV51216LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-70
-100
Symbol Parameter
Test Conditions
Min.Max.
Min.Max.
Unit
I
CC
1
Vcc Dynamic Operating V
CC
= 1.8V,
Com.
--
15
--
12
mA
Supply Current
I
OUT
= 0 mA, f = f
MAX
Ind.
--
20
--
15
I
CC
2
Vcc Dynamic Operating V
CC
= 1.8V
Com.
--
2.5
--
2.5
mA
Supply Current
I
OUT
= 0 mA, f = 1 MHz
Ind.
--
2.5
--
2.5
I
SB
2
CMOS Standby
V
CC
= Max., other input=0-V
CC
Com.
--
15
--
15
A
Current (CMOS Inputs)
1)
CE1
V
CC
0.2V,
Ind.
--
25
--
25
(
CE
1 controlled) or
2) 0V
CE2
0.2V (CE2 controlled) or
3)
LB
/
UB
V
CC
0.2 (
LB
/
UB
controlled)
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
7
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE
t
LZCE
t
HZOE
HIGH-Z
DATA VALID
t
HZB
ADDRESS
OE
CE1
LB, UB
D
OUT
CE2
t
HZCE
t
BA
t
LZB
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE
, CE1
,
UB
, or
LB
= V
IL
, CE2 = V
IH
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(
OE,
Controlled
)
AC TEST LOADS
READ CYCLE NO.1
(1,2)
(Address Controlled) (
CE1
= OE
= V
IL
, CE2
= V
IH
,
UB
or
LB
= V
IL
)
DATA VALID
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
D
OUT
ADDRESS
8
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-70
-100
Symbol Parameter
Min.
Max.
Min.
Max
Unit
t
WC
Write Cycle Time
70
--
100
--
ns
t
SCE
CE1 Low and CE2 HIGH to Write End
65
--
80
--
ns
t
AW
Address Setup Time to Write End
65
--
80
--
ns
t
HA
Address Hold from Write End
0
--
0
--
ns
t
SA
Address Setup Time
0
--
0
--
ns
t
PWB
LB, UB
Valid to End of Write
60
--
80
--
ns
t
PWE
WE
Pulse Width
55
--
80
--
ns
t
SD
Data Setup to Write End
30
--
40
--
ns
t
HD
Data Hold from Write End
0
--
0
--
ns
t
HZWE
(3)
WE
LOW to High-Z Output
--
30
--
40
ns
t
LZWE
(3)
WE
HIGH to Low-Z Output
5
--
5
--
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE1 LOW, and
UB
or
LB
,
WE
LOW, and CE2 HIGH All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE1
UB, LB
WE
D
OUT
D
IN
CE2
DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE1 or CE2
,
Controlled
, OE
= HIGH or LOW
)
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the
WE
, CE1 = V
IL
, CE2 = V
IH
and at least one of the
LB
and
UB
inputs being in the LOW state.
Integrated Circuit Solution Inc.
9
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
WRITE CYCLE NO. 2
(
WE
Controlled;
OE
is HIGH During Write Cycle)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
PWE
t
AW
t
SCE
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE1
UB, LB
WE
D
OUT
D
IN
CE2
OE
DATA
IN
VALID
t
LZWE
t
SD
WRITE CYCLE NO. 3
(
WE
Controlled;
OE
is LOW During Write Cycle)
DATA UNDEFINED
t
SCE
VALID ADDRESS
LOW
t
PWE
t
AW
t
HA
HIGH-Z
t
PBW
t
HD
t
SA
t
HZWE
ADDRESS
CE1
UB, LB
WE
D
OUT
D
IN
CE2
OE
DATA
IN
VALID
t
LZWE
t
SD
t
WC
10
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
Min.
Max.
Unit
V
DR
Vcc for Data Retention
See Data Retention Waveform
1.2
2.2
V
I
DR
Data Retention Current
V
CC
= 1.2V, CE1
V
CC
0.2V
(1)
Com. (-L)
--
20
A
Com. (-LL)
--
13
Ind. (-L)
--
30
Ind. (-LL)
--
23
t
SDR
Data Retention Setup Time See Data Retention Waveform
0
--
ns
t
RDR
Recovery Time
See Data Retention Waveform
10
--
ns
WRITE CYCLE NO. 4
(
UB
/
LB
Controlled)
DATA UNDEFINED
t
WC
ADDRESS 1
ADDRESS 2
t
WC
HIGH-Z
t
PBW
WORD 1
WORD 2
t
HD
t
SA
t
HZWE
ADDRESS
CE1
UB, LB
WE
D
OUT
D
IN
CE2
OE
DATA
IN
VALID
t
LZWE
t
SD
t
PBW
DATA
IN
VALID
t
SD
t
HD
t
SA
t
HA
t
HA
Notes:
1.1) CE1
V
CC
-0.2V, (
CE
1 controlled) or
2) 0V
CE2
0.2V (CE2 controlled) or
3)
LB
=
UB
V
CC
-0.2V, CE2
V
CC
-0.2V (
LB
/
UB
controlled)
Integrated Circuit Solution Inc.
11
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
DATA RETENTION WAVEFORM
(CE1 Controlled)
V
CC
CE1
V
CC
- 0.2V
t
SDR
t
RDR
V
DR
CE1
GND
1.65V
1.4V
Data Retention Mode
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns) Order Part No.
Package
70
IC62VV51216L-70T
TSOP-2
IC62VV51216L-70B
8*10mm TF-BGA
100
IC62VV51216L-100T
TSOP-2
IC62VV51216L-100B
8*10mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No.
Package
70
IC62VV51216L-70TI
TSOP-2
IC62VV51216L-70BI
8*10mm TF-BGA
100
IC62VV51216L-100TI
TSOP-2
IC62VV51216L-100BI
8*10mm TF-BGA
ORDERING INFORMATION
Commercial Range: 0C to +70C
Speed (ns) Order Part No.
Package
70
IC62VV51216LL-70T
TSOP-2
IC62VV51216LL-70B
8*10mm TF-BGA
100
IC62VV51216LL-100T
TSOP-2
IC62VV51216LL-100B
8*10mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No.
Package
70
IC62VV51216LL-70TI
TSOP-2
IC62VV51216LL-70BI
8*10mm TF-BGA
100
IC62VV51216LL-100TI
TSOP-2
IC62VV51216LL-100BI
8*10mm TF-BGA
12
Integrated Circuit Solution Inc.
LPSR018-0B 9/02/2002
IC62VV51216L
IC62VV51216LL
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5
TH
ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw