Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

IC80C51
IC80C31

CMOS SINGLE CHIP
8-BIT MICROCONTROLLER

FEATURES

· 80C51 based architecture

· 4K x 8 ROM (IC80C51 only)

· 128 x 8 RAM

· Two 16-bit Timer/Counters

· Full duplex serial channel

· Boolean processor

· Four 8-bit I/O ports, 32 I/O lines

· Memory addressing capability

64K ROM and 64K RAM

· Program memory lock

Encrypted verify (32 bytes)
Lock bits (2)

· Power save modes:

Idle and power-down

· Six interrupt sources

· Most instructions execute in 0.3 µs

· CMOS and TTL compatible

· Maximum speed: 40 MHz @ Vcc = 5V

· Packages available:

40-pin DIP
44-pin PLCC
44-pin PQFP

GENERAL DESCRIPTION

The

ICSI

IC80C51 and IC80C31 are high-performance

microcontroller fabricated using high-density CMOS
technology. The CMOS IC80C51/31 is functionally
compatible with the industry standard 80C51/31
microcontrollers.

The IC80C51/31 is designed with 4K x 8 ROM (IC80C51
only); 128 x 8 RAM; 32 programmable I/O lines; a serial I/
O port for either multiprocessor communications, I/O
expansion or full duplex UART; two 16-bit timer/counters;
an six-source, two-priority-level, nested interrupt structure;
and an on-chip oscillator and clock circuit. The IC80C51/31
can be expanded using standard TTL compatible memory.

Figure 1. IC80C51/31 Pin Configuration: 40-pin DIP

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

GND

VCC

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

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MC001-0B

IC80C51
IC80C31

Table 1. Detailed Pin Description

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

ALE

I/O

Address Latch Enable: Output pulse for latching the low byte
of the address during an access to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.

External Access enable:

EA must be externally held low to

enable the device to fetch code from external program memory
locations 0000H to FFFFH. If

EA is held high, the device

executes from internal program memory unless the program
counter contains an address greater than internal ROM seze.

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.

P1.0-P1.7

1-8

2-9

40-44

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal

1-3

pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). The Port 1

output buffers can sink/source four TTL inputs.

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
2 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). Port 2 emits

the high order address byte during fetches from external pro-
gram memory and during accesses to external data memory
that used 16-bit addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pullups when emitting 1s. During
accesses to external data memory that use 8-bit addresses
(MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2
Special Function Registers.

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IC80C31

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Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

P3.0-P3.7

10-17

11, 13-19

5, 7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

Port 3 also serves the special features of the IC80C51/31, as
listed below:

RxD (P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0

INT0 (P3.2): External interrupt 0.

INT1

INT1 (P3.3): External interrupt 1.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

PSEN

Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory,

PSEN is activated twice each machine cycle

except that two

PSEN activations are skipped during each

access to external data memory.

PSEN is not activated during

fetches from internal program memory.

RST

Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external capaci-
tor connected to Vcc.

XTAL 1

Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.

XTAL 2

Crystal 2: Output from the inverting oscillator amplifier.

GND

Ground: 0V reference.

Vcc

Power Supply: This is the power supply voltage for operation.

Table 1. Detailed Pin Description (continued)

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MC001-0B

IC80C51
IC80C31

OPERATING DESCRIPTION

The detail description of the IC80C51 included in this
description are:

· Memory Map and Registers

· Timer/Counters

· Serial Interface

· Interrupt System

· Other Information

MEMORY MAP AND REGISTERS

Memory

The IC80C51/31 has separate address spaces for program
and data memory. The program and data memory can be up
to 64K bytes long. The lower 4K program memory can
reside on-chip.(IC80C51 only) Figure 5 shows a map of the
IC80C51/31 program and data memory.

The IC80C51/31 has 128 bytes of on-chip RAM, plus
numbers of special function registers. The 128 bytes can be
accessed either by direct addressing or by indirect

addressing. Figure 6 shows internal data memory
organization and SFR Memory Map.

The lower 128 bytes of RAM can be divided into three
segments as listed below and shown in Figure 7.

1. Register Banks 0-3: locations 00H through 1FH (32

bytes). The device after reset defaults to register bank
0. To use the other register banks, the user must select
them in software. Each register bank contains eight
1-byte registers R0-R7. Reset initializes the stack
point to location 07H, and is incremented once to start
from 08H, which is the first register of the second
register bank.

2. Bit Addressable Area: 16 bytes have been assigned

for this segment 20H-2FH. Each one of the 128 bits of
this segment can be directly addressed (0-7FH). Each
of the 16 bytes in this segment can also be addressed
as a byte.

3. Scratch Pad Area: 30H-7FH are available to the user

as data RAM. However, if the data pointer has been
initialized to this area, enough bytes should be left
aside to prevent SP data destruction.

FFFFH:

64K

0FFFH:

Program Memory

(Read Only)

Data Memory

(Read/Write)

EA = 0

External

PSEN

EA = 1

Internal

0000

FFFFH

Internal

FFH

80H

7FH

0000

RD WR

Figure 5. IC80C51/31 Program and Data Memory Structure

IC80C51
IC80C31

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Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for
Accumulator-specific instructions, however, refer to the
Accumulator simply as A.

B Register (B)
The B register is used during multiply and divide operations.
For other instructions it can be treated as another scratch
pad register.

Program Status Word (PSW). The PSW register contains
program status information.

Figure 6. Internal Data Memory and SFR Memory Map

Figure 7. Lower 128 Bytes of Internal RAM

...7F

0 ...

BANK3

BANK2

BANK 1

BANK 0

8 BYTES

BANKS

BIT

ADDRESSABLE

SEGMENT

SCRATCH

PAD

AREA

Accessible

by Direct

Addressing

Not Available

IC80C51/31

Accessible

by Direct

and Indirect

Addressing

80H

7FH

FFH

80H

Upper

128

Lower

128

Special

Function

Registers

Ports,
Status and
Control Bits,
Timer,
Registers,
Stack Pointer,
Accumulator
(Etc.)

ACC

PSW

SCON

TCON

Bit

Addressable

F8
F0
E8
E0

D8
D0
C8
C0
B8
B0
A8
A0

98
90
88
80

FF
F7
EF
E7

DF
D7
CF
C7
BF

B7
AF
A7
9F

97
8F
87

SBUF

TMOD

TL0

DPL

TL1

DPH

TH0

TH1

PCON

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFR's) are located in
upper 128 Bytes direct addressing area. The SFR Memory
Map in Figure 6 shows that.

Not all of the addresses are occupied. Unoccupied
addresses are not implemented on the chip. Read accesses
to these addresses in general return random data, and
write accesses have no effect.

User software should not write 1s to these unimplemented
locations, since they may be used in future microcontrollers
to invoke new features. In that case, the reset or inactive
values of the new bits will always be 0, and their active
values will be 1.

The functions of the SFRs are outlined in the following
sections, and detailed in Table 2.

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IC80C51
IC80C31

initiates the transmission.) When data is moved from
SBUF, it comes from the receive buffer.

Timer Registers
Register pairs (TH0, TL0) and (TH1, TL1),are the 16-bit
Counter registers for Timer/Counters 0,1 and 2, respectively.

Control Registers
Special Function Registers IP, IE, TMOD, TCON, T2CON,
SCON, and PCON contain control and status bits for the
interrupt system, the Timer/Counters, and the serial port.
They are described in later sections of this chapter.

SPECIAL FUNCTION REGISTERS

(Continued)

Stack Pointer (SP)
The Stack Pointer Register is eight bits wide. It is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-
chip RAM, the Stack Pointer is initialized to 07H after a
reset. This causes the stack to begin at location 08H.

Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low
byte (DPL). Its function is to hold a 16-bit address. It may
be manipulated as a 16-bit register or as two independent
8-bit registers.

Ports 0 To 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and
3, respectively.

Serial Data Buffer (SBUF)
The Serial Data Buffer is actually two separate registers, a
transmit buffer and a receive buffer register. When data is
moved to SBUF, it goes to the transmit buffer, where it is
held for serial transmission. (Moving a byte to SBUF

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IC80C31

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MC001-0B

Table 2. Special Function Registers

Symbol

Description

Direct Address

Bit Address, Symbol, or Alternative Port Function

Reset Value

ACC

(1)

Accumulator

E0H

00H

(1)

B register

F0H

00H

DPH

Data pointer (DPTR) high

83H

00H

DPL

Data pointer (DPTR) low

82H

00H

(1)

Interrupt enable

A8H

ET1

EX1

ET0

EX0

0XX00000B

(1)

Interrupt priority

B8H

PT1

PX1

PT0

PX0

XXX00000B

(1)

Port 0

80H

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2 P0.1 P0.0

FFH

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

(1)

Port 1

90H

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2 P1.1 P1.0

FFH

(1)

Port 2

A0H

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2 P2.1 P2.0

FFH

AD15 AD14

AD13 AD12 AD11 AD10 AD9

AD8

(1)

Port 3

B0H

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2 P3.1 P3.0

FFH

INT1 INT0 TXD RXD

PCON

Power control

87H

SMOD

GF1

GF0

IDL

0XXX0000B

PSW

(1)

Program status word

D0H

RS1

RS0

00H

SBUF

Serial data buffer

99H

XXXXXXXXB

SCON

(1)

Serial controller

98H

SM0

SM1

SM2

REN

TB8

RB8

00H

Stack pointer

81H

07H

TCON

(1)

Timer control

88H

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00H

TMOD

Timer mode

89H

GATE

00H

TH0

Timer high 0

8CH

00H

TH1

Timer high 1

8DH

00H

TL0

Timer low 0

8AH

00H

TL1

Timer low 1

8BH

00H

Notes:

1. Denotes bit addressable.

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IC80C51
IC80C31

The detail description of each bit is as follows:

PSW:

Program Status Word. Bit Addressable.

RS1

RS0

Register Description:

PSW.7

Carry flag.

PSW.6

Auxiliary carry flag.

PSW.5

Flag 0 available to the user for
general purpose.

RS1

PSW.4

(1)

RS0

PSW.3

(1)

PSW.2

Overflow flag.

PSW.1

Usable as a general purpose flag

PSW.0

Parity flag. Set/Clear by hardware each

instruction cycle to indicate an odd/even
number of "1" bits in the accumulator.

Note:
1. The value presented by RS0 and RS1 selects the corre-

sponding register bank.

RS1

RS0

Register Bank

Address

00H-07H

08H-0FH

10H-17H

18H-1FH

PCON:

Power Control Register. Not Bit Addressable.

SMOD

GF1

GF0

IDL

Register

Description:

SMOD

Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.

Not implemented, reserve for future use.

(1)

Not implemented, reserve for future use.

(1)

Not implemented, reserve for future use.

(1)

GF1

General purpose flag bit.

GF0

General purpose flag bit.

Power-down bit. Setting this bit activates power-
down mode.

IDL

Idle mode bit. Setting this bit activates idle mode.
operation in the IC80C51/31. If 1s are written to
PD and IDL at the same time, PD takes precedence.

Note:

1. User software should not write 1s to reserved bits. These

bits may be used in future products to invoke new features.

IE:

Interrupt Enable Register. Bit Addressable.

ET1

EX1

ET0 EX0

Register Description:

IE.7

Disable all interrupts. If EA=0, no interrupt
will be acknowledged. If EA=1, each
interrupt source is individually enabled
or disabled by setting or clearing its
enable bit.

IE.6

Not implemented, reserve for future use.

(5)

IE.5

Not implemented, reserve for future use.

(5)

IE.4

Enable or disable the serial port interrupt.

ET1

IE.3

Enable or disable the Timer 1 overflow
interrupt.

EX1

IE.2

Enable or disable External Interrupt 1.

ET0

IE.1

Enable or disable the Timer 0 overflow
interrupt.

EX0

IE.0

Enable or disable External Interrupt 0.

Note: To use any of the interrupts in the 80C51 Family, the

following three steps must be taken:

1. Set the

EA (enable all) bit in the IE register to 1.

2. Set the coresponding individual interrupt enable bit in

the IE register to 1.

3. Begin the interrupt service routine at the corresponding

Vector Address of that interrupt (see below).

Interrupt Source

Vector Address

IE0

0003H

TF0

000BH

IE1

0013H

TF1

001BH

RI & TI

0023H

4. In addition, for external interrupts, pins

INT0 and INT1

(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition activated,
bits IT0 or IT1 in the TCON register may need to be set to
0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated

5. User software should not write 1s to reserved bits. These

bits may be used in future products to invoke new features.

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IC80C31

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IP:

Interrupt Priority Register. Bit Addressable.

PT1

PX1

PT0 PX0

Register Description:

IP.7

Not implemented, reserve for future use

(3)

IP.6

Not implemented, reserve for future use

(3)

IP.5

Not implemented, reserve for future use

(3)

IP.4

Defines Serial Port interrupt priority level

PT1

IP.3

Defines Timer 1 interrupt priority level

PX1

IP.2

Defines External Interrupt 1 priority level

PT0

IP.1

Defines Timer 0 interrupt priority level

PX0

IP.0

Defines External Interrupt 0 priority level

Notes:
1. In order to assign higher priority to an interrupt the

coresponding bit in the IP register must be set to 1. While
an interrupt service is in progress, it cannot be inter-
rupted by a lower or same level interrupt.

2. Priority within level is only to resolve simultaneous

requests of the same priority level. From high-to-low,
interrupt sources are listed below:

IE0
TF0
IE1
TF1
RI or TI

3. User software should not write 1s to reserved bits. These

bits may be used in future products to invoke new features.

TCON:

Timer/Counter Control Register. Bit Addressable

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Register Description:

TF1

TCON.7

Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.

TR1

TCON.6

Timer 1 run control bit. Set/Cleared by

software to turn Timer/Counter 1 ON/
OFF.

TF0

TCON.5

Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.

TR0

TCON.4

Timer 0 run control bit. Set/Cleared by

software to turn Timer/Counter 0 ON/
OFF.

IE1

TCON.3

External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.

IT1

TCON.2

Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.

IE0

TCON.1

External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.

IT0

TCON.0

Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.

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IC80C31

TMOD:

Timer/Counter Mode Control Register.
Not Bit Addressable.

Timer 1

Timer 0

GATE C/

TT
TT
T M1 M0

GATE

TT
TT
T M1 M0

GATE When TRx (in TCON) is set and GATE=1, TIMER/

COUNTERx will run only while

INTx pin is high

(hardware control). When GATE=0, TIMER/
COUNTERx will run only while TRx=1 (software
control).

Timer or Counter selector. Cleared for Timer

operation (input from internal system clock). Set
for Counter operation (input from Tx input pin).

Mode selector bit.

(1)

Mode selector bit.

(1)

Note 1:

Operating Mode

Mode 0. (13-bit Timer)

Mode 1. (16-bit Timer/Counter)

Mode 2. (8-bit auto-load Timer/Counter)

Mode 3. (Splits Timer 0 into TL0 and
TH0. TL0 is an 8-bit Timer/Counter
controller by the standard Timer 0
control bits. TH0 is an 8-bit Timer and
is controlled by Timer 1 control bits.)

Mode 3. (Timer/Counter 1 stopped).

SCON:

Serial Port Control Register. Bit Addressable.

SM0 SM1 SM2

REN

TB8

RB8

Register Description:

SM0

SCON.7

Serial port mode specifier.

(1)

SM1

SCON.6

Serial port mode specifier.

(1)

SM2

SCON.5

Enable the multiprocessor com-
munication feature in mode 2 and 3. In
mode 2 or 3, if SM2 is set to 1 then RI
will not be activated if the received 9th
data bit (RB8) is 0. In mode 1, if SM2=1
then RI will not be activated if valid stop
bit was not received. In mode 0, SM2
should be 0.

REN SCON.4

Set/Cleared by software to Enable/
Disable reception.

TB8

SCON.3

The 9th bit that will be transmitted in
mode 2 and 3. Set/Cleared by software.

RB8

SCON.2

In modes 2 and 3, RB8 is the 9th data
bit that was received. In mode 1, if
SM2=0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.

SCON.1

Transmit interrupt flag. Set by hardware
at the end of the eighth bit time in mode
0, or at the beginning of the stop bit in
the other modes. Must be cleared by
software.

SCON.0

Receive interrupt flag. Set by hardware

at the end of the eighth bit time in mode
0, or halfway through the stop bit time
in the other modes (except see SM2).
Must be cleared by software.

Note : UART Operating Modes

SM0 SM1 MODE

Description

Baud Rate

Shift register

Fosc/12

8-bit UART

Variable

9-bit UART

Fosc/64 or
Fosc/32

9-bit UART

Variable

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IC80C31

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TIMER/COUNTERS

The IC80C51/31 has two 16-bit Timer/Counter registers:
Timer 0,Timer 1. All two can be configured to operate either
as Timers or event Counters.

As a Timer, the register is incremented every machine
cycle. Thus, the register counts machine cycles. Since a
machine cycle consists of 12 oscillator periods, the count
rate is 1/12 of the oscillator frequency.

As a Counter, the register is incremented in response to a
1-to-0 transition at its corresponding external input pin, T0
and T1. The external input is sampled during S5P2 of every
machine cycle. When the samples show a high in one cycle
and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required
to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. There are no restrictions on
the duty cycle of the external input signal, but it should be
held for at least one full machine cycle to ensure that a
given level is sampled at least once before it changes.

In addition to the Timer or Counter functions, Timer 0 and
Timer 1 have four operating modes: 13-bit timer, 16-bit
timer, 8-bit auto-reload, split timer.

Timer 0 and Timer 1

Timer/Counters 0 and 1 are present in both the IC80C51/
31 and IC80C52/32.The Timer or Counter function is
selected by control bits C/

T in the Special Function Regiser

TMOD. These two Timer/Counters have four operating
modes, which are selected by bit pairs (M1, M0) in TMOD.
Modes 0, 1, and 2 are the same for both Timer/Counters,
but Mode 3 is different. The four modes are described in the
following sections.

Mode 0:
Both Timers in Mode 0 are 8-bit Counters with a divide-by-
32 prescaler. Figure 8 shows the Mode 0 operation as it
applies to Timer 1.

In this mode, the Timer register is configured as a 13-bit
register. As the count rolls over from all 1s to all 0s, it sets
the Timer interrupt flag TF1. The counted input is enabled
to the Timer when TR1 = 1 and either GATE = 0 or

INT1 =

1. Setting GATE = 1 allows the Timer to be controlled by
external input

INT1, to facilitate pulse width measurements.

TR1 is a control bit in the Special Function Register TCON.
Gate is in TMOD.

The 13-bit register consists of all eight bits of TH1 and the
lower five bits of TL1. The upper three bits of TL1 are
indeterminate and should be ignored. Setting the run flag
(TR1) does not clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1,
except that TR0, TF0 and

INT0 replace the corresponding

Timer 1 signals in Figure 8. There are two different GATE
bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.
3).

DIVIDE 12

OSC

(XTAL2)

TL1

(5 BITS)

TH1

(8 BITS)

TF1

CONTROL

C/T = 0

C/T = 1

GATE

INT1 PIN

TR1

T1 PIN

INTERRUPT

ONE MACHINE

CYCLE

ONE MACHINE

CYCLE

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

P1 P2

Figure 8. Timer/Counter 1 Mode 0: 13-Bit Counter

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

DIVIDE 12

OSC

TL1

(8 BITS)

TH1

(8 BITS)

TF1

CONTROL

RELOAD

C/T = 0

C/T = 1

GATE

INT0 PIN

TR1

T1 PIN

INTERRUPT

Mode 1:
Mode 1 is the same as Mode 0, except that the Timer
register is run with all 16 bits. The clock is applied to the
combined high and low timer registers (TL1/TH1). As
clock pulses are received, the timer counts up: 0000H,
0001H, 0002H, etc. An overflow occurs on the FFFFH-to-
0000H overflow flag. The timer continues to count. The
overflow flag is the TF1 bit in TCON that is read or written
by software (see Figure 9).

Mode 2:
Mode 2 configures the Timer register as an 8-bit Counter
(TL1) with automatic reload, as shown in Figure 9. Overflow
from TL1 not only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset by software. The reload
leaves the TH1 unchanged. Mode 2 operation is the same
for Timer/Counter 0.

Mode 3:
Timer 1 in Mode 3 simply holds its count. The effect is the
same as setting TR1 = 0. Timer 0 in Mode 3 establishes
TL0 and TH0 as two separate counters. The logic for Mode
3 on Timer 0 is shown in Figure 11. TL0 uses the Timer 0
control bits: C/

T, GATE, TR0, INT0, and TF0. TH0 is

locked into a timer function (counting machine cycles) and
over the use of TR1 and TF1 from Timer 1. Thus, TH0 now
controls the Timer 1 interrupt.

Mode 3 is for applications requiring an extra 8-bit timer or
counter. With Timer 0 in Mode 3, the IC80C51 can appear
to have three Timer/Counters. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of and
into its own Mode 3. In this case, Timer 1 can still be used
by the serial port as a baud rate generator or in any
application not requiring an interrupt.

Figure 9. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload

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IC80C51
IC80C31

Table 5. Timer/Counter 1 Used as a Timer

TMOD

Mode

Timer 1

Internal

External

Function

Control

(1)

Control

(2)

13-Bit Timer

00H

80H

16-Bit Timer

10H

90H

8-Bit Auto-Reload

20H

A0H

Does Not Run

30H

B0H

Table 6. Timer/Counter 1 Used as a Counter

TMOD

Mode

Timer 1

Internal

External

Function

Control

(1)

Control

(2)

13-Bit Timer

40H

C0H

16-Bit Timer

50H

D0H

8-Bit Auto-Reload

60H

E0H

Not Available

Notes:
1. The Timer is turned ON/OFF by setting/clearing bit TR1

in the software.

2. The Timer is turned ON/OFF by the 1-to-0 transition on

INT1 (P3.3) when TR1 = 1 (hardware control).

Timer Setup

Tables 3 through 6 give TMOD values that can be used to
set up Timers in different modes.

It assumes that only one timer is used at a time. If Timers
0 and 1 must run simultaneously in any mode, the value in
TMOD for Timer 0 must be ORed with the value shown for
Timer 1 (Tables 5 and 6).

For example, if Timer 0 must run in Mode 1 GATE (external
control), and Timer 1 must run in Mode 2 COUNTER, then
the value that must be loaded into TMOD is 69H (09H from
Table 3 ORed with 60H from Table 6).

Moreover, it is assumed that the user is not ready at this
point to turn the timers on and will do so at another point in
the program by setting bit TRx (in TCON) to 1.

Table 3. Timer/Counter 0 Used as a Timer

TMOD

Mode

Timer 0

Internal

External

Function

Control

(1)

Control

(2)

13-Bit Timer

00H

08H

16-Bit Timer

01H

09H

8-Bit Auto-Reload

02H

0AH

Two 8-Bit Timers

03H

0BH

Table 4. Timer/Counter 0 Used as a Counter

TMOD

Mode

Timer 0

Internal

External

Function

Control

(1)

Control

(2)

13-Bit Timer

04H

0CH

16-Bit Timer

05H

0DH

8-Bit Auto-Reload

06H

0EH

One 8-Bit Counter

07H

0FH

Notes:
1. The Timer is turned ON/OFF by setting/clearing bit TR0

in the software.

2. The Timer is turned ON/OFF by the 1-to-0 transition on

INT0 (P3.2) when TR0=1 (hardware control)

IC80C51
IC80C31

S3-18

Integrated Circuit Solution Inc.

MC001-0B

SERIAL INTERFACE

The Serial port is full duplex, which means it can transmit
and receive simultaneously. It is also receive-buffered,
which means it can begin receiving a second byte before
a previously received byte has been read from the receive
register. (However, if the first byte still has not been read
when reception of the second byte is complete, one of the
bytes will be lost.) The serial port receive and transmit
registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and
reading SBUF accesses a physically separate receive
register.

The serial port can operate in the following four modes:

Mode 0:
Serial data enters and exits through RXD. TXD outputs the
shift clock. Eight data bits are transmitted/received, with
the LSB first. The baud rate is fixed at 1/12 the oscillator
frequency (see Figure 11).

Mode 1:
Ten bits are transmitted (through TXD) or received (through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable (see
Figure 12).

Mode 2:
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). On transmit,
the ninth data bit (TB8 in SCON) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW) can
be moved into TB8. On receive, the ninth data bit goes into
RB8 in Special Function Register SCON, while the stop bit
is ignored. The baud rate is programmable to either 1/32 or
1/64 the oscillator frequency (see Figure 13).

Mode 3:
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except the
baud rate, which is variable in Mode 3 (see Figure 14).

In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is
initiated in Mode 0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by the incoming
start bit if REN = 1.

Multiprocessor Communications

Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, nine data bits are
received, followed by a stop bit. The ninth bit goes into RB8;
then comes a stop bit. The port can be programmed such
that when the stop bit is received, the serial port interrupt
is activated only if RB8 = 1. This feature is enabled by
setting bit SM2 in SCON.

The following example shows how to use the serial interrupt
for multiprocessor communications. When the master
processor must transmit a block of data to one of several
slaves, it first sends out an address byte that identifies the
target slave. An address byte differs from a data byte in that
the ninth bit is 1 in an address byte and 0 in a data byte. With
SM2 = 1, no slave is interrupted by a data byte. An address
byte, however, interrupts all slaves, so that each slave can
examine the received byte and see if it is being addressed.
The addressed slave clears its SM2 bit and prepares to
receive the data bytes that follows. The slaves that are not
addressed set their SM2 bits and ignore the data bytes.

SM2 has no effect in Mode 0 but can be used to check the
validity of the stop bit in Mode 1. In a Mode 1 reception, if
SM2 = 1, the receive interrupt is not activated unless a valid
stop bit is received.

Baud Rates

The baud rate in Mode 0 is fixed as shown in the following
equation.

Mode 0 Baud Rate =

Oscillator Frequency

The baud rate in Mode 2 depends on the value of the SMOD
bit in Special Function Register PCON. If SMOD = 0 (the
value on reset), the baud rate is 1/64 of the oscillator
frequency. If SMOD = 1, the baud rate is 1/32 of the
oscillator frequency, as shown in the following equation.

Mode 2 Baud Rate =

SMOD

x (Oscillator Frequency)

In the IC80C51/31, the Timer 1 overflow rate da termines
th e baud rates in Modes 1 and 3.

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IC80C51
IC80C31

Using the Timer 1 to Generate Baud Rates
When Timer 1 is the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate
and the value of SMOD according to the following equation.

Mode 1, 3

SMOD

(Timer 1 Overflow Rate)

Baud Rate

The Timer 1 interrupt should be disabled in this application.
The Timer itself can be configured for either timer or
counter operation in any of its three running modes. In the
most typical applications, it is configured for timer operation
in auto-reload mode (high nibble of TMOD = 0010B). In this
case, the baud rate is given by the following formula.

Mode 1,3

SMOD

Oscillator Frequency

Baud Rate

12x [256 (TH1)]

Programmers can achieve very low baud rates with Timer
1 by leaving the Timer 1 interrupt enabled, configuring the
Timer to run as a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do a 16-bit
software reload.

Table 9 lists commonly used baud rates and how they can
be obtained from Timer 1.

Table 7. Commonly Used Baud Rates Generated by Timer 1

Timer 1

Baud Rate

OSC

SMOD

TT
TT
T

Mode

Reload Value

Mode 0 Max: 1 MHz

12 MHz

Mode 2 Max: 375K

12 MHz

Modes 1, 3: 62.5K

12 MHz

FFH

19.2K

11.059 MHz

FDH

9.6K

11.059 MHz

FDH

4.8K

11.059 MHz

FAH

2.4K

11.059 MHz

F4H

1.2K

11.059 MHz

E8H

137.5

11.986 MHz

1DH

110

6 MHz

72H

110

12 MHz

FEEBH

More About Mode 0
Serial data enters and exits through RXD. TXD outputs the
shift clock. Eight data bits are transmitted/received, with
the LSB first. The baud rate is fixed at 1/12 the oscillator
frequency.

Figure 15 shows a simplified functional diagram of the
serial port in Mode 0 and associated timing.

Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBUF" signal at
S6P2 also loads a 1 into the ninth position of the transmit
shift register and tells the TX Control block to begin a
transmission. The internal timing is such that one full
machine cycle will elapse between "write to SBUF" and
activation of SEND.

SEND transfer the output of the shift register to the alternate
output function line of P3.0, and also transfers SHIFT
CLOCK to the alternate output function line of P3.1. SHIFT
CLOCK is low during S3, S4, and S5 of every machine
cycle, and high during S6, S1, and S2. At S6P2 of every
machine cycle in which SEND is active, the contents of the
transmit shift register are shifted one position to the right.

As data bits shift out to the right, 0s come in from the left.
When the MSB of the data byte is at the output position of
the shift register, the 1 that was initially loaded into the ninth
position is just to the left of the MSB, and all positions to the
left of that contain 0s. This condition flags the TX Control

IC80C51
IC80C31

S3-20

Integrated Circuit Solution Inc.

MC001-0B

block to do one last shift, then deactivate SEND and set TI.
Both of these actions occur at S1P1 of the tenth machine
cycle after "write to SBUF."

Reception is initiated by the condition REN = 1 and
RI = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register
and activates RECEIVE in the next clock phase.

RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents of
the receive shift register are shifted on position to the left.
The value that comes in from the right is the value that was
sampled at the P3.0 pin at S5P2 of the same machine
cycle.

As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the right-most
position arrives at the left-most position in the shift register,
it flags the RX Control block to do one last shift and load
SBUF. At S1P1 of the tenth machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared and RI is set.

More About Mode 1
Ten bits are transmitted (through TXD), or received (through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in SCON. In
the IC80C51 the baud rate is determined by the Timer 1
overflow rate.

Figure 16 shows a simplified functional diagram of the
serial port in Mode 1 and associated timings for transmit
and receive.

Transmission is initiated by any instruction that uses SBUF
as a destination register.

The "write to SBUF" signal also loads a 1 into the ninth bit
position of the transmit shift register and flags the TX
control unit that a transmission is requested. Transmission
actually commences at S1P1 of the machine cycle following
the next rollover in the divide-by-16 counter. Thus, the bit
times are synchronized to the divide-by-16 counter, not to
the "write to SBUF" signal.

The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time after
that.

As data bits shift out to the right, 0s are clocked in from the
left. When the MSB of the data byte is at the output position
of the shift register, the 1 that was initially loaded into the
ninth position is just to the left of the MSB, and all positions
to the left of that contain 0s. This condition flags the TX
Control unit to do one last shift, then deactivate SEND and

set TI. This occurs at the tenth divide-by-16 rollover after
"write to SBUF".

Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16 times
the established baud rate. When a transition is detected,
the divide-by-16 counter is immediately reset, and 1FFH is
written into the input shift register. Resetting the divide-by-
16 counter aligns its rollovers with the boundaries of the
incoming bit times.

The 16 states of the counter divide each bit time into 16th.
At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. This is done to reject noise. In order to reject
false bits, if the value accepted during the first bit time is not
0, the receive circuits are reset and the unit continues
looking for another 1-to-0 transition. If the start bit is valid,
it is shifted into the input shift register, and reception of the
rest of the frame proceeds.

As data bits come in from the right, 1s shift to the left. When
the start bit arrives at the leftmost position in the shift
register, (which is a 9-bit register in Mode 1), it flags the RX
Control block to do one last shift, load SBUF and RB8, and
set RI. The signal to load SBUF and RB8 and to set RI is
generated if, and only if, the following conditions are met at
the time the final shift pulse is generated.

1) RI = 0 and

2) Either SM2 = 0, or the received stop bit =1

If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the eight data bits go into SBUF, and
RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-0
transition in RXD.

More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). On transmit,
the ninth data bit (TB8) can be assigned the value of 0 or
1. On receive, the ninth data bit goes into RB8 in SCON.
The baud rate is programmable to either 1/32 or
1/64 of the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from Timer 1.

Figures 17 and 18 show a functional diagram of the serial
port in Modes 2 and 3. The receive portion is exactly the
same as in Mode 1. The transmit portion differs from Mode
1 only in the ninth bit of the transmit shift register.

Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBUF" signal also

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IC80C51
IC80C31

loads TB8 into the ninth bit position of the transmit shift
register and flags the TX Control unit that a transmission is
requested. Transmission commences at S1P1 of the
machine cycle following the next rollover in the divide-by-
16 counter. Thus, the bit times are synchronized to the
divide-by-16 counter, not to the "write to SBUF" signal.

The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit timer later, DATA is
activated, which enables the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time after
that. The first shift clocks a 1 (the stop bit) into the ninth bit
position of the shift register. Thereafter, only 0s are clocked
in. Thus, as data bits shift out to the right, 0s are clocked in
from the left. When TB8 is at the output position of the shift
register, then the stop bit is just to the left of TB8, and all
positions to the left of that contain 0s. This condition flags
the TX Control unit to do one last shift, then deactivate
SEND and set TI. This occurs at the eleventh divide-by-16
rollover after "write to SBUF".

At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit continues
looking for another 1-to-0 transition. If the start bit proves
valid, it is shifted into the input shift register, and reception
of the rest of the frame proceeds.

As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the shift
register (which in Modes 2 and 3 is a 9-bit register), it flags
the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The signal to load SBUF and RB8 and to
set RI is generated if, and only if, the following conditions
are met at the time the final shift pulse is generated:

1) RI = 0, and

2) Either SM2 = 0 or the received ninth data bit = 1

If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met, the received ninth data bit goes into RB8, and the first
eight data bits go into SBUF. One bit time later, whether the
above conditions were met or not, the unit continues
looking for a 1-to-0 transition at the RXD input.

Note that the value of the received stop bit is irrelevant to
SBUF, RB8, or RI.

Table 8. Serial Port Setup

Mode

SCON

SM2Variation

10H

50H

90H

D0H

70H

B0H

F0H

Single Processor

Environment

(SM2 = 0)

Multiprocessor

Environment

(SM2 = 1)

IC80C51
IC80C31

S3-26

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MC001-0B

INTERRUPT SYSTEM

The IC80C51/31 provides six interrupt sources: two external
interrupts, two timer interrupts, and a serial port interrupt.
These are shown in Figure 15.

The External Interrupts

INT0 and INT1 can each be either

level-activated or transition-activated, depending on bits
IT0 and IT1 in Register TCON. The flags that actually
generate these interrupts are the IE0 and IE1 bits in TCON.
When the service routine is vectored, hardware clears the
flag that generated an external interrupt only if the interrupt
was transition-activated. If the interrupt was level-activated,
then the external requesting source (rather than the on-
chip hardware) controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except for Timer 0 in Mode 3).
When a timer interrupt is generated, the on-chip hardware
clears the flag that generated it when the service routine is
vectored to.

The Serial Port Interrupt is generated by the logical OR of
RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service
routine normally must determine whether RI or TI generated
the interrupt, and the bit must be cleared in software.

All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware. That is, interrupts can be
generated and pending interrupts can be canceled in
software.

Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE (interrupt enable) at address 0A8H. As well as
individual enable bits for each interrupt source, there is a
global enable/disable bit that is cleared to disable all
interrupts or set to turn on interrupts (see SFR IE).

Figure 15. Interrupt System

INT1

INTERNAL

SERIAL

PORT

SCON.0

SCON.1

TIMER/COUNTER 1

TCON.7

TF1

EXTERNAL

INT RQST 1

TCON.3

IE1

TIMER/COUNTER 0

TCON.5

TF0

EXTERNAL

INT RQST 0

TCON.1

IE0

INT0

IE.4

IE.3

ET1

IE.2

EX1

IE.1

ET0

IE.0

EX0

IE.7

IP.4

IP.3

PT1

IP.2

PX1

IP.1

PT0

IP.0

PX0

POLLING

HARDWARE

SOURCE

I.D.

HIGH PRIORITY

INTERRUPT

REQUEST

VECTOR

SOURCE

I.D.

LOW PRIORITY

INTERRUPT

REQUEST

VECTOR

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Priority Level Structure

Each interrupt source can also be individually programmed
to one of two priority levels by setting or clearing a bit in
Special Function Register IP (interrupt priority) at address
0B8H. IP is cleared after a system reset to place all
interrupts at the lower priority level by default. A low-priority
interrupt can be interrupted by a high-priority interrupt but
not by another low-priority interrupt. A high-priority interrupt
can not be interrupted by any other interrupt source.

If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence, as follows:

Source

Priority Within Level

IE0

(Highest)

TF0

IE1

TF1

R1 + T1

(Lowest)

Note that the "priority within level" structure is only used to
resolve simultaneous requests of the same priority level.

How Interrupts Are Handled

The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following machine
cycle (the Timer 2 interrupt cycle is different, as described
in the Response Timer Section). If one of the flags was in
a set condition at S5P2 of the preceding cycle, the polling
cycle will find it and the interrupt system will generate an

LCALL to the appropriate service routine, provided this
hardware generated LCALL is not blocked by any of the
following conditions:

1. An interrupt of equal or higher priority level is already

in progress.

2. The current (polling) cycle is not the final cycle in the

execution of the instruction in progress.

3. The instruction in progress is RETI or any write to the

IE or IP registers.

Any of these three conditions will block the generation of
the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed
before vectoring to any service routine. Condition 3 ensures
that if the instruction in progress is RETI or any access to
IE or IP, then at least one more instruction will be executed
before any interrupt is vectored to.

The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. If an active interrupt flag is
not being serviced because of one of the above conditions
and is not still active when the blocking condition is removed,
the denied interrupt will not be serviced. In other words, the
fact that the interrupt flag was once active but not serviced
is not remembered. Every polling cycle is new. The polling
cycle/LCALL sequence is illustrated in Figure 16.

Note that if an interrupt of higher priority level goes active
prior to S5P2 of the machine cycle labeled C3 in Figure 16,
then in accordance with the above rules it will be serviced
during C5 and C6, without any instruction of the lower
priority routine having been executed.

Figure 16. Interrupt Response Timing Diagram

INTERRUPT

GOES ACTIVE

INTERRUPTS

ARE POLLED

INTERRUPT

ROUTINE

LONG CALL TO

INTERRUPT

VECTOR ADDRESS

INTERRUPT
LATCHED

S5P2

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Thus, the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that
generated the interrupt, and in other cases it does not. It
never clears the Serial Port or Timer 2 flags. This must be
done in the user's software. The processor clears an
external interrupt flag (IE0 or IE1) only if it was transition-
activated. The hardware-generated LCALL pushes the
contents of the Program Counter onto the stack (but it does
not save the PSW) and reloads the PC with an address that
depends on the source of the interrupt being serviced, as
shown in the following table.

Interrupt

Cleared by

Vector

Source

Request Bits

Hardware

Address

INT0

IE0

No (level)

0003H

Yes (trans.)

Timer 0

TF0

Yes

000BH

INT1

IE1

No (level)

0013H

Yes (trans.)

Timer 1

TF1

Yes

001BH

Serial Port

RI, TI

0023H

Timer 2

TF2, EXF2

002BH

System

RST

0000H

Reset

Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.

Note that a simple RET instruction would also have returned
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress.

SFR Register and

Interrupt

Flag

Bit Position

External 0

IE0

TCON.1

External 1

IE1

TCON.3

Timer 1

TF1

TCON.7

Timer 0

TF0

TCON.5

Serial Port

SCON.1

Serial Port

SCON.0

When an interrupt is accepted, the following action occurs:

1. The current instruction completes operation.

2. The PC is saved on the stack.

3. The current interrupt status is saved internally.

4. Interrupts are blocked at the level of the interrupts.

5. The PC is loaded with the vector address of the ISR

(interrupts service routine).

6. The ISR executes.

The ISR executes and takes action in response to the
interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of the
main program continues where it left off.

External Interrupts

The external sources can be programmed to be level-
activated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x
is triggered by a detected low at the

INTx pin. If ITx = 1,

external interrupt x is edge-triggered. In this mode if
successive samples of the

INTx pin show a high in one

cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to ensure
that the transition is seen so that interrupt request flag IEx
will be set. IEx will be automatically cleared by the CPU
when the service routine is called.

If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

Response Time

The

INT0 and INT1 levels are inverted and latched into the

interrupt flags IE0 and IE1 at S5P2 of every machine cycle.
Similarly, the Timer 2 flag EXF2 and the Serial Port flags RI
and TI are set at S5P2. The values are not actually polled
by the circuitry until the next machine cycle.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag TF2 is set at S2P2 and is polled in the same
cycle in which the timer overflows.

If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested
service routine will be the next instruction executed. The
call itself takes two cycles. Thus, a minimum of three
complete machine cycles elapsed between activation of an
external interrupt request and the beginning of execution of
the first instruction of the service routine. Figure 19 shows
response timings.

A longer response time results if the request is blocked by
one of the three previously listed conditions. If an interrupt
of equal or higher priority level is already in progress, the
additional wait time depends on the nature of the other
interrupt's service routine. If the instruction in progress is
not in its final cycle, the additional wait time cannot be more
than three cycles, since the longest instructions (MUL and
DIV) are only four cycles long. If the instruction in progress
is RETI or an access to IE or IP, the additional wait time
cannot be more than five cycles (a maximum of one more
cycle to complete the instruction in progress, plus four
cycles to complete the next instruction if the instruction is
MUL or DIV).

Thus, in a single-interrupt system, the response time is
always more than three cycles and less than nine cycles.

Single-Step Operation

The IC80C51/31 interrupt structure allows single-step
execution with very little software overhead. As previously
noted, an interrupt request will not be serviced while an
interrupt of equal priority level is still in progress, nor will it
be serviced after RETI until at least one other instruction
has been executed. Thus, once an interrupt routine has
been entered, it cannot be re-entered until at least one
instruction of the interrupted program is executed. One
way to use this feature for single-step operation is to
program one of the external interrupts (for example,

INT0)

to be level-activated. The service routine for the interrupt
will terminate with the following code:

JNB

P3.2,$

;Wait Here Till

INT0 Goes High

P3.2,$

;Now Wait Here Till it Goes Low

RETI

; G o B a c k a n d E x e c u t e O n e
Instruction

If the

INT0 pin, which is also the P3.2 pin, is held normally

low, the CPU will go right into the External Interrupt 0
routine and stay there until INT0 is pulsed (from low-to-
high-to-low). Then it will execute RETI, go back to the task
program, execute one instruction, and immediately re-
enter the External Interrupt 0 routine to await the next
pulsing of P3.2. One step of the task program is executed
each time P3.2 is pulsed.

IC80C51
IC80C31

S3-30

Integrated Circuit Solution Inc.

MC001-0B

Table 9. Reset Values of the SFR's

SFR Name

Reset Value

0000H

ACC

00H

PSW

00H

07H

DPTR

0000H

P0-P3

FFH

XX000000B

0X000000B

TMOD

00H

TCON

00H

TH0

00H

TL0

00H

TH1

00H

TL1

00H

SCON

00H

SBUF

Indeterminate

PCON

0XXX0000B

OTHER INFORMATION

Reset

The reset input is the RST pin, which is the input to a
Schmitt Trigger.

A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 17.

The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.

The internal reset algorithm writes 0s to all the SFRs except
the port latches, the Stack Pointer, and SBUF. The port
latches are initialized to FFH, the Stack Pointer to 07H, and
SBUF is indeterminate. Table 9 lists the SFRs and their
reset values.

Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.

Figure 17. Reset Timing

12 OSC. PERIODS

ALE

RST

SAMPLE

RST

SAMPLE
RST

INTERNAL RESET SIGNAL

PSEN

11 OSC. PERIODS

INST

ADDR

INST

19 OSC. PERIODS

S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4

ADDR

INST

ADDR

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

Power-on Reset

An automatic reset can be obtained when V

goes

through a 10

µF capacitor and GND through an 8.2K

resistor, providing the Vcc rise time does not exceed 1
msec and the oscillator start-up time does not exceed 10
msec. For the IC80C51/31, the external resistor can be
removed because the RST pin has an internal pulldown.
The capicator value can then be reduced to 1

µF (see

Figure 18).

When power is turned on, the circuit holds the RST pin high
for an amount of time that depends on the value of the
capacitor and the rate at which it charges. To ensure a good
reset, the RST pin must be high long enough to allow the
oscillator time to start-up (normally a few msec) plus two
machine cycles.

Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.

With this circuit, reducing V

quickly to 0 causes the RST

pin voltage to momentarily fall below 0V. However, this
voltage is internally limited and will not harm the device.

Figure 18. Power-On Reset Circuit

Vcc

RST

GND

Vcc

IC80C51/31

1.0 F

IC80C51
IC80C31

S3-32

Integrated Circuit Solution Inc.

MC001-0B

Power-Saving Modes of Operation

The IC80C51/31 has two power-reducing modes. Idle and
Power-down. The input through which backup power is
supplied during these operations is Vcc. Figure 19 shows
the internal circuitry which implements these features. In
the Idle mode (IDL = 1), the oscillator continues to run and
the Interrupt, Serial Port, and Timer blocks continue to be
clocked, but the clock signal is gated off to the CPU. In
Power-down (PD = 1), the oscillator is frozen. The Idle and
Power-down modes are activated by setting bits in Special
Function Register PCON.

Idle Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode, the
internal clock signal is gated off to the CPU, but not to the
Interrupt, Timer, and Serial Port functions. The CPU status
is preserved in its entirety; the Stack Pointer, Program
Counter, Program Status Word, Accumulator, and all other
registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated.
ALE and

PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.

The flag bits GF0 and GF1 can be used to indicate whether
an interrupt occurred during normal operation or during an
Idle. For example, an instruction that activates Idle can also
set one or both flag bits. When Idle is terminated by an
interrupt, the interrupt service routine can examine the flag
bits.

The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.

The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 17, two or three machine cycles of program execution
may take place before the internal reset algorithm takes
control. On-chip hardware inhibits access to the internal
RAM during his time, but access to the port pins is not
inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not write to a port pin or to external data
RAM.

Power-down Mode
An instruction that sets PCON.1 is the last instruction
executed before Power-down mode begins. In the Power-
down mode, the on-chip oscillator stops. With the clock
frozen, all functions are stopped, but the on-chip RAM and
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and

PSEN

output lows.

In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
the Power-down mode is invoked, and Vcc must be restored
to its normal operating level before the Power-down mode
is terminated. The reset that terminates Power-down also
frees the oscillator. The reset should not be activated
before Vcc is restored to its normal operating level and
must be held active long enough to allow the oscillator to
restart and stabilize (normally less than 10 msec).

The only exit from Power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.

OSC

CLOCK

GEN

XTAL 1

XTAL 2

IDL

CPU

INTERRUPT,
SERIAL PORT,
TIMER BLOCKS

Figure 19. Idle and Power-Down Hardware

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

Table 10. Status of the External Pins During Idle and Power-down Modes.

Mode

Memory

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

On-Chip Oscillators

The on-chip oscillator circuitry of the IC80C51/31 is a single
stage inverter, intended for use as a crystal-controlled,
positive reactance oscillator. In this application the crystal is
operated in its fundamental response mode as an inductive
reactance in parallel resonance with capacitance external to
the crystal (Figure 20). Examples of how to drive the clock
with external oscillator are shown in Figure 21.

Figure 20. Oscillator Connections

GND

XTAL1

XTAL2

EXTERNAL

OSCILLATOR

SIGNAL

Figure 21. External Clock Drive Configuration

GND

XTAL1

XTAL2

The crystal specifications and capacitance values (C1 and
C2 in Figure 20) are not critical. 20 pF to 30 pF can be used
in these positions at a 12 MHz to 24 MHz frequency with
good quality crystals. (For ranges greater than 24 MHz refer
to Figure 21.) A ceramic resonator can be used in place of
the crystal in cost-sensitive applications. When a ceramic
resonator is used, C1 and C2 are normally selected to be of
somewhat higher values. The manufacturer of the ceramic
resonator should be consulted for recommendation on the
values of these capacitors.

IC80C51
IC80C31

S3-36

Integrated Circuit Solution Inc.

MC001-0B

OPERATING RANGE

(1)

Range

Ambient Temperature

Oscillator Frequency

Commercial

0°C to +70°C

5V ± 10%

3.5 to 40 MHz

Note:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

(2)

2.0 to +7.0

BIAS

Temperature Under Bias

(3)

0 to +70

°C

STG

Storage Temperature

65 to +125

°C

Power Dissipation

1.5

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.

0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V
which may overshoot to Vcc + 2.0V for periods less than 20 ns.

3. Operating temperature is for commercial products only defined by this specification.

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

DC CHARACTERISTICS

(Ta=0°C to 70 °C; VCC=5V+10%; VSS=0V )

Symbol

Parameter

Test conditions

Min

Max

Unit

Input low voltage (All except

EA)

0.5

0.2Vcc 0.1

Input low voltage (

EA)

0.5

0.2Vcc 0.3

Input high voltage

0.2Vcc + 0.9

Vcc + 0.5

(All except XTAL 1, RST)

Input high voltage (XTAL 1)

0.7Vcc

Vcc + 0.5

SCH

RST positive schmitt-trigger

0.7Vcc

Vcc + 0.5

threshold voltage

SCH

RST negative schmitt-trigger

0.2Vcc

threshold voltage

(1)

Output low voltage

Iol = 100 µA

0.3

(Ports 1, 2, 3)

= 1.6 mA

0.45

= 3.5 mA

1.0

(1)

Output low voltage

= 200 µA

0.3

(Port 0, ALE,

PSEN)

= 3.2 mA

0.45

= 7.0 mA

1.0

Output high voltage

= 10 µA

0.9Vcc

(Ports 1, 2, 3, ALE,

PSEN)

Vcc = 4.5V-5.5V

= 25 µA

0.75Vcc

= 60 µA

2.4

Output high voltage

= 80 µA

0.9Vcc

(Port 0, ALE,

PSEN)

Vcc = 4.5V-5.5V

= 300 µA

0.75Vcc

= 800 µA

2.4

Logical 0 input current (Ports 1, 2, 3) V

= 0.45V

110

µA

Input leakage current (Port 0)

0.45V < V

< Vcc

+10

µA

Logical 1-to-0 transition current

= 2.0V

650

µA

(Ports 1, 2, 3)

RST

RST pulldown resister

300

Note:

1. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

10 mA

Maximum I

per 8-bit port

Port 0: 26 mA
Ports 1, 2, 3: 15 mA

Maximum total I

for all output pins: 71 mA

If I

exceeds the test condition, V

may exceed the related specification.

Integrated Circuit Solution Inc.

MC001-0B

IC80C51
IC80C31

Figure 27. Clock Signal Waveform for I

Tests in Active and Idle Mode (t

CLCH

CHCL

=5 ns)

AC CHARACTERISTICS

(Ta=0°C to 70 °C; VCC=5V+10%; GND=0V; C1 for Port 0, ALE and PSEN Outputs=100pF; C1 for other

outputs=80pF)

EXTERNAL MEMORY CHARACTERISTICS

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5 - 40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instr in

147

CLCL

LLPL

ALE low to

PSEN low

CLCL

PLPH

PSEN pulse width

110

CLCL

PLIV

PSEN low to valid instr in

105

CLCL

PXIX

Input instr hold after

PSEN

PXIZ

Input instr float after

PSEN

CLCL

AVIV

Address to valid instr in

188

105

CLCL

PLAZ

PSEN low to address float

RLRH

RD pulse width

230

130

CLCL

WLWH

WR pulse width

230

130

CLCL

RLDV

RD low to valid data in

157

CLCL

RHDX

Data hold after

RHDZ

Data float after

CLCL

LLDV

ALE low to valid data in

282

165

CLCL

AVDV

Address to valid data in

323

190

CLCL

LLWL

ALE low to

RD or WR low

105

145

CLCL

+20

AVWL

Address to

RD or WR low

146

CLCL

QVWX

Data valid to

WR transition

CLCL

WHQX

Data hold after

CLCL

RLAZ

RD low to address float

WHLH

RD or WR high to ALE high

CLCL

+15

0.45V

Vcc -- 0.5V

CHCX

CLCL

CLCH

CLCX

CHCL

0.7Vcc

0.2Vcc -- 0.1

IC80C51
IC80C31

S3-40

Integrated Circuit Solution Inc.

MC001-0B

EXTERNAL MEMORY CHARACTERISTICS

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5-40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

XLXL

Serial port clock cycle time

490

510

290 310

12t

CLCL

12t

CLCL

+10

QVXH

Output data setup to

406

240

10t

CLCL

clock rising edge

XHQX

Output data hold after

CLCL

clock rising edge

XHDX

Input data hold after

clock rising edge

XHDV

Clock rising edge to

417

250

10t

CLCL

input data valid

EXTERNAL CLOCK DRIVE

Symbol

Parameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

3.5

MHz

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

ROM VERIFICATION CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

MHz

AVQV

Address to data valid

40t

CLCL

ELQV

ENABLE low to data valid

48t

CLCL

EHQZ

Data float after ENABLE

48t

CLCL

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