IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

IC80LV51
IC80LV31

CMOS SINGLE CHIP
LOW VOLTAGE
8-BIT MICROCONTROLLER

FEATURES

· 80C51 based architecture

· 4K x 8 ROM (IC80LV51 only)

· 128 x 8 RAM

· Two 16-bit Timer/Counters

· Full duplex serial channel

· Boolean processor

· Four 8-bit I/O ports, 32 I/O lines

· Memory addressing capability

64K ROM and 64K RAM

· Programmable lock

Lock bits (2)

· Power save modes:

Idle and power-down

· Six interrupt sources

· Most instructions execute in 0.5 µs

· CMOS and TTL compatible

· Maximum speed: 24 MHz @ Vcc = 3.3V

· Packages available:

40-pin DIP
44-pin PLCC
44-Pin PQFP

GENERAL DESCRIPTION

The

ICSI

IC80LV51 and IC80LV31 are high-performance

microcontrollers fabricated using high-density CMOS
technology. The CMOS IC80LV51/31 is functionally
compatible with the industry standard 80C51 micro-
controllers.

The IC80LV51/31 is designed with 4K x 8 ROM (IC80LV51
only); 128 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; two 16-bit timer/counters
; a six-source, two-priority-level, nested interrupt structure
; and an on-chip oscillator and clock circuit. The
IC80LV51/31 can be expanded using standard TTL
compatible memory.

Figure 1. IC80LV51/31 Pin Configuration: 40-pin DIP

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

GND

VCC

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

Table 1. Detailed Pin Description

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

ALE

I/O

Address Latch Enable: Output pulse for latching the low byte
of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory.

External Access enable:

EA must be externally held low to

enable the device to fetch code from external program memory
locations 0000H to FFFFH. If

EA is held high, the device

executes from internal program memory unless the program
counter contains an address greater than 0FFFH.

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.

P1.0-P1.7

1-8

2-9

40-44

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal

1-3

pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). The Port 1

output buffers can sink/source four TTL inputs.

Port 1 also receives the low-order address byte during ROM
verification.

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
2 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). Port 2 emits

the high order address byte during fetches from external pro-
gram memory and during accesses to external data memory
that used 16-bit addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pullups when emitting 1s. During
accesses to external data memory that use 8-bit addresses
(MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2
Special Function Register.

Port 2 also receives the high-order bits and some control signals
during ROM verification.

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC005-0B

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

P3.0-P3.7

10-17

11, 13-19

5, 7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

Port 3 also serves the special features of the IC80LV51/31, as
listed below:

RxD (P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0

INT0 (P3.2): External interrupt 0.

INT1

INT1 (P3.3): External interrupt 1.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6): External data memory write strobe.

RD (P3.7): External data memory read strobe.

PSEN

Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory,

PSEN is activated twice each machine cycle

except that two

PSEN activations are skipped during each

access to external data memory.

PSEN is not activated during

fetches from internal program memory.

RST

Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external capaci-
tor connected to Vcc.

XTAL 1

Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.

XTAL 2

Crystal 2: Output from the inverting oscillator amplifier.

GND

Ground: 0V reference.

Vcc

Power Supply: This is the power supply voltage for operation.

Table 1. Detailed Pin Description (continued)

OPERATING DESCRIPTION

The detail description of the IC80LV51/31 included in this description are:

· Memory Map and Registers

· Timer/Counters

· Serial Interface

· Interrupt System

· Other Information

The detail information desriptionof the IC80LV51/31 refer to IC80C51/31 date sheet

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

Table 2. Reset Values of the SFR's

SFR Name

Reset Value

0000H

ACC

00H

PSW

00H

07H

DPTR

0000H

P0P3

FFH

XXX00000B

0XX00000B

TMOD

00H

TCON

00H

TH0

00H

TL0

00H

TH1

00H

TL1

00H

SCON

00H

SBUF

Indeterminate

PCON

0XXX0000B

OTHER INFORMATION

Reset

The reset input is the RST pin, which is the input to a
Schmitt Trigger.

A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 6.

The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.

The internal reset algorithm writes 0s to all the SFRs except
the port latches, the Stack Pointer, and SBUF. The port
latches are initialized to FFH, the Stack Pointer to 07H, and
SBUF is indeterminate. Table 2 lists the SFRs and their
reset values.

Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC005-0B

Power-on Reset

An automatic reset can be obtained when V

goes through

a 10µF capacitor and GND through an 8.2K resistor (see
Figure 5), providing the V

rise time does not exceed 1

msec and the oscillator start-up time does not exceed 10
msec. For the IC80LV51/31, the external resistor can be
removed because the RST pin has an internal pulldown.
The capicator value can then be reduced to 1 µF

When power is turned on, the circuit holds the RST pin high
for an amount of time that depends on the value of the
capacitor and the rate at which it charges. To ensure a good
reset, the RST pin must be high long enough to allow the
oscillator time to start-up (normally a few msec) plus two
machine cycles.

Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.

With this circuit, reducing V

quickly to 0 causes the RST

pin voltage to momentarily fall below 0V. However, this
voltage is internally limited, and will not harm the device.

Figure 5. Power-On Reset Circuit

Vcc

RST

GND

Vcc

IC80LV51/31

10 F

8.2K

Figure 6. Reset Timing

12 OSC. PERIODS

ALE

RST

SAMPLE

RST

SAMPLE
RST

INTERNAL RESET SIGNAL

PSEN

11 OSC. PERIODS

INST

ADDR

INST

19 OSC. PERIODS

S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4

ADDR

INST

ADDR

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

Power-Saving Modes of Operation

The IC80LV51/31 has two power-reducing modes. Idle
and Power-down. The input through which backup power
is supplied during these operations is Vcc. Figure 7 shows
the internal circuitry which implements these features. In
the Idle mode (IDL = 1), the oscillator continues to run and
the Interrupt, Serial Port, and Timer blocks continue to be
clocked, but the clock signal is gated off to the CPU. In
Power-down (PD = 1), the oscillator is frozen. The Idle and
Power-down modes are activated by setting bits in Special
Function Register PCON.

Idle Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode, the
internal clock signal is gated off to the CPU, but not to the
Interrupt, Timer, and Serial Port functions. The CPU status
is preserved in its entirety: the Stack Pointer, Program
Counter, Program Status Word, Accumulator, and all other
registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated.
ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.

The flag bits GF0 and GF1 can be used to indicate whether
an interrupt occurred during normal operation or during an
Idle. For example, an instruction that activates Idle can also
set one or both flag bits. When Idle is terminated by an
interrupt, the interrupt service routine can examine the flag
bits.

The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.

The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 19, two or three machine cycles of program execution
may take place before the internal reset algorithm takes
control. On-chip hardware inhibits access to the internal
RAM during his time, but access to the port pins is not
inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not write to a port pin or to external data
RAM.

Power-down Mode
An instruction that sets PCON.1 is the last instruction
executed before Power-down mode begins. In the Power-
down mode, the on-chip oscillator stops. With the clock
frozen, all functions are stopped, but the on-chip RAM and
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and

PSEN

output lows.

In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
the Power-down mode is invoked, and Vcc must be restored
to its normal operating level before the Power-down mode
is terminated. The reset that terminates Power-down also
frees the oscillator. The reset should not be activated
before Vcc is restored to its normal operating level and
must be held active long enough to allow the oscillator to
restart and stabilize (normally less than 10 msec).

The only exit from Power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.

OSC

CLOCK

GEN

XTAL 1

XTAL 2

IDL

CPU

INTERRUPT,
SERIAL PORT,
TIMER BLOCKS

Figure 7. Idle and Power-Down Hardware

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC005-0B

Table 3. Status of the External Pins During Idle and Power-down Modes.

Mode

Memory

ALE

PSEN

PORT 0

PORT 1

PORT 2

PORT 3

Idle

Internal

Data

Idle

External

Float

Data

Address

Data

Power-down

Internal

Data

Power-down

External

Float

Data

Table 4. Recommended Value for C1, C2, R

Frequency Range

4 MHz - 24 MHz

20 pF-30 pF

Not Apply

Figure 8. Oscillator Connections

GND

XTAL1

XTAL2

EXTERNAL

OSCILLATOR

SIGNAL

Figure 9. External Clock Drive Configuration

GND

XTAL1

XTAL2

On-Chip Oscillators

The on-chip oscillator circuitry of the IC80LV51/31 is a
single stage linear inverter, intended for use as a crystal-
controlled, positive reactance oscillator (Figure 8). In this
application the crystal is operated in its fundamental
response mode as an inductive reactance in parallel
resonance with capacitance external to the crystal (Figure
8). Examples of how to drive the clock with external
oscillator are shown in Figure 9.

The crystal specifications and capacitance values (C1 and
C2 in Figure 8) are not critical. 20 pF to 30 pF can be used
in these positions at a12 MHz to 24 MHz frequency with
good quality crystals. A ceramic resonator can be used in
place of the crystal in cost-sensitive applications. When a
ceramic resonator is used, C1 and C2 are normally selected
to be of somewhat higher values. The manufacturer of the
ceramic resonator should be consulted for recommendation
on the values of these capacitors.

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC005-0B

OPERATING RANGE

(1)

Range

Ambient Temperature

Oscillator Frequency

Commercial

0°C to +70°C

3.3V ± 10%

3.5 to 24 MHz

Note:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

(2)

2.0 to +7.0

BIAS

Temperature Under Bias

(3)

0 to +70

°C

STG

Storage Temperature

65 to +125

°C

Power Dissipation

1.5

Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V

for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V which
may overshoot to Vcc + 2.0V for periods less than 20 ns.

3. Operating temperature is for commercial products only defined by this specification.

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

DC CHARACTERISTICS

= 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V)

Symbol

Parameter

Test conditions

Min

Max

Unit

Input low voltage (All except

EA)

0.5

0.2Vcc + 0.1

Input low voltage (

EA)

0.5

0.2Vcc + 0.1

Input high voltage

0.2Vcc + 0.9

Vcc + 0.5

(All except XTAL 1, RST)

Input high voltage (XTAL 1)

0.7Vcc

Vcc + 0.5

SCH

RST positive schmitt-trigger

0.7Vcc

Vcc + 0.5

threshold voltage

SCH

RST negative schmitt-trigger

0.3Vcc

threshold voltage

Vol

(1)

Output low voltage

= 1.6 mA

0.45

(Ports 1, 2, 3)

(1)

Output low voltage

= 3.2 mA

0.45

(Port 0, ALE,

PSEN)

Output high voltage

= 20 µA

Vcc - 0.9

(Ports 1, 2, 3, ALE,

PSEN)

Output high voltage

= 800 µA

Vcc - 0.9

(Port 0, ALE,

PSEN)

Logical 0 input current (Ports 1, 2, 3) V

= 0.45V

µA

Input leakage current (Port 0)

0.45V < V

< Vcc

µA

Logical 1-to-0 transition current

= 2.0V

450

µA

(Ports 1, 2, 3)

RST

RST pulldown resister

150

450

Note:

1. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

10 mA

Maximum I

per 8-bit port

Port 0: 26 mA
Ports 1, 2, 3: 15 mA

Maximum total I

for all output pins: 71 mA

If I

exceeds the test condition, V

may exceed the related specification.

Pins are not guaranteed to sink greater than the listed test conditions.

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC006-0B

Figure 14. Clock Signal Waveform for Icc Tests in Active and Idle Modes. (t

CLCH

CHCL

=5 ns)

0.45V

Vcc -- 0.5V

CHCX

CLCL

CLCH

CLCX

CHCL

0.7Vcc

0.2Vcc -- 0.1

AC CHARACTERISTICS

= 0°C to 70°C; Vcc = 3.3V ± 10%; GND = 0V; Cl for Port 0, ALE and

PSEN Outputs = 100 pF;

Cl for other outputs = 80 pF)

EXTERNAL MEMORY CHARACTERISTICS

12 MHz

24 MHz

Variable Oscillator

Clock

(3.5-24 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

152

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instr in

313

147

CLCL

LLPL

ALE low to

PSEN low

CLCL

PLPH

PSEN pulse width

235

110

CLCL

PLIV

PSEN low to valid instr in

230

105

CLCL

PXIX

Input instr hold after

PSEN

PXIZ

Input instr float after

PSEN

CLCL

AVIV

Address to valid instr in

397

188

CLCL

PLAZ

PSEN low to address float

RLRH

RD pulse width

480

230

CLCL

WLWH

WR pulse width

480

230

CLCL

RLDV

RD low to valid data in

323

157

CLCL

RHDX

Data hold after

RHDZ

Data float after

162

CLCL

LLDV

ALE low to valid data in

573

282

CLCL

AVDV

Address to valid data in

656

323

CLCL

LLWL

ALE low to

RD or WR low

230

270

105 145

CLCL

+20

AVWL

Address to

RD or WR low

313

146

CLCL

QVWX

Data valid to

WR transition

CLCL

WHQX

Data hold after

CLCL

RLAZ

RD low to address float

WHLH

RD or WR high to ALE high

CLCL

+15

IC80LV51
IC80LV31

Integrated Circuit Solution Inc.

MC005-0B

EXTERNAL MEMORY CHARACTERISTICS

(Continued)

12 MHz

24 MHz

Variable Oscillator

Clock

(3.5-24 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

XLXL

Serial port clock cycle time

990

1010

290 310

12t

CLCL

12t

CLCL+

QVXH

Output data setup to

823

240

10t

CLCL

clock rising edge

XHQX

Output data hold after

157

CLCL

clock rising edge

XHDX

Input data hold after

clock rising edge

XHDV

Clock rising edge to

833

250

10t

CLCL

input data valid

EXTERNAL CLOCK DRIVE

Symbol

wParameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

3.5

MHz

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

ROM VERIFICATION CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

MHz

AVQV

Address to data valid

48t

CLCL

ELQV

ENABLE low to data valid

48t

CLCL

EHQZ

Data float after ENABLE

48t

CLCL

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IC80LV51-24PL

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IC80LV51-24PL