IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
with 8(4)-Kbytes of FLASH

FEATURES

· 80C52(51) based architecture

· 8(4)-Kbytes Flash memory with fast-pulse

programming algorithm and software protection

· 256 x 8 RAM (128x8 RAM)

· Three (Two)16-bit Timer/Counters

· Full duplex serial channel

· Boolean processor

· Four 8-bit I/O ports, 32 I/O lines

· Memory addressing capability

64K ROM and 64K RAM

· Program memory lock

Lock bits (3)

· Power save modes:

Idle and power-down

· Eight interrupt sources

· Most instructions execute in 0.3 µs

· CMOS and TTL compatible

· Maximum speed: 40 MHz @ Vcc = 5V

· Packages available:

40-pin DIP
44-pin PLCC
44-pin PQFP

GENERAL DESCRIPTION

The ICSI IC89C52(51)A is a high-performance micro-

controller fabricated with high-density CMOS technology.
The CMOS IC89C52A is functionally compatible with the
NMOS Intel 8052(51), Philips' 80C52(51) micro controller.

The IC89C52(51)A contains a 8K (4K) x 8 Flash; a 256

x 8 RAM (128 x 8 RAM); 32 I/O lines for either multi-
processor communications; I/O expansion or full duplex
UART; three (two) 16-bit timers/counters; a six-source
(five-source), two-priority-level, nested interrupt structure;
and on chip oscillator and clock circuit. The IC89C52(51)
A can be expanded using standard TTL compatible memory.

Figure 1. IC89C52(51)A Pin Configuration: 40-pin DIP

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

GND

VCC

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Table 1. Detailed Pin Description

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

ALE/

PROG

I/O

Address Latch Enable:

Output pulse for latching the low byte

of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory. This pin is also the Program
Pulse input (

PROG

) during Flash programming.

External Access enable:

must be externally held low to

enable the device to fetch code from external program memory
locations 0000H to 1FFFH . If

is held high, the device

executes from internal program memory unless the program
counter contains an address greater than 1FFFH. This also
receives the 12V programming enable voltage (V

) during

Flash programming.

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0:

Port 0 is an 8-bit open-drain, bidirectional I/O port. Port

0 pins that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.

Port 0 also receives the command and code bytes during
programmable memory programming and outputs the code
bytes during program verification. External pullups are required
during program verification.

P1.0-P1.7

1-8

2-9

40-44

I/O

Port 1:

Port 1 is an 8-bit bidirectional I/O port with internal

1-3

pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). The Port 1

output buffers can sink/source four TTL inputs.

Port 1 also receives the low-order address byte during Flash
programming and verification.

T2(P1.0):

Timer/Counter 2 external count input.(IC89C52A

only)

T2EX(P1.1):

Timer/Counter 2 trigger input.(IC89C52A only)

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2:

Port 2 is an 8-bit bidirectional I/O port with internal

pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
2 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

). Port 2 emits

the high order address byte during fetches from external pro-
gram memory and during accesses to external data memory
that used 16-bit addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pullups when emitting 1s. During
accesses to external data memory that use 8-bit addresses
(MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of the P2
Special Function Register.

Port 2 also receives the high-order bits and some control signals
during Flash programming and verification. P2.6 and P2.7 are
the control signals while the chip programs and erases.

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

P3.0-P3.7

10-17

11, 13-19

5, 7-13

I/O

Port 3:

Port 3 is an 8-bit bidirectional I/O port with internal

pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because
of the internal pullups. (See DC Characteristics: I

Port 3 also serves the special features of the IC89C52(51)A, as
listed below:

RxD (P3.0):

Serial input port.

TxD (P3.1):

Serial output port.

INT0

INT0 (P3.2):

External interrupt 0.

INT1

INT1 (P3.3):

External interrupt 1.

T0 (P3.4):

Timer 0 external input.

T1 (P3.5):

Timer 1 external input.

WR (P3.6):

External data memory write strobe.

Program control signal while the chip programs and erases.

RD (P3.7):

External data memory read strobe.

Program control signal while the chip programs and erases.

PSEN

Program Store Enable:

The read strobe to external program

memory. When the device is executing code from the external
program memory,

PSEN

is activated twice each machine cycle

except that two

PSEN

activations are skipped during each

access to external data memory.

PSEN

is not activated during

fetches from internal program memory.

PSEN

is an input control signal while memory program and

verification.

RST

Reset:

A high on this pin for two machine cycles while the

oscillator is running resets the device. An internal resistor to
VSS permits a power-on reset using only an external capacitor.
A small internal resistor permits power-on reset using only a
capacitor connected to VCC.

RST is an input control signal during memory program and
verification.

XTAL 1

Crystal 1:

Input to the inverting oscillator amplifier and input

to the internal clock generator circuits.

XTAL 2

Crystal 2:

Output from the inverting oscillator amplifier.

GND

Ground:

0V reference.

Vcc

Power Supply:

This is the power supply voltage for operation.

Table 1. Detailed Pin Description (continued)

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Figure 5. Programming Interface

Programming the IC89C52(51)A:

The IC89C52(51)A is normally shipped the on-chip

Flash memory array in the erased state (i.e. contents=FFH)
and ready to be programmed. The IC89C52(51)A is
programmed byte-by-byte in programming mode. Before
the on-chip flash code memory can be re-programmed, the
entire memory array must be erased electrically.

Programming Interface:

Some conditions must be satisfied before entering the

programming mode. The conditions are listed following.

1. RST is high level

PSEN

is low level

3. P3.6 and P3.7 is high level

The interface-controlled signals are matched these

conditions, then the IC89C52(51)A will enter received
command mode. The flash command is accepted by the
flash command decoder in command received mode. The
programming interface is listed in figure 5.

VSS

RST

PSEN

ALE/PROG

EA/VPP

P2.6

P2.7

P3.6

P3.7

XTAL1

PROG pulse

12V/H

Command Write

Output Enable

1-12MHz Clock

VCC

89C52A/51A

10K

VCC

D7-D0

A7-A0

P2.4-2.0

A12-A8

OPERATING DESCRIPTION

The detail description of the IC89C52(51)A included in this description are:

· Memory Map and Registers

· Timer/Counters

· Serial Interface

· Interrupt System

· Other Information

The detail information desription of the IC89C52(51)A refer to IC80C52/32 data sheet

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Flash Command Definitions

Bus

First Bus Cycle

Second Bus Cycle

Cycle

Operation

Address

Data

VPP

Operation Address

Data

VPP

Normal Verify

(1)

(n+1)

(2)

P2.6

00H

P2.7 Low

(3)

Read Signature Byte

P2.6

90H

P2.7 Low

30H

D5H

31H

52H

32H

55H/AAH

Program Code Memory

P2.6

40H

PROG

(3)

12V/H

Program Verify

(1)

(n+1)

(2)

P2.6

C0H

P2.7 Low

PVD

(3)

Program Lock Bit 1

P2.6

60H

PROG

D0H

12V/H

Program Lock Bit 2

P2.6

70H

PROG

D0H

12V/H

Program Lock Bit 3

P2.6

80H

PROG

D0H

12V/H

Chip Erase

P2.6

20H

PROG

D0H

12V/H

Erase Verify

(1)

(n+1)

(2)

P2.6

A0H

P2.7 Low

(3)

EVD

(3)

Note:

1. Normal Verify: Internal flash sense amplifier uses the same threshold as instruction executing threshold.
Program Verify: The flash sense amplifier applies an internally generated higher margin

voltage to the addressed byte. If a comparison between the programmed byte and the true data is successful, there
is a margin exists in the programmed data.

Erase Verify: The flash sense amplifier applies an internally generated lower margin voltage to the addressed
byte. Reading FFH from the addressed byte indicates that all bits in the bytes are erased.
2. To verify n bytes data.
3. SA = Selected Address of memory location to be read except program or erase verify.

SD = Data read from location SA with Normal Verification threshold.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
PVD = Data read from location PA during program verify.
EA = Address of memory location to be read during erase verify.
EVD - Data read from location EA during erase verify.

Programming Core Memory

Every code byte in the Flash array can be written and the entire array can be erased using the appropriate command
from Port 0 by programmer or application system. The program/erase are two-cycle operations. The first cycle is command
write cycle; the command 40H is written by P2.6 falling and rising edges. The command would be held a stable value within
P2.6 low state. The command decoder enables programming flag after the first cycle is completion, then the internal
programming flag is set. Rising edge of

PROG

will clear internal programming flag, so the programming command must

be presented every programming cycle. The second cycle is real flash programming cycle. The programming address and
data are latched at

PROG

falling edge, the programming time is controlled by low time of

PROG

. The programming flag

is cleared at

PROG

rising edge in the second cycle. Programming address range is from 0 to 1FFFH. IC89C52(51)A

programming range is from 0 to 1FFFH, but the program counter will jump to external menory while MCU executing the
address is excess 0FFFH.

The IC89C52(51)A code memory programming now is described in Figure 6.

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Program Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-
dress and data lines for verification. `C0H' command is
needed for switching to program verify mode. During pro-
gram verify, the code memory use the internally-gener-
ated higher margin voltage to the addressed byte.

Normal Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-
dress and data lines for verification. If flash command
decoder receives the `00H' command or IC89C52(51)A
power is initialized, the command decoder switches to
normal verify mode. During normal verify, the code
memory use the same threshold as instruction executing
threshold.

Erase Verify

If lock bits LB2 and LB3 have not been programmed,

the programmed code data can be read back via the ad-
dress and data lines for verification. `A0H' command is
needed for switching to erase verify mode. During erase
verify, the code memory use the internally-generated lower
margin voltage to the addressed byte.

Program Lock Bit 1, 2, 3

The lock bit 1, 2, 3 is programmed by using the erase
command `60H', `70H' and `80H' in the first cycle. In the
second cycle, the `D0H' command is presented on whole

PROG

strobe time. The

PROG

strobe time is real lock

bits programming time. The

PROG

rising edge will clear

the erasing state to normal verify state. The programming
lock bits operations don't use the smart algorithm but it is
programmed 10 times directly. If programming lock bits
are needed, it must be programmed after the encryption
array and code memory programming.

The IC89C52(51)A lock bits programming flow is
described in Figure 7.

Chip Erase

All flash cell must be programmed to `00' before the
chip is erased. The programming sequence is encryption
array, code memory and lock bit 1, 2, 3. The entire flash
array is erased electrically by using the erase command
`20H' in the first cycle. In the second cycle, the `D0H'
command is presented on whole

PROG

strobe time. The

PROG

strobe time is real flash erasing time. The

PROG

rising edge will clear the erasing state to normal verify
state. The code array is written with all "1"s. The chip erase
operation must be executed before the code memory can
be re-programmed. If the any flash cell is not `1' (include
encryption array and lock bits) repeat erase condition less
than 50 times.

The IC89C52(51)A detail erase flow is described in
Figure 8.

Reading the Signature Bytes:

The signature bytes are read by the same procedure as
a normal verification of locations 030H, 031H and 032H,
except that command is `90H'. The values returned are:

(030H) = D5H indicates manufactured by ICSI

(031H) = 52H indicates IC89C52A/IC89C51A

(032H) = AAH indicates programming voltage is 12V

55H indicates programming voltage is 5V

The signatures can be read by following conditions. It's
easier to recognize by programmer.
1. RST = high level.

PSEN

= Low level.

PROG

= High

level. VPP = High Level. P2.6 = Low level. P2.7 = Low
level. P3.6 = Low level. P3.7 = Low level.

2. Address is switched to (030H), (031H) and (032H). Then

the Data bus outputs the D5H, 52H, AAH (55H).

Program Lock bits

Protection Type

LB1

LB2

LB3

No program lock feature enabled.

MOVC instructions executed from external program memory are disabled from fetching

code bytes from internal memory,

is sampled and latched on reset, and further

programming of the Flash is disabled.

Same as 2, also verify is disabled

Same as 3, also external execution is disabled

Lock bits Features

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Figure. 6 IC89C52(51)A Main Memory Programming Flow

Start

Programming

PLSCNT=0,
Address=0,
Setup Received
Command Mode

(1)

VPP=Vppl,

Setup '40H'

Command

Setup 'C0H'

Command

VPP=Vppl,
Address=0

P2.6 set low pulse

for 100 ns

P2.6 set low pulse

for 100 ns

Programming

Error

Programming

Completed

Setup Address

,Data

VPP=Vpph

orVppl

(2)

Setup Address

& P2.7 = 0

Read Data

& Set P2.7=1

PROG set low

pulse for 200 us

INC

Address

INC

Address

INC PLSCNT

Last Address ?

PLSCNT=10?

Verify Data?

Yes

1. Received Command Mode status:
RST=1, PSEN=0, PROG=1, VPP=1, P2.6=1, P2.7=1, P3.6=1, P3.7=1
2. The VPP voltage is decided by Signature Byte address(032H)

Yes

Last Address?

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Figure. 8 IC89C52(51)A Erase Flow

Start

Erase Flow

PLSCNT=0,
Setup Received
Command Mode

(1)

Programming all

data to '00'

(4)

PLSCNT=0,

Address=00H

Setup 'A0H'

Command

P2.6 set low pulse

for 100 ns

Setup Address

& P2.7 = 0

Read Data

& Set P2.7 = 1

INC

PLSCNT

Erase operation

(2)

Erase operation

(2)

* 2 pulse

Erase

Completed

INC

Address

Data='FF' ?

Yes

1. Received Command Mode status:
RST=1, PSEN=0, PROG=1, VPP=1,
P2.6=1, P2.7=1, P3.6=1, P3.7=1
2. The erase operation show in "Erase
Operation" Sub-flow
3. To program main memory to '00',
then program lock bits.
The pre-programming address range
are from 0 to 1FFFH either in
IC89C52A or in IC89C51A
4. The VPP voltage is decided by
Signature Byte address(032H)

Start Erase

operation

VPP=Vppl,

Setup '20H'

Command

Setup 'D0H'

Command,

VPP=Vpph or

Vppl

(5)

P2.6 set low pulse

for 100 ns

VPP=Vppl

PROG set low

pulse for 200 ns

Erase

Completed

Chip Erase Sub-flow

Chip Erase Main flow

Last Address ?

PLSCNT=50 ?

Erase

Error

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

OPERATING RANGE

(1)

Range

Ambient Temperature

Oscillator Frequency

Commercial

0°C to +70°C

5V 10%

3.5 to 40 MHz

Note:

1. Operating ranges define those limits between which the functionality of the device is guaranteed.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Parameter

Value

Unit

TERM

Terminal Voltage with Respect to GND

(2)

2.0 to +7.0

BIAS

Temperature Under Bias

(3)

0 to +70

°C

STG

Storage Temperature

65 to +125

°C

Power Dissipation

1.5

Note:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

2. Minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.

0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V
which may overshoot to Vcc + 2.0V for periods less than 20 ns.

3. Operating temperature is for commercial products only defined by this specification.

Warning:

Stressing the device beyond the "Absolute Maximum Rating" may cause permanent
damage. This is stress rating only. Operation beyond the "operating conditions" is not
recommended and extended exposure beyond the "operating conditions" may affect
device reliability.

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

DC CHARACTERISTICS

(Ta=0°C to 70°C; VCC=5V+10%; VSS=0V )

Symbol

Parameter

Test conditions

Min

Max

Unit

Input low voltage (All except

)

0.5

0.2Vcc 0.1

Input low voltage (

)

0.5

0.2Vcc 0.3

Input high voltage

0.2Vcc + 0.9

Vcc + 0.5

(All except XTAL 1, RST,

)

Input high voltage (XTAL 1,

)

0.7Vcc

Vcc + 0.5

SCH

RST positive schmitt-trigger

0.7Vcc

Vcc + 0.5

threshold voltage

SCH

RST negative schmitt-trigger

0.3Vcc

threshold voltage

(1)

Output low voltage

Iol = 100 µA

0.3

(Ports 1, 2, 3)

= 1.6 mA

0.45

= 3.5 mA

1.0

(1)

Output low voltage

= 200 µA

0.3

(Port 0, ALE,

PSEN

)

= 3.2 mA

0.45

= 7.0 mA

1.0

Output high voltage

= 10 µA

0.9Vcc

(Ports 1, 2, 3, ALE,

PSEN

)

Vcc = 4.5V-5.5V

= 25 µA

0.75Vcc

= 60 µA

2.4

Output high voltage

= 80 µA

0.9Vcc

(Port 0, ALE,

PSEN

)

Vcc = 4.5V-5.5V

= 300 µA

0.75Vcc

= 800 µA

2.4

Logical 0 input current (Ports 1, 2, 3) V

= 0.45V

µA

Input leakage current (Port 0)

0.45V < V

< Vcc

+10

µA

Logical 1-to-0 transition current

= 2.0V

650

µA

(Ports 1, 2, 3)

RST

RST pulldown resister

=0v

300

Note:

1. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

10 mA

Maximum I

per 8-bit port

Port 0: 26 mA
Ports 1, 2, 3: 15 mA

Maximum total I

for all output pins: 71 mA

If I

exceeds the test condition, V

may exceed the related specification.

Pins are not guaranteed to sink greater than the listed test conditions.

2.The Icc test conditions are shown below. Minimum V

for Power Down is 2 V.

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Max

Unit

Icc

Power supply current

(1)

Vcc = 5.0V

Active mode

12 MHz

16 MHz

20 MHz

24 MHz

32 MHz

40 MHz

Idle mode

12 MHz

16 MHz

20 MHz

7.6

24 MHz

32 MHz

40 MHz

Power-down mode

= 5V

100

µA

Note:

1. See Figures 9,10,11, and 12 for Icc test conditiions.

Figure 9. Active Mode

Figure 10. Idle Mode

Figure 11. Power-down Mode

(Vcc=2.0V~6.0V)

XTAL1

GND

RST

Vcc

CLOCK

SIGNAL

Icc

XTAL2

Vcc

XTAL1

GND

RST

Vcc

CLOCK

SIGNAL

Icc

XTAL2

XTAL1

GND

RST

Vcc

Icc

XTAL2

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Figure 12. Clock Signal Waveform for I

Tests in Active and Idle Mode (t

CLCH

CHCL

=5 ns)

AC CHARACTERISTICS

(Ta=0°C to 70 °C; V

=5V 10%; V

=0V; C1 for port 0, ALE and

PSEN

Outputs=100pF; C1 for other outputs=80pF)

EXTERNAL MEMORY CHARACTERISTICS

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5 - 40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instr in

147

CLCL

LLPL

ALE low to

PSEN

low

CLCL

PLPH

PSEN

pulse width

110

CLCL

PLIV

PSEN

low to valid instr in

105

CLCL

PXIX

Input instr hold after

PSEN

PXIZ

Input instr float after

PSEN

CLCL

AVIV

Address to valid instr in

188

105

CLCL

PLAZ

PSEN

low to address float

RLRH

pulse width

230

130

CLCL

WLWH

pulse width

230

130

CLCL

RLDV

low to valid data in

157

CLCL

RHDX

Data hold after

RHDZ

Data float after

CLCL

LLDV

ALE low to valid data in

282

165

CLCL

AVDV

Address to valid data in

323

190

CLCL

LLWL

ALE low to

low

105

145

CLCL

+20

AVWL

Address to

low

146

CLCL

QVWX

Data valid to

transition

CLCL

WHQX

Data hold after

CLCL

RLAZ

low to address float

WHLH

high to ALE high

CLCL

+15

0.45V

Vcc -- 0.5V

CHCX

CLCL

CLCH

CLCX

CHCL

0.7Vcc

0.2Vcc -- 0.1

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

SERIAL PORT TIMING: SHIFT REGISTER MODE

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5-40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

XLXL

Serial port clock cycle time

490

290

12t

CLCL

QVXH

Output data setup to

327

160

10t

CLCL

clock rising edge

XHQX

Output data hold after

CLCL

clock rising edge

XHDX

Input data hold after

clock rising edge

XHDV

Clock rising edge to

284

117

10t

CLCL

--133

input data valid

EXTERNAL CLOCK DRIVE CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

3.5

MHz

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

Symbol

Parameter

Min

Max

Unit

Vcc

Programming and Erase Power Voltage

5.25

5.75

Vpp

Programming and Erase Enable Voltage

11.5

12.5

Ipp

Programming and Erase Enable Current

2.0

tDVCL

Data Valid to Command Setup Low

tCLCH

Command Setup Width

100

tCHDX

Data Hold after Command Setup

tAVGL

Address Setup to

PROG

Low

tGHAX

Address Hold after

PROG

tDVGL

Data Setup to

PROG

Low

tGHDX

Data Hold after

PROG

tSHGL

Vpp Setup to

PROG

Low

tGHSL

Vpp Hold after

PROG

tGLGH

PROG

Pulse Width in Programming Cycle

200

tGLGHE

PROG

Pulse Width in Erase Cycle

200

tAVQV

Address Valid to Data Valid

tELQV

ENABLE

Low to Data Valid

tAXQX

Data Float after Address Float

tEHQX

Data Float after

ENABLE

Flash Program/Erase and Verification & Test Mode Characteristics

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

Figure 18. Erase Timing Waveform

Figure 19. External Clock Drive Waveform

Figure 20. AC Test Point

Note:

1.AC inputs during testing are driven at Vcc-0.5v for logic "1" and 0.45V for logic "0".

Timing measurements are made at Vih min for logic "1" and max for logic "0".

0.45V

Vcc -- 0.5V

CHCX

CLCL

CLCH

CLCX

CHCL

0.7Vcc

0.2Vcc -- 0.1

Vcc - 0.5V

0.45V

0.2Vcc + 0.9V

0.2Vcc - 0.1V

P2.4-P2.0
P1.7-P1.0

PROG

VPP

DVCL

CLCH

ELQV

EHQX

GLGHE

GHSL

SHGL

CHDX

DVGL

GHDX

DVCL

CHDX

AVQV

AXQX

ADDRESS IN

ERASE

SETUP CYCLE

ERASE CYCLE

ERASE VERIFY

SETUP CYCLE

ERASE

VERIFY CYCLE

DATA OUT

P2.6

(Command Setup)

P2.7(OE)

D0H

20H

A0H

IC89C52(51)A

Integrated C ircuitSolution Inc.

MC008-0C 11/27/2001

ORDERING INFORMATION
Commercial Range: 0°C to +70°C

Speed

Order Part Number

Package

12 MHz

IC89C52(51)A-12PL

PLCC

IC89C52(51)A-12W

600mil DIP

IC89C52(51)A-12PQ

PQFP

24 MHz

IC89C52(51)A-24PL

PLCC

IC89C52(51)A-24W

600mil DIP

IC89C52(51)A-24PQ

PQFP

40 MHz

IC89C52(51)A-40PL

PLCC

IC89C52(51)A-40W

600mil DIP

IC89C52(51)A-40PQ

PQFP

Integrated C ircuitSolution Inc.

HEADQUARTER:

NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,

HSIN-CHU, TAIWAN, R.O.C.

TEL: 886-3-5780333

Fax: 886-3-5783000

BRANCH OFFICE:

7F, NO. 106, SEC. 1, HSIN-TAI 5

ROAD,

HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.

TEL: 886-2-26962140

FAX: 886-2-26962252

http://www.icsi.com.tw

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