IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

IC89C54/58/64

CMOS SINGLE CHIP
8-BIT MICROCONTROLLER
with 16/32/64-Kbytes of FLASH

FEATURES

· 80C52 based architecture

· 16K/32K/64K Byte Flash Memory with fast-

pulse programming algorithm

· 256 x 8 RAM

· Three 16-bit Timer/Counters

· Full duplex serial channel

· Boolean processor

· Four 8-bit I/O ports, 32 I/O lines

· Memory addressing capability

64K Program Memory and 64K Data Memory

· Program memory lock

Lock bits (3)

· Power save modes:

Idle and power-down

· Eight interrupt sources

· Most instructions execute in 0.3 µs

· CMOS and TTL compatible

· Maximum speed: 40 MHz @ Vcc = 5V

· Packages available:

40-pin DIP
44-pin PLCC
44-pin PQFP

GENERAL DESCRIPTION

IC89C54, IC89C58, IC89C64 are members of

ICSI

embedded microcontroller family. The IC89C54/58/64 uses
the same powerful instruction set, has the same architecture,
and is pin-to-pin compatible with standard 80C52 controller
devices. IC89C54/58/64 are just changed internal Flash
size, other features are same as standard IC89C52.

The IC89C54/58/64 contains a 16K/32K/64K x 8 Flash;

a 256 x 8 RAM; 32 I/O lines for either multi-processor
communications; I/O expansion or full duplex UART; three
16-bit timers/counters; an eight-source, two-priority-level,
nested interrupt structure; and on chip oscillator and clock
circuit. The IC89C54/58/64 can be expanded using standard
TTL compatible memory.

Figure 1. IC89C54/58/64 Pin Configuration: 40-pin DIP

T2/P1.0

T2EX/P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

RST

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

GND

VCC

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

ALE/PROG

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Table 1. Detailed Pin Description

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

ALE/

PROG

I/O

Address Latch Enable: Output pulse for latching the low byte
of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory. This pin is also the Program
Pulse input (

PROG) during Flash programming.

EA/V

External access enable: EA# must be externally held low to enable
the device to fetch code from external program memory locations
0000H to FFFFH. If EA# is held high, the device executes from internal
program memory unless the program counter contains an address
grater than 3FFFH/7FFFH respecting to IC89C54/58 and the device
always executes internal program memory in IC89C64.

This is also receives the 12 V programming enable voltage (Vpp)
during Flash programming, when 12 V programming is selected.

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins
that have 1s written to them float and can be used as high-
impedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.

Port 0 also receives the command and code bytes during
memory program and verification, and outputs the code bytes
during program verification. External pullups are required dur-
ing program verification.

P1.0-P1.7

1-8

2-9

40-44

I/O

Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-
ups. Port 1 pins that have 1s written to them are pulled high by
the internal pullups and can be used as inputs. As inputs, port
1 pins that are externally pulled low will source current because
of the internal pullups.
Port 1 also receives the low-order address byte during memory
program and verification.

T2(P1.0) : Timer/counter 2 external count input.

T2EX(P1.1): Timer/counter 2 trigger input.

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-
ups. Port 2 pins that have 1s written to them are pulled high by
the internal pullups and can be used as inputs. As inputs, port
2 pins that are externally pulled low will source current because
of the internal pullups. Port 2 emits the high order address byte
during fetches from external program memory and during
accesses to external data memory that used 16-bit addresses.
In this application, it uses strong internal pullups when emitting
1s. During accesses to external data memory that use 8-bit
addresses, port 2 emits the contents of the P2 special function
register.

Port 2 also receives the high-order address bits from A13 to A8
and some control signals during Flash programming and
verification. P2.6, P2.7 are the control signals while the chip
programs and erases. P2.6 is a program command strobe
signal. P2.7 is a data output enable signal.

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Symbol

PDIP

PLCC

PQFP

I/O

Name and Function

P3.0-P3.7

10-17

11, 13-19

5, 7-13

I/O

Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-
ups. Port 3 pins that have 1s written to them are pulled high by
the internal pull-ups and can be used as inputs. As inputs, port
3 pins that are externally pulled low will source current because
of the internal pullups.

Port 3 also serves the special features, as listed below:

RxD (P3.0): Serial input port.

TxD (P3.1): Serial output port.

INT0

INT0 (P3.2): External interrupt. Serve as A14 during memory
program and verification.

INT1

INT1 (P3.3): External interrupt. Serve as A15 during memory
program and verification.

T0 (P3.4): Timer 0 external input.

T1 (P3.5): Timer 1 external input.

WR (P3.6):External data memory write strobe. Control signal
during memory program, verification and erase.

RD (P3.7): External data memory read strobe. Control signal
during memory program, verification and erase.

PSEN

Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory,

PSEN is activated twice each machine cycle

except that two

PSEN activations are skipped during each

access to external data memory.

PSEN is not activated during

fetches from internal program memory.

PSEN is an input control

signal while memory program and verification.

RST

Reset: A high on this pin for two machine cycles while the
oscillator is running resets the device. An internal resistor to
VSS permits a power-on reset using only an external capacitor.
A small internal resistor permits power-on reset using only a
capacitor connected to VCC.

RST is an input control signal during memory program and
verification.

XTAL 1

Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.

XTAL 2

Crystal 2: Output from the inverting oscillator amplifier.

GND

Ground: 0V reference.

Vcc

Power Supply: This is the power supply voltage for operation.

Table 1. Detailed Pin Description (continued)

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

OPERATION DESCRIPTPION

The detail desription of the IC89C54/58/64 included
in this desription are:

· Memory Map and Registers

· Flash Memory

Other informations refer to IC80C52/32 data sheet except
flash memory.

Main Flash

RAM Size

IC89C54 16K Bytes : [0H~3FFFH] 256 Bytes : [ 0-FFH]

IC89C58 32K Bytes : [0H~7FFFH] 256 Bytes : [ 0-FFH]

IC89C64 64K Bytes : [0H~FFFFH] 256 Bytes : [ 0-FFH]

MEMORY MAP AND REGISTERS

Table 1 shows program memory and data memory

size versus three products. The IC89C54/58/64 series
includes a standard IC80C32 and a 16K/32K/64K Flash
Memory. The program memory and data memory access
ranges are listed table 2.

Table 2. Program memory and Data memory sizes

FLASH MEMORY PROGRAMMING

The Flash architecture of IC89C54/58/64 is shown in Figure 5. IC89C54/58 include block 1 and lock bits block.

The signature bytes are fixed value reside in MCU, they are read only. Block 2 resides in IC89C64 only.

Figure 5. The Flash Architecture of IC89C54/58/64

IC89C54

3 Lock Bits Falsh Cell

Dummy Address

3FFFH

0000H

0032H

0030H

7FFFH

0000H

0032H

0030H

EFFFH

0000H

0032H

0030H

FFFFH

F000H

16K Flash

(Block 1)

3x8 bits

Signature Bytes

Dummy Address

32K Flash

(Block 1)

3x8 bits

Signature Bytes

60K Flash

(Block 1)

4K Flash
(Block 2)

3x8 bits

Signature Bytes

3 Lock Bits Falsh Cell

IC89C58

IC89C64

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

The IC89C54/58/64 provide the user with a direct flash

memory access that can be used for programming into the
flash memory without using the CPU. The direct flash
memory access is entered using the External Host Mode.
While the reset input (RST) is continually held active (high),
if the

PSEN pin is forced by an input with low state, the

device enters the External Host Mode arming state at this
time. The CPU core is stopped from running and all the chip
I/O pins are reassigned and become flash memory access
and control pins. At this time, the external host should
initiate a "Read Signature Bytes" operation. After the
completion of the "Read Signature Bytes" operation, the
device is armed and enters the External Host Mode. After
the device enters into the External Host Mode, the internal
flash memory blocks are accessed through the re-assigned
I/O port pins by an external host, such as a printed circuit
board tester, a PC controlled development board or an
MCU programmer.

When the chip is in the external host mode, Port 0 pins

are assigned to be the parallel data input and output pins.
Port 1 pins are assigned to be the low order address bus
signals for the internal flash memory (A0-A7). The first six
bits of Port 2 pins (P2[0:5]) are assigned to be the upper
order address bus signals for the internal flash memory
(A8-A13) along with two of the Port 3 pins (P3.2 as A14 and
P3.3 as A15). Two upper order Port 2 pins (P2.6 and P2.
7) and two upper order Port 3 pins (P3.6 and P3.7) along
with RST,

PSEN, PROG/ALE, EA pins are assigned as the

control signal pins. The P3.4 is assigned to be the ready/
busy status signal, the P3.5 is assigned to be the timeout

signal, which can be used for handshaking with the external
host during a flash memory programming operation. The
flash memory programming operation (Erase, Program,
Verify, etc.) is internally self-timed and can be controlled by
an external host asynchronously or synchronously.

The insertion of an "arming" command prior to entering

the External Host Mode by utilizing the "Read Signature
Bytes" operation provides additional protection for
inadvertent writes to the internal flash memory cause by a
noisy or unstable system environment during the power-up
or power unstable conditions.

The External Host Mode uses hardware setup mode,

which are decoded from the control signal pins, to facilitate
the internal flash memory erase, test and programming
process. The External Host Mode Commands are enabled
on the falling edge of ALE/

PROG. The list in Table 3

outlines all the setup conditions of normal mode. Before
entering these written modes must have read 3 signature
bytes.

Programming Interface

Some conditions must be satisfied before entering the

programming mode. The conditions are listed in table 3.
The interface-controlled signals are matched these
conditions, then the IC89C54/58/64 will enter received
command mode. The flash command is accepted by the
flash command decoder in command received mode. The
programming interface is listed in figure 6.

Figure 6. IC89C52/54/64 External Host Programming Signals

VSS

RST

PSEN

ALE/PROG

EA/VPP

PROG pulse

12V/H

VCC

89C54/58/64

10K

VCC

D7-D0

A7-A0

P3.4

P3.5

P2.6

P2.7

P3.6

P3.7

Ready/Busy

Timeout

P2.6

P2.7

P3.6

P3.7

A13-A8

A15-A14

P2.5-2.0

P3.3-3.2

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Mode(1)

RST

PSEN# PROG# EA#

P2.6

P2.7

P3.6

P3.7

P0[7:0] P1[7:0] P3[3:2]

COM

P2[5:0] HEX(3)

Read Signature Byte

Chip Erase

12V/H

Block 1 (2) Erase

12V/H

Block 2 (2) Erase

12V/H

Program Main code

12V/H

Program Lock Bit 1

12V/H

Program Lock Bit 2

12V/H

Program Lock Bit 3

12V/H

Verify Lock Bits

DO[3:1]

Verify Main Code

1. To read the signature bytes 30H, 31H, 32H are needed before any written command. To read signature bytes is needed

after any new mode changed. This operation provides additional protection for inadvertent writes to the internal flash
memory cause by a noisy or unstable system environment during the power-up or unstable power condition. If any
unstable power condition has happened while written operation proceeds, to read signature bytes again will re-enable
written command. (Power-on reset voltage is about 2.7V.)

2. Block 1 includes flash address from 0000H to 3FFFH in IC89C54, from 0000H to 7FFFH in IC89C58, from 0000H to

EFFFH in IC89C64. Block 2 includes F000H to FFFFH. Block 2 is resident in IC89C64 only.

3. "COM HEX" presents the combination value of [P3.7, P3.6, P2.7, P2.6].

Product Identification

The "Read Signature Bytes" command accesses the Signature Bytes that identify the device as IC89C54/58/64 and the

manufacturer code. External programmers primarily use these Signature Bytes, shown in Table 4, in the selection of
programming algorithms. The Read Signature Bytes command is selected by the byte code of 00h on P3[7:6] and P2[7:
6]. Manufacturer code of ICSI is "D5H" that reside in address 30H of signature. The flash memory sizes of MCU are shown
in address 31H, code value 04H respect to 16K main flash memory, code value 08H respect to 32K main flash memory,
code value 10H respect to 64K main flash memory. The address 32H value of signature byte respect to written operation
VPP value, code value FFH respects to 12V and 55H respects to 5V.

Table 4. Signature Bytes Information

Addr 30H

Addr 31H

Addr 32H

IC89C54 (VPP=12V)

D5H

04H

FFH

IC89C54 (VPP=5V)

D5H

04H

05H

IC89C58 (VPP=12V)

D5H

08H

FFH

IC89C58 (VPP=5V)

D5H

08H

05H

IC89C64 (VPP=12V)

D5H

10H

FFH

IC89C64 (VPP=5V)

D5H

10H

05H

Table 3. Flash Programming Mode

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Arming Command

An arming command must take place before a Written

Mode will be recognized by the IC89C54/58/64. This is to
prevent accidental triggering of written operation due to
noise or programmer error. The arming command is as
follows:

A Read Signature Bytes command is issued. This is

actually a natural step for the programmer, but will also serve
as the arming command. After the above sequence, all other
Written Mode commands are enabled. Before the Read
Signature Bytes command is received, all other Written
Mode commands received are ignored. The IC89C54/8/64
will exit Written Mode if power off, so arming command is
needed every power on for entering External Host Command
Mode.

External Host Mode Commands

The following is a brief description of the commands. See

Table 3 for all signal logic assignments for the External Host
Mode Commands. The critical timing for all Erase and
Program commands, is self-generated by the flash memory
controller on-chip.

The high-to-low transition of the

PROG signal initiates

the Erase and Program commands, which are synchronized
internally. All the data in the memory array will be erased to
FFH. Memory addresses that are to be programmed must
be in the erased state prior to programming. There are two
erase commands in IC89C64, Block 1 erase and Block 2
erase. Selection of the Erase command to use, prior to
programming the device, will be dependent upon the contents
already in the array and the desired programming field block.

The "Chip Erase" command erases all bytes in both

memory blocks (16K/32K/64K) of the IC89C54/58/64.This
command ignores the "Lock bits" status and will erase the
Security Byte. The "Chip Erase" command is selected by the
byte code of 01H on P3[7:6] and P2[7:6]. The "Block 1 Erase"
command erases all bytes in one of the memory blocks 1
(16/32/60K) of the IC89C54/58/64. The "Block 2 Erase"
command erases all bytes in one of the memory blocks 2
(Address range is from F000H to FFFFH) of the IC89C64.
These block erase commands will not enable if the Lock Bit
2 or Lock Bit 3 is enabled.

Flash Operation Status Detection

(Ext. Host Handshake)

The IC89C54/58/64 provide two signals mean for an

external host to detect the completion of a flash memory
operation, therefore the external host can optimize the
system Program or Erase cycle of the embedded flash
memory. The end of a flash memory operation cycle
(Erase or Program) can be detected by: 1) monitoring the
Ready/

Busy bit at Port 3.4; 2) monitoring the Timeout

Polling bit at Port 3.5. The following two Program com-
mands are for programming new data into the memory
array. Selection of which Program command to use for
programming will be dependent upon the desired pro-
gramming field size. The Program commands will not
enable if Lock Bit 2 or Lock Bit 3 is enabled on the
selected memory block. The "Program Main Code"
command program data into a single byte. Ports P0[0:7]
are used for data in. The memory location is selected by
P1[0:7], P2[0:5], and P3[2:3] (A0-A15).

The "Verify Main Code" command allows the user to

verify that the IC89C54/58/64 correctly performed an Erase
or Program command. Ports P0[0:7] are used for data out.
The memory location is selected by P1[0:7], P2[0:5], and P3
[2:3] (A0-A15). These commands will not enable if any lock
bit is enabled on the selected memory block.

Ready/

BUSY

USY

The progress of the flash memory programming can be

monitored by the Ready/

BUSY output signal. The Ready/

BUSY indicates whether an Embedded Algorithm in Written
State Machine (WSM) is in progress or complete. The RY/
BY status is valid after the falling edge of the programming
or erase controlled signal. If the output is low (Busy), the
device is in an erasing/programming state with an internal
verification. If the output is high, the device is ready to read
data. While the RY/

BY signal is at low level (Busy) and

Timeout is high level, the programming or erasing procedure
is failed.

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Program Lock bits

Protection Type

LB1

LB2

LB3

No program lock feature enabled.

MOVC instructions executed from external program memory are disabled from fetching

code bytes from internal memory, #EA is sampled and latched on reset, and Data

verification is disabled. ("Verify Signature Byte" and "Verify Lock Bits are still enabled.)

Same as 2, also further written operation of the Flash is disabled

Same as 3, also external execution is disabled

Timeout

Timeout indicates whether the program or erase time has

exceeded a specified internal timer limit. Under these
conditions Timeout go to high and Ready/

BUSY remains a

low. This is a failed condition that indicates the program or
erase cycle was not successful completed. If there are any
program or erase failure in erasing operation, Timeout go to
high and Ready/

BUSY remains low.

It is cleared by any rising edge of written signal (like

Program Main Code, Chip Erase, ...etc.). The time from
written signal to Timeout=1 is re-initiated at every written
signal's rising edge. It is high when the program or erase
operations don't complete and have no newly written signal
in the expected time.

Programming a IC89C54/58/64

To program new data into the memory array, supply 5

volts to VDD and RST, and perform the following steps.

1. Set RST to high and

PSEN to low.

2. Raise

EA High (either 12V or 5V).

3. Read the "Read Signature Bytes" command to ensure

the correct programming algorithm.

4. Verify that the memory blocks for programming are in

the erased state, FFH. If they are not erased, then
erase

them using the appropriate Erase command.

5. Set P2.6, P2.7, P3.6, P3.7 to a properly programming

combination.

6. Select the memory location using the address lines (P1

[0:7], P2[0:5], P3[2:3]).

7. Present the data in on P0[0:7].

8. Pulse ALE/

PROG.

9. Wait for low to high transition on Ready/

Busy(P3.4) or

Timeout pin(P3.5). If Ready/

Busy is from low to

high, this address is programmed completely. If the

Timeout signal is from low to high before Ready/

Busy

goes high, this byte is failed in programming.

10. Repeat steps 6~9 until programming is finished.

Lock bits Features

The IC89C54/58/64 provide three lock bits to protect the embedded program against software piracy. These three

bytes are user programmable. The relation between lock bits status and protection type are listed in table 5.

Table 5. Lock Bits Features

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Absolute Maximum Ratings

Notes :

1. Operating temperature is for commercial product defined by this spec.

2. Minimum D.C. input voltage is -0.5 V. During transitions, inputs may undershoot, to -2.0 V for periods less than 20 ns.

Maximum D.C. voltage on output pins is VCC+0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

Warning:

Stressing the device beyond the "Absolute Maximum Rating" may cause permanent damage. This is stress rating only.
Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating
conditions" may affect device reliability.

Operating Range

Parameter

Rating

Unit

Operating temperature under bias

0 to +70

°C (1)

Storage temperature range

-65 to +125

°C

Voltage on any other pin to VSS

-2.0 to +7.0

V (2)

Power dissipation ( based on package heat transfer l

imitations, not device power consumption)

1.5

Operating ranges define those limits between which the functionality of the device is guaranteed.

Commercial devices case temperature

0 to +70 °C

VCC supply voltage

+4.5 to 5.5 V

Oscillator frequency

3.5 to 40 MHz

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

DC CHARACTERISTICS

(Ta=0°C to 70°C; VCC=5V+10%; VSS=0V )

Symbol

Parameter

Test conditions

Min

Max

Unit

Input low voltage (All except

EA)

0.5

0.2Vcc 0.1

Input low voltage (

EA)

0.5

0.2Vcc 0.3

Input high voltage

0.2Vcc + 0.9

Vcc + 0.5

(All except XTAL 1, RST)

Input high voltage (XTAL 1)

0.7Vcc

Vcc + 0.5

SCH

RST positive schmitt-trigger

0.7Vcc

Vcc + 0.5

threshold voltage

SCH

RST negative schmitt-trigger

0.3Vcc

threshold voltage

(1)

Output low voltage

Iol = 100 µA

0.3

(Ports 1, 2, 3)

= 1.6 mA

0.45

= 3.5 mA

1.0

(1)

Output low voltage

= 200 µA

0.3

(Port 0, ALE,

PSEN)

= 3.2 mA

0.45

= 7.0 mA

1.0

Output high voltage

= 10 µA

0.9Vcc

(Ports 1, 2, 3, ALE,

PSEN)

Vcc = 4.5V-5.5V

= 25 µA

0.75Vcc

= 60 µA

2.4

Output high voltage

= 80 µA

0.9Vcc

(Port 0, ALE,

PSEN)

Vcc = 4.5V-5.5V

= 300 µA

0.75Vcc

= 800 µA

2.4

Logical 0 input current (Ports 1, 2, 3) V

= 0.45V

µA

Input leakage current (Port 0)

0.45V < V

< Vcc

+10

µA

Logical 1-to-0 transition current

= 2.0V

650

µA

(Ports 1, 2, 3)

RST

RST pulldown resister

=0v

300

Note:

1. Under steady state (non-transient) conditions, I

must be externally limited as follows:

Maximum I

per port pin:

10 mA

Maximum I

per 8-bit port

Port 0: 26 mA
Ports 1, 2, 3: 15 mA

Maximum total I

for all output pins: 71 mA

If I

exceeds the test condition, V

may exceed the related specification.

Pins are not guaranteed to sink greater than the listed test conditions.

2.The Icc test conditions are shown below. Minimum VCC for Power Down is 2 V.

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test conditions

Min

Max

Unit

Icc

Power supply current

(1)

Vcc = 5.0V

Active mode

12 MHz

16 MHz

20 MHz

24 MHz

32 MHz

40 MHz

Idle mode

12 MHz

16 MHz

20 MHz

7.6

24 MHz

32 MHz

40 MHz

Power-down mode

= 5V

µA

Note:
1. See Figures7,8,9, and 10 for Icc test conditiions.

Figure 7. Active Mode

Figure 8. Active Mode

Figure 9. Active Mode

XTAL1

GND

RST

Vcc

CLOCK

SIGNAL

Icc

XTAL2

Vcc

XTAL1

GND

RST

Vcc

CLOCK

SIGNAL

Icc

XTAL2

XTAL1

GND

RST

Vcc

Icc

XTAL2

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Figure 10. Clock Signal Waveform for I

Tests in Active and Idle Mode (t

CLCH

CHCL

=5 ns)

AC CHARACTERISTICS

(Ta=0°C to 70°C; VCC=5V+10%; V

=0V; C1 for port 0, ALE and

PSEN Outputs=100pF; C1 for other outputs=80pF)

EXTERNAL MEMORY CHARACTERISTICS

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5 - 40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

1/t

CLCL

Oscillator frequency

3.5

MHz

LHLL

ALE pulse width

CLCL

AVLL

Address valid to ALE low

CLCL

LLAX

Address hold after ALE low

CLCL

LLIV

ALE low to valid instr in

147

CLCL

LLPL

ALE low to

PSEN low

CLCL

PLPH

PSEN pulse width

110

CLCL

PLIV

PSEN low to valid instr in

105

CLCL

PXIX

Input instr hold after

PSEN

PXIZ

Input instr float after

PSEN

CLCL

AVIV

Address to valid instr in

188

105

CLCL

PLAZ

PSEN low to address float

RLRH

RD pulse width

230

130

CLCL

WLWH

WR pulse width

230

130

CLCL

RLDV

RD low to valid data in

157

CLCL

RHDX

Data hold after

RHDZ

Data float after

CLCL

LLDV

ALE low to valid data in

282

165

CLCL

AVDV

Address to valid data in

323

190

CLCL

LLWL

ALE low to

RD or WR low

105

145

CLCL

+20

AVWL

Address to

RD or WR low

146

CLCL

QVWX

Data valid to

WR transition

CLCL

WHQX

Data hold after

CLCL

RLAZ

RD low to address float

WHLH

RD or WR high to ALE high

CLCL

+15

0.45V

Vcc -- 0.5V

CHCX

CLCL

CLCH

CLCX

CHCL

0.7Vcc

0.2Vcc -- 0.1

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

SERIAL PORT TIMING: SHIFT REGISTER MODE

24 MHz

40 MHz

Variable Oscillator

Clock

(3.5-40 MHz)

Symbol

Parameter

Min

Max

Min Max

Min

Max

Unit

XLXL

Serial port clock cycle time

490

510

290 310

12t

CLCL

12t

CLCL

+10

QVXH

Output data setup to

406

240

10t

CLCL

clock rising edg1

XHQX

Output data hold after

CLCL

clock rising edge

XHDX

Input data hold after

clock rising edge

XHDV

Clock rising edge to

417

250

10t

CLCL

input data valid

EXTERNAL CLOCK DRIVE CHARACTERISTICS

Symbol

Parameter

Min

Max

Unit

1/t

CLCL

Oscillator Frequency

3.5

MHz

CHCX

High time

CLCX

Low time

CLCH

Rise time

CHCL

Fall time

IC89C54/58/64

Integrated Circuit Solution Inc.

MC009-0B

Flash Program/Erase and Verification Characteristics

Symbol

Parameter

Min

Max

Unit

Vpph

Programming and Erase Enable Voltage

11.5

12.5

Vppl

Programming and Erase Enable Voltage

4.5

6.0

Ipph

Programming and Erase Enable Current while VPP=Vpph

2.0

Ippl

Programming and Erase Enable Current while VPP=Vppl

1.0

tWSCV

Power Setup to Command Setup Low

tCVQV

Command Valid to Data Output Valid

tAVQV

Address Valid to Data Output Valid

tCVPL

Command Valid to PROG# Low

tSHPL

VPP Setup to PROG# Low

tAVPL

Address Setup to PROG# Low

tDVPL

Data Setup to PROG# Low

tPLBL

PROG# Low to Busy# Low

tPLTL

PROG# Low to Timeout Low

tBLCX

Command Hold after Busy# Low

tBLAX

Address Hold after Busy# Low

tBLPH

Busy# Low to PROG# high

tBLDX

Data Hold after Busy# Low

tBLBH

Busy# Low to Busy# High

480

tBLTH

Busy# Low to Timeout High

180

720

tBHSL

VPP Hold after Busy# High

tAXQX

Output Hold after Address Release

tCXQX

Output Hold after Command Release

tBLBHE

Busy# Time while Chip Erase

4.5

Sec

tBLBHE1

Busy# Time while Block 1 Erase (IC89C54)

1.2

Sec

tBLBHE2

Busy# Time while Block 1 Erase (IC89C58)

2.4

Sec

tBLBHE3

Busy# Time while Block 1 Erase (IC89C64)

4.0

Sec

tBLBHE4

Busy# Time while Block 2 Erase (IC89C64)

0.7

Sec

tBLTHE

Busy# Low to Timeout High while Chip Erase

0.00018

6.75

Sec

tBLTHE1

Busy# Low to Timeout High while Block 1 Erase (IC89C54)

0.00018

1.8

Sec

tBLTHE2

Busy# Low to Timeout High while Block 1 Erase (IC89C58)

0.00018

3.6

Sec

tBLTHE3

Busy# Low to Timeout High while Block 1 Erase (IC89C64)

0.00018

6.0

Sec

tBLTHE4

Busy# Low to Timeout High while Block 2 Erase (IC89C64)

0.00018

1.05

Sec

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IC89C54

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: IC89C54