ICS280
MDS 280 C
1
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
PRELIMINARY INFORMATION
Description
The ICS280 field programmable spread spectrum
clock synthesizer generates up to four high-quality,
high-frequency clock outputs including multiple
reference clocks from a low-frequency crystal input. It
is designed to replace crystals, crystal oscillators and
stand alone spread spectrum devices in most
electronic systems.
Using ICS' VersaClock
TM
software to configure PLLs
and outputs, the ICS280 contains a One-Time
Programmable (OTP) ROM for field programmability.
Programming features include input/output
frequencies, spread spectrum amount and eight
selectable configuration registers.
Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple
crystals and oscillators, saving board space and cost.
The ICS280 is also available in factory programmed
custom versions for high-volume applications.
Features
Packaged as 16-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Configurable Spread Spectrum Modulation
Input crystal frequency of 5 to 27 MHz
Input clock frequency of 3 to 166 MHz
Up to four reference outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
Block Diagram
Crystal
Oscillator
GND
3
3
VDD
PDTS
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
S2:S0
3
OTP
ROM
with PLL
Values
X2
Crystal or
Clock Input
External capacitors
are required with a crystal input.
X1/ICLK
PLL1 with
Spread
Spectrum
CLK1
CLK3
CLK4
CLK2
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
2
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
Pin Assignment
Pin Descriptions
12
1
11
2
10
3
9
4
S0
5
S1
6
VDD
7
GND
8
VDD
PDTS
S2
GND
GND
VDD
CLK2
CLK4
16
15
14
13
CLK3
X2
16 pin (173 mil) TSSOP
X1/ICLK
CLK1
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
GND
Power
Connect to ground.
2
S0
Input
Select pin 0. Internal pull-up resistor.
3
S1
Input
Select pin 1. Internal pull-up resistor.
4
VDD
Power
Connect to +3.3 V.
5
CLK1
Output
Output clock 1. Weak internal pull-down when tri-state.
6
CLK2
Output
Output clock 2. Weak internal pull-down when tri-state.
7
GND
Power
Connect to ground.
8
X1/ICLK
XI
Crystal input. Connect this pin to a crystal or external input clock.
9
X2
XO
Crystal Output. Connect this pin to a crystal. Float for clock input.
10
VDD
Power
Connect to +3.3 V.
11
CLK3
Output
Output clock 3. Weak internal pull-down when tri-state.
12
CLK4
Output
Output clock 4. Weak internal pull-down when tri-state.
13
GND
Power
Connect to ground.
14
PDTS
Input
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resistor.
15
VDD
Power
Connect to +3.3 V.
16
S2
Input
Select pin 2. Internal pull-up resistor.
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
3
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
External Components
The ICS280 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
trace (a
commonly used trace impedance), place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS280 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Avoid the use of vias on the decoupling circuit.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device. Crystal capacitors must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
ICS280 Configuration Capabilities
The architecture of the ICS280 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 1024 and N = 1 to
32,895.
The ICS280 also provides separate output divide
values, from 2 through 63, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Drive Control
The ICS270 has two output drive settings. Low drive
should be selected when outputs are less than 100
MHz. High drive should be selected when outputs are
greater than 100 MHz. (Consult the AC Electrical
Characteristics for output rise and fall times for each
drive option.)
ICS VersaClock Software
ICS applies years of PLL optimization experience into a
user friendly software that accepts the user's target
reference clock and output frequencies and generates
the lowest jitter, lowest power configuration, with only a
press of a button. The user does not need to have prior
PLL experience or determine the optimal VCO
frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and
provides an easy to understand, bar code rating for the
target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in
seconds.
Spread Spectrum Modulation
The ICS280 utilizes frequency modulation (FM) to
distribute energy over a range of frequencies. By
modulating the output clock frequencies, the device
effectively lowers energy across a broader range of
frequencies; thus, lowering a system's electromagnetic
interference (EMI). The modulation rate is the time from
transitioning from a minimum frequency to a maximum
frequency and then back to the minimum.
Spread Spectrum Modulation can be applied as either
"center spread" or "down spread". During center spread
modulation, the deviation from the target frequency is
OutputFreq
REFFreq
M
N
-----
=
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
4
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
equal in the positive and negative directions. The
effective average frequency is equal to the target
frequency. In applications where the clock is driving a
component with a maximum frequency rating, down
spread should be applied. In this case, the maximum
frequency, including modulation, is the target
frequency. The effective average frequency is less than
the target frequency.
The ICS280 operates in both center spread and down
spread modes. For center spread, the frequency can
be modulated between 0.125% to 2.0%. For down
spread, the frequency can be modulated between
-0.25% to -4.0%.
Both output frequency banks will utilize identical spread
spectrum percentage deviations and modulation rates,
if a common VCO frequency can be identified.
Spread Spectrum Modulation Rate
The spread spectrum modulation frequency applied to
the output clock frequency may occur at a variety of
rates. For applications requiring the driving of
"down-circuit" PLLs, Zero Delay Buffers, or those
adhering to PCI standards, the spread spectrum
modulation rate should be set to 30-33 kHz. For other
applications, a 120 kHz modulation option is available.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS280. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Parameter
Condition
Min.
Typ.
Max.
Units
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Storage Temperature
-65
150
C
Soldering Temperature
Max 10 seconds
260
C
Junction Temperature
125
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS280PG/PGLF)
0
+70
C
Ambient Operating Temperature (ICS280PGI/PGILF)
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.135
+3.3
+3.465
V
Power Supply Ramp Time
4
ms
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
5
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
Note 1: Example with 25 MHz crystal input, four unloaded 33.3 MHz outputs.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
Operating Supply Current
Input High Voltage
IDD
Config. Dependent - See
VersaClock
TM
Estimates
mA
Four 33.3333 MHz outs,
VDD=3.3V;
PDTS = 1, no load, Note 1
22
mA
PDTS = 0, no load
500
A
Input High Voltage
V
IH
S2:S0
VDD/2+1
V
Input Low Voltage
V
IL
S2:S0
0.4
V
Input High Voltage, PDTS
V
IH
VDD-0.5
V
Input Low Voltage, PDTS
V
IL
0.4
V
Input High Voltage
V
IH
ICLK
VDD/2+1
V
Input Low Voltage
V
IL
ICLK
VDD/2-1
V
Output High Voltage
(CMOS High)
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -8 mA (Low Drive);
I
OH
= -12 mA (High Drive)
2.4
V
Output Low Voltage
V
OL
I
OL
= 8 mA (Low Drive);
I
OL
= 12 mA (High Drive)
0.4
V
Short Circuit Current
I
OS
Low Drive
40
mA
High Drive
70
Nom. Output Impedance
Z
O
20
Internal pull-up Resistor
R
PUS
S2:S0, PDTS
190
k
Internal pull-down
Resistor
R
PD
CLK outputs
120
k
Input Capacitance
C
IN
Inputs
4
pF
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
6
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
F
IN
Fundamental crystal
5
27
MHz
Clock Input
3
166
MHz
Output Frequency
0.314
200
MHz
Output Rise/Fall Time
t
OF
80% to 20%, high drive,
Note 1
1.0
ns
Output Rise/Fall Time
t
OF
80% to 20%, low drive,
Note 1
2.0
ns
Duty Cycle
Note 2
40
49-51
60
%
Output Frequency Synthesis Error
Configuration Dependent
TBD
ppm
Power-up Time
PLL lock-time from
power-up
4
10
ms
PDTS goes high until
stable CLK output,
Spread Spectrum Off
0.2
2
ms
PDTS goes high until
stable CLK output,
Spread Spectrum On
4
7
ms
One Sigma Clock Period Jitter
Configuration Dependent
50
ps
Maximum Absolute Jitter
t
ja
Deviation from Mean.
Configuration Dependent
+200
ps
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
78
C/W
JA
1 m/s air flow
70
C/W
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
JC
37
C/W
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
7
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
Marking Diagrams
Marking Diagrams (Pb free)
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. "I" denotes industrial temperature range (if applicable).
4. "L" denotes Pb (lead) free package.
5. Bottom marking: country of origin.
1
8
9
16
280PG
######
YYWW
1
8
9
16
280PGI
######
YYWW
1
8
9
16
280PGL
######
YYWW
1
8
9
16
280PGIL
######
YYWW
Triple PLL Field Prog. Spread Spectrum Clock Synthesizer
MDS 280 C
8
Revision 062205
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS280
PRELIMINARY INFORMATION
Package Outline and Package Dimensions
(16-pin TSSOP, 173 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
VersaClock
TM
is a trademark of Integrated Circuit Systems, Inc. All rights reserved.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS280PG
See page 7
Tubes
16-pin TSSOP
0 to +70
C
ICS280PGI
Tubes
16-pin TSSOP
-40 to +85
C
ICS280PGLF
Tubes
16-pin TSSOP
0 to +70
C
ICS280PGILF
Tubes
16-pin TSSOP
-40 to +85
C
INDEX
AREA
1 2
24
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
.10 (.004)
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.10
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
.018
.030
0
8
0
8
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