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Электронный компонент: ICS8442AY

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8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
1
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8442 is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency
Synthesizer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8442 has a selectable TEST_CLK
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The
VCO operates at a frequency range of 250MHz to 700MHz. The
VCO frequency is programmed in steps equal to the value of
the input reference or crystal frequency. The VCO and output
frequency can be programmed using the serial or parallel inter-
face to the configuration logic. The low phase noise characteris-
tics of the ICS8442 makes it an ideal clock source for Gigabit
Ethernet and Sonet applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential LVDS outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
Output frequency range: 31.25MHz to 700MHz
Crystal input frequency range: 10MHz to 25MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming counter
and output dividers
RMS period jitter: 2.7ps (typical)
Cycle-to-cycle jitter: 18ps (typical)
3.3V supply voltage
0C to 85C ambient operating temperature
"Lead-Free" package available
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
TEST_CLK
XTAL_SEL
V
DDA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
GND
GND
nFOUT0
FOUT0
V
DD
nFOUT1
FOUT1
V
DD
TEST
X
T
AL2
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8442
HiPerClockSTM
ICS
OSC
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL1
XTAL2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
1
2
4
8
MR
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
2
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
cific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel
input mode. The relationship between the VCO frequency, the
crystal frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10
M 28. The frequency
out is defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8442 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVDS output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8442 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1 shows
the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a spe-
F
UNCTIONAL
D
ESCRIPTION
fVCO = fxtal x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS FOUT
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
*NOTE: The NULL timing slot must be observed.
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
FOUT = fVCO = fxtal x M
N
N
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
3
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
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8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
4
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
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8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
5
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
85C
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AXIMUM
R
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Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
10mA
Surge Current
15mA
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
6
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
85C
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
85C
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ABLE
7. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, T
A
= 0C
TO
85C
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8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
7
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
S
KEW
odc & t
P
ERIOD
Cycle-to-Cycle Jitter
Period Jitter
V
OH
V
REF
V
OL
Mean Period
(First edge after trigger)
Reference Point
(Trigger Edge)
1
contains 68.26% of all measurements
2
contains 95.4% of all measurements
3
contains 99.73% of all measurements
4
contains 99.99366% of all measurements
6
contains (100-1.973x10
-7
)% of all measurements
Histogram
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SW I N G
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
nFOUT0, nFOUT1
FOUT0, FOUT1
nFOUT0,
nFOUT1
FOUT0,
FOUT1
t
sk(o)
nFOUTx
FOUTx
nFOUTy
FOUTy
V
OS
/


VOS
S
ETUP
VOD /


VOD
S
ETUP
3.3V O
UTPUT
L
OAD
T
EST
C
IRCUIT
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
SCOPE
Qx
nQx
LVDS
3.3V5%
Power Supply
+
-
Float GND
t
cycle n
t
cycle n+1
t
jit(cc) =
t
cycle n
t
cycle n+1
1000 Cycles
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
S
TORAGE
A
REA
N
ETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below lists the common fre-
Table 8. Common SANs Application Frequencies
Table 9. Configuration Details for SANs Applications
A
PPLICATION
I
NFORMATION
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2
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8442 provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the inter nal PLL. V
DD
and V
DDA
, should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply
isolation is required.
Figure 2 illustrates how a 10
along
|with a 10
F and a .01F bypass capacitor should be
connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
t
c
e
n
n
o
c
r
e
t
n
I
y
g
o
l
o
n
h
c
e
T
y
c
n
e
u
q
e
r
F
l
a
t
s
y
r
C
)
z
H
M
(
2
4
4
8
S
C
I
y
c
n
e
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q
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r
F
t
u
p
t
u
O
S
E
D
R
E
S
o
t
)
z
H
M
(
2
4
4
8
S
C
I
s
g
n
i
t
t
e
S
N
&
M
8
M
7
M
6
M
5
M
4
M
3
M
2
M
1
M
0
M
1
N
0
N
t
e
n
r
e
h
t
E
t
i
b
a
g
i
G
5
2
5
2
1
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0
0
0
1
0
1
0
0
1
0
5
2
0
5
2
0
0
0
0
1
0
1
0
0
0
1
5
2
5
2
.
6
5
1
0
0
0
0
1
1
0
0
1
1
0
5
2
1
3
5
.
9
1
5
2
.
6
5
1
0
0
0
1
0
0
0
0
0
1
0
1
l
e
n
n
a
h
C
r
e
b
i
F
5
2
5
2
1
.
3
5
0
0
0
0
1
0
0
0
1
1
1
5
2
5
2
.
6
0
1
0
0
0
0
1
0
0
0
1
1
0
2
l
e
n
n
a
h
C
r
e
b
i
F
5
2
6
5
1
0
6
.
6
1
5
2
1
8
.
2
3
1
0
0
0
1
0
0
0
0
0
1
0
d
n
a
b
i
n
i
f
n
I
5
2
5
2
1
0
0
0
0
1
0
1
0
0
1
0
5
2
0
5
2
0
0
0
0
1
0
1
0
0
0
1
quencies used as well as the settings for the ICS8442 to gener-
ate the appropriate frequency.
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
9
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
C
RYSTAL
I
NPUT
I
NTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS8442 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
Figure 3. C
RYSTAL
I
NPU
t I
NTERFACE
C2
22p
C1
18p
X1
18pF Parallel Crystal
ICS8442
25
24
XTAL2
XTAL1
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 3. Typical results using parallel 18pF crystals are shown
in Table 10.
LVDS D
RIVER
T
ERMINATION
A general LVDS interface is shown in
Figure 4. In a 100
differ-
ential transmission line environment, LVDS drivers require a
matched load termination of 100
across near the receiver in-
put. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the un-used outputs.
100
Differential Transmission Line
3.3V
3.3V
LVDS_DRIVER
R1
100
HiPerClockS
Zo = 50 Ohm
Zo = 50 Ohm
nCLK
CLK
F
IGURE
4. T
YPICAL
LVDS D
RIVER
T
ERMINATION
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
The schematic of the ICS8442 layout example used in this layout
guideline is shown in
Figure 5A. The ICS8442 recommended PCB
board layout for this example is shown in
Figure 5B. This layout
example is used as a general guideline. The layout in the actual
L
AYOUT
G
UIDELINE
F
IGURE
5A. R
ECOMMENDED
S
CHEMATIC
L
AYOUT
U1
ICS8442
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
GND
T
EST
VDD
FO
U
T1
nFO
U
T1
VDD
FO
U
T0
nFO
U
T0
GND
MR
S_CLOCK
S_DATA
S_LOAD
VDDA
nXTAL_SEL
T_CLK
XTAL1
M4
M3
M2
M1
M0
VCO_
SEL
nP
_LO
A
D
XT
AL
2
VDDA
VDD
Zo = 50 Ohm
TL1
+
-
VDD
nFO
U
T0
R7
10
X1
Zo = 50 Ohm
TL1N
R2
100
R1
100
+
-
C2
C15
0.1u
FO
U
T1
C14
0.1u
C16
10u
C11
0.01u
VDD
nFO
U
T1
Zo = 50 Ohm
TL2
FO
U
T0
Zo = 50 Ohm
TL2N
C1
system will depend on the selected component types, the den-
sity of the components, the density of the traces, and the stack
up of the P.C. board.
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
11
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
If V
DDA
shares the same power supply with V
DD
, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the V
DDA
as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
traces should be routed first and should be locked prior to routing
other signal traces.
The traces with 50
transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other. Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Make sure no other signal trace is routed between the
clock trace pair.
The matching termination resistors R1 and R2 should be located
as close to the receiver input pins as possible. Other termination
scheme can also be used but is not shown in this example.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS8442
VDD
TL1
C15
C14
R1
Same requirement fo
FOUT1/nFOUT1
VDDA
Close to the input
pins of the
receiver
R7
X1
C2
For FOUT0/n FOUT0
output TL1, TL1N are
50 Ohm traces and
equal length
VIA
GND
TL1N
TL1
PIN 1
U1
C1
TL1N
C11
C16
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
12
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8442 is: 3662
T
ABLE
10.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
32 L
EAD
LQFP


JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- Y S
UFFIX
FOR
32 L
EAD
LQFP
T
ABLE
11. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
14
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
T
ABLE
12. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
8442AY
www.icst.com/products/hiperclocks.html
REV. C JULY 8, 2004
15
Integrated
Circuit
Systems, Inc.
ICS8442
700MH
Z
, C
RYSTAL
O
SCILLATOR
-
TO
-D
IFFERENTIAL
LVDS F
REQUENCY
S
YNTHESIZER
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