87949AY-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 2, 2002
1
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
1, 2
C
LOCK
G
ENERATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS87949-01 is a low skew, 1, 2 Clock
Generator and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS87949-01 has selectable single
ended clock or LVPECL clock inputs. The single
ended clock input accepts LVCMOS or LVTTL input levels.
The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The low impedance LVCMOS outputs are de-
signed to drive 50
series or parallel terminated transmis-
sion lines. The effective fanout can be increased from 15 to
30 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the 1, 2 or a
combination of 1 and 2 modes. The master reset input, MR/
nOE, resets the internal frequency dividers and also controls
the active and high impedance states of all outputs.
The ICS87949-01 is characterized at 3.3V core/3.3V output and
3.3V core/ 2.5V output. Guaranteed bank, output and part-to-
part skew characteristics make the ICS87949-01 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
F
EATURES
15 single ended LVCMOS outputs, 7
typical output
impedance
Selectable LVCMOS or LVPECL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum input frequency: 250MHz
Output skew: 200ps (maximum)
Part-to-part skew: 500ps (typical)
Multiple frequency skew: 350ps (maximum)
3.3V input, outputs may be either 3.3V or 2.5V supply modes
0C to 70C ambient operating temperature
Industrial temperature information available upon request
Functionally compatible to the MPC949 in a smaller footprint
requiring less board space
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
HiPerClockSTM
,&6
V
DDD
QD4
GND
QD3
V
DDD
QD2
GND
QD1
V
DDD
QD0
GND
GND
MR/nOE
CLK_SEL
V
DD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
36
35
34
33
32
31
30
29
28
27
26
25
48 47 46 45 44 43 42 41 40 39 38 37
nc
GND
QC0
V
DDC
QC1
GND
QC2
V
DDC
QC3
GND
GND
QD5
V
DDB
QB2
GND
QB1
V
DDB
QB0
GND
GND
QA1
V
DDA
QA0
GND
ICS87949-01
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
MR/nOE
QA0 - QA1
QB0 - QB2
QC0 - QC3
QD0 - QD5
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
0
1
1
2
0
1
0
1
0
1
0
1
R
0
1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87949AY-01
www.icst.com/products/hiperclocks.html
REV. A JANUARY 2, 2002
4
Integrated
Circuit
Systems, Inc.
ICS87949-01
L
OW
S
KEW
1, 2
C
LOCK
G
ENERATOR
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V5%, T
A
= 0C
TO
70C
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