www.docs.chipfind.ru
Integrated
Circuit
Systems, Inc.
ICS950403
Advance Information
0732--01/27/03
Block Diagram
Functionality
Pin Configuration
Recommended Application:
AMD K8 System Clock with AMD, VIA or ALI Chipset
Output Features:
2 - Differential pair push-pull CPU clocks @
3.3V
9 - PCICLK (Including 1 free running) @ 3.3V
3 - Selectable PCICLK/HTTCLK @ 3.3V
1 - HTTCLK @ 3.3V
1 - 48MHz @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI
control.
Watchdog timer technology and RESET# output
to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/
write operations.
Uses external 14.318MHz crystal.
Supports Hyper Transport Technology (HTTCLK).
AMD - K8TM System Clock Chip
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
*FS0/REF0 1
48 REF1/FS1*
VDDREF 2
47 GND
X1 3
46 VDDREF
X2 4
45 REF2/FS2*
GND 5
44 Reset#
~*ModeA/HTTCLK0 6
43 VDDA
~*ModeB/PCICLK7/HTTCLK1 7
42 GND
~PCICLK8/HTTCLK2 8
41 CPUCLK8T0
VDDPCI 9
40 CPUCLK8C0
GND 10
39 GND
~PCICLK9/HTTCLK3 11
38 VDDCPU
PCICLK10 12
37 CPUCLK8T1
PCICLK0 13
36 CPUCLK8C1
PCICLK1 14
35 VDDCPU
GND 15
34 GND
VDDPCI 16
33 GND
~PCICLK2 17
32 PD#*
~PCICLK3 18
31 48MHz/FS3**
VDDPCI 19
30 GND
GND 20
29 AVDD48
PCICLK4 21
28 24_48MHz/Sel24_48#*~
PCICLK5 22
27 GND
~PCICLK_F 23
26 SDATA
~PCICLK6 24
25 SCLK
48-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
~ This Output has 2X Drive Strength
IC
S950403
CPU
HTT
PCI
MHz
MHz
MHz
0
0
0
0
100.90
67.27
33.63
0
0
0
1
133.90
66.95
33.48
0
0
1
0
168.00
67.20
33.60
0
0
1
1
202.00
67.33
33.67
0
1
0
0
100.20
66.80
33.40
0
1
0
1
133.50
66.75
33.38
0
1
1
0
166.70
66.68
33.34
0
1
1
1
200.40
66.80
33.40
1
0
0
0
150.00
60.00
30.00
1
0
0
1
180.00
60.00
30.00
1
0
1
0
210.00
70.00
35.00
1
0
1
1
240.00
60.00
30.00
1
1
0
0
270.00
67.50
33.75
1
1
0
1
233.33
66.67
33.33
1
1
1
0
266.67
66.67
33.33
1
1
1
1
300.00
75.00
37.50
FS3
FS2
FS1
FS0
PLL2
PLL1
Spread
Spectrum
PCICLK (6:0, 10)
CPUCLKT (1:0)
CPUCLKC (1:0)
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
SDATA
SCLK
PD#
FS (3:0)
SEL24_48#
MODE (A,B)
Control
Logic
REF (2:0)
48MHz
24_48MHz
/ 2
PCICLK_F
PCICLK/HTTCLK (3:1)
HTTCLK0
X 2
Config.
Reg.
2
ICS950403
Advance Information
0732--01/27/03
Pin Descriptions
PIN #
PIN NAME
PIN
TYPE
DESCRIPTION
1
*FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
2
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
3
X1
IN
Crystal input,nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
GND
PWR
Ground pin.
6
~*ModeA/HTTCLK0
I/O
Mode selection latch input pin / Hyper Transport output.
7
~*ModeB/PCICLK7/HTTCLK
I/O
Mode selection latch input pin / PCI clock output / Hyper Transport output.
8
~PCICLK8/HTTCLK2
OUT
PCI clock output / Hyper Transport output.
9
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
10
GND
PWR
Ground pin.
11
~PCICLK9/HTTCLK3
OUT
PCI clock output / Hyper Transport output.
12
PCICLK10
OUT
PCI clock output.
13
PCICLK0
OUT
PCI clock output.
14
PCICLK1
OUT
PCI clock output.
15
GND
PWR
Ground pin.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
~PCICLK2
OUT
PCI clock output.
18
~PCICLK3
OUT
PCI clock output.
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
GND
PWR
Ground pin.
21
PCICLK4
OUT
PCI clock output.
22
PCICLK5
OUT
PCI clock output.
23
~PCICLK_F
I/O
Free running PCI clock not affected by PCI_STOP#.
24
~PCICLK6
OUT
PCI clock output.
25
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
26
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
27
GND
PWR
Ground pin.
28
24_48MHz/Sel24_48#*~
I/O
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
29
AVDD48
PWR
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
30
GND
PWR
Ground pin.
31
48MHz/FS3**
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
32
PD#*
IN
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 1.8ms.
33
GND
PWR
Ground pin.
34
GND
PWR
Ground pin.
35
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
36
CPUCLK8C1
OUT
"Complementary" clocks of differential 3.3V push-pull K8 pair.
37
CPUCLK8T1
OUT
"True" clocks of differential 3.3V push-pull K8 pair.
38
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
39
GND
PWR
Ground pin.
40
CPUCLK8C0
OUT
"Complementary" clocks of differential 3.3V push-pull K8 pair.
41
CPUCLK8T0
OUT
"True" clocks of differential 3.3V push-pull K8 pair.
42
GND
PWR
Ground pin.
43
VDDA
PWR
3.3V power for the PLL core.
44
Reset#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
45
REF2/FS2*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
46
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
47
GND
PWR
Ground pin.
48
REF1/FS1*
I/O
14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength
3
ICS950403
Advance Information
0732--01/27/03
General Description
The ICS950403 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary
clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems.
The ICS950403 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This
part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the
use of a serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency
setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and
enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to
0.1MHz increment.
Power Groups
Mode Functionality Tables
ModeA
ModeB
Pin7
Pin8
Pin11
0
0
HTTCLK1
HTTCLK2
PCICLK9
0
1
HTTCLK1
HTTCLK2
HTTCLK3
1
0
PCICLK7
PCICLK8
PCICLK9
1
1
HTTCLK1
PCICLK8
PCICLK9
AVDD
GND
2
5
Crystal
29
27, 30
48MHz fixed,
29
33
Fix Analog, Fix Digital
43
42
CPU Master Clock, CPU Analog
VDD
GND
9
10
PCICLK/HTTCLK Outputs
16, 19
15, 20
PCICLK Outputs
35, 38
34, 39
CPU outputs
46
47
REF
Pin Number
Description
4
ICS950403
Advance Information
0732--01/27/03
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
5
ICS950403
Advance Information
0732--01/27/03
Table1: Frequency Selection Table
Bit4
Bit3
Bit2
Bit1
CPU
HTT
PCI
FS3
FS2
FS1
FS0
MHz
MHz
MHz
0
0
0
0
0
100.90
67.27
33.63
0
0
0
0
1
133.90
66.95
33.48
0
0
0
1
0
168.00
67.20
33.60
0
0
0
1
1
202.00
67.33
33.67
0
0
1
0
0
100.20
66.80
33.40
0
0
1
0
1
133.50
66.75
33.38
0
0
1
1
0
166.70
66.68
33.34
0
0
1
1
1
200.40
66.80
33.40
0
1
0
0
0
150.00
60.00
30.00
0
1
0
0
1
180.00
60.00
30.00
0
1
0
1
0
210.00
70.00
35.00
0
1
0
1
1
240.00
60.00
30.00
0
1
1
0
0
270.00
67.50
33.75
0
1
1
0
1
233.33
66.67
33.33
0
1
1
1
0
266.67
66.67
33.33
0
1
1
1
1
300.00
75.00
37.50
1
0
0
0
0
100.00
66.67
33.33
1
0
0
0
1
133.33
66.67
33.33
1
0
0
1
0
166.66
66.66
33.33
1
0
0
1
1
200.00
66.67
33.33
1
0
1
0
0
103.00
68.67
34.33
1
0
1
0
1
137.33
68.66
34.33
1
0
1
1
0
171.66
68.66
34.33
1
0
1
1
1
206.00
68.67
34.33
1
1
0
0
0
154.50
61.80
30.90
1
1
0
0
1
185.40
61.80
30.90
1
1
0
1
0
216.30
72.10
36.05
1
1
0
1
1
247.20
61.80
30.90
1
1
1
0
0
278.10
69.53
34.76
1
1
1
0
1
240.33
68.67
34.33
1
1
1
1
0
274.67
68.67
34.33
1
1
1
1
1
309.00
77.25
38.63
Bit5
6
ICS950403
Advance Information
0732--01/27/03
I
2
C Table: Functionality and Frequency Control Register
Control
Function
Bit 7
GSR_EN
Gear Shift Reset
Enable
RW
Disable
Enable
0
Bit 6
-
SPREAD Enable
RW
Disable
Enable
0
Bit 5
-
FS4
RW
0
Bit 4
-
FS3
RW
0
Bit 3
-
FS2
RW
0
Bit 2
-
FS1
RW
0
Bit 1
-
FS0
RW
0
Bit 0
FS Source
Frequency H/W IIC
Select
RW
Latch Inputs
IIC
0
I
2
C Table: Output Control Register
Control
Function
Bit 7
PCICLK10
Output Control
RW
Disable
Enable
1
Bit 6
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Control
Function
Bit 7
CPUT/C_1
Output Control
RW
Disable
Enable
1
Bit 6
CPUT/C_0
Output Control
RW
Disable
Enable
1
Bit 5
REF2
Output Control
RW
Disable
Enable
1
Bit 4
REF1
Output Control
RW
Disable
Enable
1
Bit 3
REF0
Output Control
RW
Disable
Enable
1
Bit 2
24_48MHz
Output Control
RW
Disable
Enable
1
Bit 1
48MHz
Output Control
RW
Disable
Enable
1
Bit 0
WDSEN
Watchdog Soft Alarm
Enable
RW
Disable
Enable
0
I
2
C Table: Output Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
1
Bit 6
Reserved
Reserved
RW
-
-
1
Bit 5
Reserved
Reserved
RW
-
-
1
Bit 4
Reserved
Reserved
RW
-
-
1
Bit 3
Reserved
Reserved
RW
-
-
1
Bit 2
Reserved
Reserved
RW
-
-
1
Bit 1
Reserved
Reserved
RW
-
-
1
Bit 0
Reserved
Reserved
RW
-
-
1
-
-
-
-
-
-
-
-
31
-
Byte 3
Pin #
1
PWD
-
-
Name
Pin #
Byte 0
Type
0
-
-
-
-
-
-
45
21
Pin #
17
Byte 1
14
12
18
1
28
41/40
Byte 2
48
Pin #
PWD
0
24
22
Name
Type
1
PWD
Name
1
PWD
0
Type
0
1
Name
13
37/36
Type
See Table1: Frequency
Selection Table
7
ICS950403
Advance Information
0732--01/27/03
I
2
C Table: Read back
Control
Function
Bit 7
WDHRB
WD Hard Alarm Status
Read back
R
-
-
X
Bit 6
WDSRB
WD Soft Alarm Status
Read back
R
-
-
X
Bit 5
24_48SEL
24_48SEL pin Control
R
By S/W
By Latched
1
Bit 4
FS3
FS3 on POR state
R
By S/W
By Latched
1
Bit 3
FS2
FS2 on POR state
R
By S/W
By Latched
1
Bit 2
FS1
FS1 on POR state
R
By S/W
By Latched
1
Bit 1
FS0
FS0 on POR state
R
By S/W
By Latched
1
Bit 0
Reserved
Reserved
R
-
-
0
I
2
C Table: Output Control Register
Control
Function
Bit 7
HTTCLK0
Output Control
RW
Disable
Enable
1
Bit 6
PCICLK9/HTTCLK3
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK8/HTTCLK2
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK7/HTTCLK1
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK_F
Output Control
RW
Disable
Enable
1
Bit 2
Reserved
Reserved
RW
-
-
0
Bit 1
Reserved
Reserved
RW
-
-
0
Bit 0
Reserved
Reserved
RW
-
-
0
I
2
C Table: Byte Count Register
Control
Function
Bit 7
BC7
RW
-
-
0
Bit 6
BC6
RW
-
-
0
Bit 5
BC5
RW
-
-
0
Bit 4
BC4
RW
-
-
0
Bit 3
BC3
RW
-
-
1
Bit 2
BC2
RW
-
-
1
Bit 1
BC1
RW
-
-
1
Bit 0
BC0
RW
-
-
1
I
2
C Table: Vendor and Revision ID Register
Control
Function
Bit 7
RID3
R
-
-
0
Bit 6
RID2
R
-
-
0
Bit 5
RID1
R
-
-
0
Bit 4
RID0
R
-
-
0
Bit 3
VID3
R
-
-
0
Bit 2
VID2
R
-
-
0
Bit 1
VID1
R
-
-
0
Bit 0
VID0
R
-
-
1
-
-
-
-
-
-
-
Byte 7
Pin #
-
-
PWD
-
Type
Name
0
1
Writing to this register
will configure how
many bytes will be read
back, default is 0F
= 15
bytes.
-
-
Byte 6
Pin #
23
-
-
-
6
11
8
7
-
Byte 5
Pin #
Name
-
-
-
-
-
Name
Type
Byte 4
Pin #
-
-
PWD
Name
0
Type
PWD
PWD
1
Type
0
1
-
-
-
-
REVISION ID
VENDOR ID
0
1
8
ICS950403
Advance Information
0732--01/27/03
I
2
C Table: Output Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
Reserved
Reserved
RW
-
-
0
Bit 3
Reserved
Reserved
RW
-
-
0
Bit 2
Reserved
Reserved
RW
-
-
0
Bit 1
Reserved
Reserved
RW
-
-
0
Bit 0
Reserved
Reserved
RW
-
-
0
I
2
C Table: Watchdog Timer Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
WD4
RW
-
-
1
Bit 3
WD3
RW
-
-
0
Bit 2
WD2
RW
-
-
0
Bit 1
WD1
RW
-
-
0
Bit 0
WD0
RW
-
-
0
I
2
C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 6
WDEN
Watchdog Enable
RW
Disable
Enable
0
Bit 5
WDFSEN
WD Safe Frequency
Mode
RW
Latched
FS/Byte0
WD B10
b(4:0)
0
Bit 4
WD SF4
RW
-
-
0
Bit 3
WD SF3
RW
-
-
0
Bit 2
WD SF2
RW
-
-
0
Bit 1
WD SF1
RW
-
-
0
Bit 0
WD SF0
RW
-
-
1
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8
N Divider Bit 8
RW
-
-
X
Bit 6
M Div6
RW
-
-
X
Bit 5
M Div5
RW
-
-
X
Bit 4
M Div4
RW
-
-
X
Bit 3
M Div3
RW
-
-
X
Bit 2
M Div2
RW
-
-
X
Bit 1
M Div1
RW
-
-
X
Bit 0
M Div0
RW
-
-
X
-
-
The decimal
representation of M Div
(6:0) + 2 is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
-
-
-
-
-
RW
Disable
Byte 11
Pin #
Name
-
Type
-
-
Writing to these bit will
configure the safe
frequency as Byte0 bit
(5:1)
-
-
-
-
0
Byte 10
Pin #
Bit 7
-
M/NEN
M/N Programming
Enable
Name
Type
Enable
-
-
-
-
-
-
-
-
-
-
Byte 9
Pin #
-
-
-
PWD
-
-
-
Byte 8
Pin #
Name
1
Type
0
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is 16 X 290ms
=4.64 seconds
Name
0
PWD
PWD
PWD
1
1
1
0
Type
0
9
ICS950403
Advance Information
0732--01/27/03
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div7
RW
-
-
X
Bit 6
N Div6
RW
-
-
X
Bit 5
N Div5
RW
-
-
X
Bit 4
N Div4
RW
-
-
X
Bit 3
N Div3
RW
-
-
X
Bit 2
N Div2
RW
-
-
X
Bit 1
N Div1
RW
-
-
X
Bit 0
N Div0
RW
-
-
X
I
2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
SSP7
RW
-
-
X
Bit 6
SSP6
RW
-
-
X
Bit 5
SSP5
RW
-
-
X
Bit 4
SSP4
RW
-
-
X
Bit 3
SSP3
RW
-
-
X
Bit 2
SSP2
RW
-
-
X
Bit 1
SSP1
RW
-
-
X
Bit 0
SSP0
RW
-
-
X
I
2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
SSP13
RW
-
-
X
Bit 4
SSP12
RW
-
-
X
Bit 3
SSP11
RW
-
-
X
Bit 2
SSP10
RW
-
-
X
Bit 1
SSP9
RW
-
-
X
Bit 0
SSP8
RW
-
-
X
I
2
C Table: Output Divider Control Register
Control
Function
Bit 7
PCI / HTTDiv3
RW
X
Bit 6
PCI / HTTDiv2
RW
X
Bit 5
PCI / HTTDiv1
RW
X
Bit 4
PCI / HTTDiv0
RW
X
Bit 3
CPU Div3
RW
X
Bit 2
CPU Div2
RW
X
Bit 1
CPU Div1
RW
X
Bit 0
CPU Div0
RW
X
-
CPU divider ratio can
be configured via these
4 bits individually.
See Table 2: Divider Ratio
Combination Table
-
-
-
PWD
-
PCICLK/HTTCLK
divider ratio can be
configured via these 4
bits individually.
See Table 2: Divider Ratio
Combination Table
-
-
-
Byte 15
Pin #
Name
Type
-
-
-
-
-
-
-
It is recommended to
use ICS Spread %
table for spread
programming.
PWD
-
Byte 14
Pin #
Name
Type
-
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
-
-
-
-
-
-
-
Byte 13
Pin #
Name
Type
Type
-
The decimal
representation of N Div
(8:0) + 8 is equal to
VCO divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
-
-
-
-
-
-
-
Byte 12
Pin #
Name
0
0
1
1
1
PWD
PWD
0
1
0
10
ICS950403
Advance Information
0732--01/27/03
Table 2: Divider Ratio Combination Table
Bit
00
01
10
11
MSB
1
2
4
8
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB Address Div Address Div Address Div Address
Div
Divider (3:2)
Divider (1:0)
I
2
C Table: Output Divider Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
X
Bit 6
Reserved
Reserved
RW
-
-
X
Bit 5
Reserved
Reserved
RW
-
-
X
Bit 4
Reserved
Reserved
RW
-
-
X
Bit 3
Reserved
Reserved
RW
-
-
X
Bit 2
Reserved
Reserved
RW
-
-
X
Bit 1
Reserved
Reserved
RW
-
-
X
Bit 0
Reserved
Reserved
RW
-
-
X
I
2
C Table: Output Divider Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
X
Bit 6
Reserved
Reserved
RW
-
-
X
Bit 5
Reserved
Reserved
RW
-
-
X
Bit 4
CPUINV
CPU Phase Invert
RW
Default
Inverse
X
Bit 3
Reserved
Reserved
RW
-
-
X
Bit 2
Reserved
Reserved
RW
-
-
X
Bit 1
Reserved
Reserved
RW
-
-
X
Bit 0
Reserved
Reserved
RW
-
-
X
I
2
C Table: Group Skew Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
Reserved
Reserved
RW
-
-
0
Bit 3
CPUSkw3
RW
0
Bit 2
CPUSkw2
RW
0
Bit 1
CPUSkw1
RW
0
Bit 0
CPUSkw0
RW
0
-
Byte 18
All other clocks -
CPUCLKT/C Skew
Control
-
-
-
-
See Table 3: 7-Steps Skew
Programming Table
PWD
-
-
-
Name
Type
0
1
-
-
-
Pin #
-
-
-
-
-
Byte 17
Pin #
Name
-
PWD
Type
0
1
-
-
-
-
PWD
-
-
-
Type
0
1
Byte 16
Pin #
Name
11
ICS950403
Advance Information
0732--01/27/03
Table 3: 7-Steps Skew Programming Table
7 Step
11
10
01
00
LSB
11
900 ps
750 ps
600 ps
450 ps
10
N/A
N/A
N/A
300 ps
01
N/A
N/A
N/A
150 ps
00
N/A
N/A
N/A
0.0 ps
MSB
I
2
C Table: Group Skew Control Register
Control
Function
Bit 7
PCISkw3
RW
0
Bit 6
PCISkw2
RW
0
Bit 5
PCISkw1
RW
0
Bit 4
PCISkw0
RW
0
Bit 3
PCI/HTTSkw3
RW
0
Bit 2
PCI/HTTSkw2
RW
0
Bit 1
PCI/HTTSkw1
RW
0
Bit 0
PCI/HTTSkw0
RW
0
I
2
C Table: Group Skew Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
1
Bit 6
Reserved
Reserved
RW
-
-
1
Bit 5
Reserved
Reserved
RW
-
-
1
Bit 4
Reserved
Reserved
RW
-
-
1
Bit 3
Reserved
Reserved
RW
-
-
1
Bit 2
Reserved
Reserved
RW
-
-
1
Bit 1
Reserved
Reserved
RW
-
-
1
Bit 0
Reserved
Reserved
RW
-
-
1
I
2
C Table: Slew Rate Control Register
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
Reserved
Reserved
RW
-
-
0
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
Reserved
Reserved
RW
-
-
0
Bit 4
Reserved
Reserved
RW
-
-
0
Bit 3
Reserved
Reserved
RW
-
-
0
Bit 2
Reserved
Reserved
RW
-
-
0
Bit 1
ASEL
Async Frequency
Select
RW
66.0MHz
75.4MHz
0
Bit 0
AEN
AGP/PCI/ Freq Source
Select
RW
Fix PLL
CPU PLL
1
CPU-PCICLK
/HTTCLK Skew Control
-
-
-
-
-
Byte 21
-
-
-
-
-
0
1
-
-
-
-
-
PWD
-
Byte 20
Pin #
Name
Type
-
-
-
-
See Table 3: 7-Steps Skew
Programming Table
Byte 19
Pin #
Type
CPU-PCICLK Skew
Control
0
PWD
1
Name
See Table 3: 7-Steps Skew
Programming Table
12
ICS950403
Advance Information
0732--01/27/03
I
2
C Table: Drive Strength Control Register
Control
Function
Bit 7
PCI9/HTT3 DrCntrl
PCICLK9/HTTCLK3
Drive Strength Control
RW
1X
2X
1
Bit 6
PCI6Drv
PCICLK6 Drive
Strength Control
RW
1X
2X
1
Bit 5
PCI3Drv
PCICLK3 Drive
Strength Control
RW
1X
2X
1
Bit 4
PCI2Drv
PCICLK2 Drive
Strength Control
RW
1X
2X
1
Bit 3
PCIFDrv
PCICLK_F Drive
Strength Control
RW
1X
2X
1
Bit 2
24_48Drv
24_48MHz Drive
Strength Control
RW
1X
2X
1
Bit 1
PCI8/HTT2 DrCntrl
PCICLK8/HTTCLK2
Drive Strength Control
RW
1X
2X
1
Bit 0
PCI7/HTT1 DrCntrl
PCICLK7/HTTCLK1
Drive Strength Control
RW
1X
2X
1
I
2
C Table: Slew Rate Control Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
1
Bit 6
Reserved
Reserved
RW
-
-
0
Bit 5
Reserved
Reserved
RW
-
-
1
Bit 4
Reserved
Reserved
RW
-
-
0
Bit 3
PCISlw1
RW
-
-
1
Bit 2
PCISlw0
RW
-
-
0
Bit 1
PCISlw1
RW
-
-
1
Bit 0
PCISlw0
RW
-
-
0
I
2
C Table: Slew Rate Control Register
Control
Function
Bit 7
REFSlw1
RW
-
-
1
Bit 6
REFSlw0
RW
-
-
0
Bit 5
48MSlw1
RW
-
-
1
Bit 4
48MSlw0
RW
-
-
0
Bit 3
Reserved
Reserved
RW
-
-
1
Bit 2
Reserved
Reserved
RW
-
-
0
Bit 1
Reserved
Reserved
RW
-
-
1
Bit 0
Reserved
Reserved
RW
-
-
1
48MHz Slew Rate
Control
PCICLK(1:0) Slew
Rate Control
PCICLK(10, 5:4) Slew
Rate Control
REF(2:0) Slew Rate
Control
0
1
-
PWD
-
Byte 24
Pin #
Name
Type
-
-
-
-
-
-
-
-
-
-
-
-
-
PWD
-
Byte 23
Pin #
Name
Type
-
-
1
0
-
-
-
-
PWD
-
-
Byte 22
Pin #
Name
Type
1
0
13
ICS950403
Advance Information
0732--01/27/03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+3.8 V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . 65C to +150C
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating
I
DD3.3OP66
C
L
= 0 pF; Select @ 66MHz
Supply Current
I
DD3.3OP100
C
L
= 0 pF; Select @ 100MHz
I
DD3.3OP133
C
L
= 0 pF; Select @ 133MHz
Power Down
PD
600
mA
Input frequency
F
i
V
DD
= 3.3 V;
10
14.318
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
3
ms
1
Guaranteed by design, not 100% tested in production.
180
mA
Input Capacitance
1
14
ICS950403
Advance Information
0732--01/27/03
Electrical Characteristics - CPUCLK
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
Z
O
V
O
= V
X
15
55
Output High Voltage
V
OH2B
1
1.2
V
Output Low Voltage
V
OL2B
0.4
V
Output Low Current
I
OL2B
V
OL
= 0.3 V
18
mA
Rise Edge Rate
1
Measured from 20-80%
2
7
V/ns
Fall Edge Rate
1
Measured from 80-20%
2
7
V/ns
V
DIFF
Differential Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
0.4
2.3
V
DV
DIFF
Change in V
DIFF_DC
magnitude, Measured @
the Hammer test load
(single-ended
measurement)
-150
150
mV
V
CM
Common Mode Voltage,
Measured @ the Hammer
test load (single-ended
measurement)
1.05
1.45
V
DV
CM
Change in Common Mode
Voltage, Measured @ the
Hammer test load (single-
ended measurement)
-200
200
mV
Duty Cycle
1
d
t2B
V
T
= 50%
45
53
%
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= V
X
0
200
ps
Notes:
1 - Guaranteed by design, not 100% tested in production.
3 - Vpullup
(external)
= 1.5V, Min = Vpullup
(external)
/2-150mV; Max=(Vpullup
(external)
/2)+150mV
2 - V
DIF
specifies the minimum input differential voltages (V
TR
-V
CP
) required for switching, where V
TR
is the "true"
input level and V
CP
is the "complement" input level.
15
ICS950403
Advance Information
0732--01/27/03
Electrical Characteristics - PCICLK/HTTCLK
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%; C
L
= 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
V
OH1
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 9.0 mA
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-15
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
10
mA
Rise Edge Rate
1
Measured from 20-60%
1
4
V/ns
Fall Edge Rate
1
Measured from 60-20%
1
4
V/ns
Duty Cycle
1
d
t1
V
T
= 50%
45
55
%
Jitter, Cycle-to-
cycle
1
t
jcyc-cyc2B
Measured on rising edge @ 1.5V
250
ps
Jitter, Accumulated
1
-1000
1000
ps
Output Impedance
Z
O
V
O
= V
X
12
55
W
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%; C
L
= 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
V
OH1
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 9.0 mA
0.4
V
Output High Current
I
OH1
V
OH
= 2.0 V
-15
mA
Output Low Current
I
OL1
V
OL
= 0.8 V
10
mA
Rise Edge Rate
1
Measured from 20-60%
1
4
V/ns
Fall Edge Rate
1
Measured from 60-20%
1
4
V/ns
Duty Cycle
1
d
t1
V
T
= 50%
45
55
%
Jitter, Cycle-to-
cycle
1
t
jcyc-cyc2B
Measured on rising edge @ 1.5V
250
ps
Jitter, Accumulated
1
-1000
1000
ps
Output Impedance
Z
O
V
O
= V
X
12
55
W
1
Guaranteed by design, not 100% tested in production.
16
ICS950403
Advance Information
0732--01/27/03
Electrical Characteristics - 24MHz, 48MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Edge Rate
1
Measured from 20-80%
0.5
2
V/ns
Fall Edge Rate
1
Measured from 80-20%
0.5
2
V/ns
Duty Cycle
1
d
t5
V
T
= 50%
45
55
%
Jitter, Absolute
1
t
jabs5
V
T
= 1.5 V
-1
1
ns
Jitter, Cycle-to-
cycle
1
t
jcyc-cyc2B
V
T
= V
X,
for 24_48MHz clock
0
500
ps
Jitter, Cycle-to-
cycle
1
t
jcyc-cyc2B
V
T
= V
X,
for 48MHz clock
0
200
ps
Output Impedance
Z
O
V
O
= V
X
20
60
W
Electrical Characteristics - REF
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output High Voltage
V
OH5
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 9 mA
0.4
V
Output High Current
I
OH5
V
OH
= 2.0 V
-22
mA
Output Low Current
I
OL5
V
OL
= 0.8 V
16
mA
Rise Edge Rate
1
Measured from 20-80%
0.5
2
V/ns
Fall Edge Rate
1
Measured from 80-20%
0.5
2
V/ns
Duty Cycle
1
d
t5
V
T
= 50%
45
55
%
Jitter, Cycle-to-
cycle
1
t
jcyc-cyc2B
Mesured on rising edge @ 1.5V
0
1000
ps
Jitter, Accumulated
1
-1000
1000
ps
1
Guaranteed by design, not 100% tested in production.
17
ICS950403
Advance Information
0732--01/27/03
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS950403
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of Power-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
18
ICS950403
Advance Information
0732--01/27/03
Ordering Information
ICS950403yFT
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Example:
ICS XXXXXX y F - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
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