Integrated
Circuit
Systems, Inc.
ICS95V857 -XXX
0674Q--08/03/04
Block Diagram
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Pin Configuration
48-Pin TSSOP/TVSOP
Recommended Application:
DDR Memory Modules / Zero Delay Board Fan Out
Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_2)
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum-tolerant inputs
Auto PD when input signal removed
Choice of static phase offset available,
for easy board tuning;
-XXX = device pattern number for options listed
below.
- ICS95V857 ............. 0ps
- ICS95V857-130 .. +50ps
Specifications:
Meets PC3200 Class A+ specification for DDR-I 400
support
Covers all DDRI speed grades
Switching Characteristics:
CYCLE - CYCLE jitter: <50ps
OUTPUT - OUTPUT skew: <40ps
Period jitter: 30ps
S
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Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS95V857-XXX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
ICS95V857-XXX
0674Q--08/03/04
Pin Configuration
40-Pin MLF
56-Ball BGA
Top View
GND
CLKC2
CLKT2
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
VDD
FB_OUTC
FB_OUTT
CLKC3
CLKT3
VDD
CLKT4
CLKC4
CLKC9
CLKT9
VDD
CLKT8
CLKC8
CLKC1
CLKT1
VDD
CLKT0
CLKC0
CLKC5
CLKT5
VDD
CLKT6
CLKC6
1
10
11
20
21
31
30
40
ICS95V857
A
B
1
2
3
4
5
6
C
D
E
F
G
H
J
K
1
2
3
4
5
6
A
CLKT0
CLKC0
GND
GND
CLKC5
CLKT5
B
CLKC1
CLKT1
VDD
VDD
CLKT6
CLKC6
C
GND
GND
NC
NC
GND
GND
D
CLKT2
CLKC2
NC
NC
CLKC7
CLKT7
E
VDD
VDD
NB
NB
VDD
PD#
F
CLK_INT
CLK_INC
NB
NB
FB_INC
FB_INT
G
VDD
AVDD
NC
NC
FB_OUTC
VDD
H
AGND
GND
NC
NC
GND
FB_OUTT
J
CLKC3
CLKT3
VDD
VDD
CLKT8
CLKC8
K
CLKT4
CLKC4
GND
GND
CLKC9
CLKT9
3
ICS95V857 -XXX
0674Q--08/03/04
Pin Descriptions
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This PLL Clock Buffer is designed for a V
DD
of 2.5V, an AV
DD
of 2.5V and differential data input and output levels.
The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The
ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V857 is characterized for operation from 0C to 85C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
4
ICS95V857-XXX
0674Q--08/03/04
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 4.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+ 0.5 V
Ambient Operating Temperature . . . . . . . . . . 0C to +85C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 85C; Supply Voltage A
VDD
, V
DD
= 2.5V 0.2V
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
I
IH
V
I
= V
DD
or GND
5
A
Input Low Current
I
IL
V
I
= V
DD
or GND
5
A
I
DD2.5
C
L
= 0pf @ 200MHz
148
170
mA
I
DDPD
C
L
= 0pf
100
A
Output High Current
I
OH
V
DD
= 2.3V, V
OUT
= 1V
-18
-32
mA
Output Low Current
I
OL
V
DD
= 2.3V, V
OUT
= 1.2V
26
35
mA
High Impedance
Output Current
I
OZ
V
DD
=2.7V, Vout=V
DD
or GND
10
mA
Input Clamp Voltage
V
IK
V
DDQ
= 2.3V Iin = -18mA
-1.2
V
V
DD
= min to max,
I
OH
= -1 mA
V
DDQ
- 0.1
V
V
DDQ
= 2.3V,
I
OH
= -12 mA
1.7
V
V
DD
= min to max
I
OL
=1 mA
0.1
V
V
DDQ
= 2.3V
I
OH
=12 mA
0.6
V
Input Capacitance
1
C
IN
V
I
= GND or V
DD
3
pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DD
3
pF
1
Guaranteed by design at 220MHz, not 100% tested in production.
Operating Supply
Current
High-level output
voltage
V
OH
Low-level output voltage
V
OL
5
ICS95V857 -XXX
0674Q--08/03/04
Recommended Operating Condition (see note1)
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
DD
, A
VDD
2.3
2.5
2.7
V
CLKT, CLKC, FB_INC
0.4
V
DD
/2 - 0.18
V
PD#
-0.3
0.7
V
CLKT, CLKC, FB_INC
V
DD
/2 + 0.18
2.1
V
PD#
1.7
V
DD
+ 0.6
V
DC input signal voltage
(note 2)
V
IN
-0.3
V
DD
+ 0.3
V
DC - CLKT, FB_INT
0.36
V
DD
+ 0.6
V
AC - CLKT, FB_INT
0.7
V
DD
+ 0.6
V
Output differential cross-
voltage (note 4)
V
OX
V
DD
/2 - 0.15
V
DD
/2 + 0.15
V
Input differential cross-
voltage (note 4)
V
IX
V
DD
/2 - 0.2
V
DD
/2
V
DD
/2 + 0.2
V
High level output
current
I
OH
-6.4
mA
Low level output current
I
OL
5.5
mA
Operating free-air
temperature
T
A
0
85
C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage
V
IL
High level input voltage
V
IH
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VT is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of V
DD
and is the
voltage at which the differential signal must be crossing.
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