Integrated
Circuit
Systems, Inc.
ICS97U877
0792A--04/15/04
Block Diagram
1.8V Wide Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Switching Characteristics:
Period jitter: 40ps
Half-period jitter: 60ps
CYCLE - CYCLE jitter 40ps
OUTPUT - OUTPUT skew: 40ps
A
B
1
2
3
4
5
6
C
D
E
F
G
H
J
K
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
OS
CLKT3
CLKC3
CLKC4
CLKT4
VDDQ
CLKT9
CLKC9
CLKC8
CLKT8
VDDQ
CLKC1
CLKT1
CLKT0
CLKC0
VDDQ
CLKC5
CLKT5
CLKT6
CLKC6
VDDQ
1
10
11
20
21
31
30
40
ICS97U877
52-Ball BGA
Top View
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
AV
DD
FB_INT
CLK_INT
CLK_INC
FB_INC
PLL
Powerdown
Control and
Test Logic
OE
LD* or OE
PLL bypass
LD*
LD*, OS or OE
OS
GND
10K-100k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
1
2
3
4
5
6
A
CLKT1
CLKT0
CLKC0
CLKC5
CLKT5
CLKT6
B
CLKC1
GND
GND
GND
GND
CLKC6
C
CLKC2
GND
NB
NB
GND
CLKC7
D
CLKT2
VDDQ
VDDQ
VDDQ
OS
CLKT7
E
CLK_INT
VDDQ
NB
NB
VDDQ
FB_INT
F
CLK_INC
VDDQ
NB
NB
OE
FB_INC
G
AGND
VDDQ
VDDQ
VDDQ
VDDQ
FB_OUTC
H
AVDD
GND
NB
NB
GND
FB_OUTT
J
CLKT3
GND
GND
GND
GND
CLKT8
K
CLKC3
CLKC4
CLKT4
CLKT9
CLKC9
CLKC8
2
ICS97U877
0792A--04/15/04
Pin Descriptions
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The PLL clock buffer, ICS97U877, is designed for a V
DDQ
of 1.8 V, a AV
DD
of 1.8 V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U877 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the
LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND or V
DDQ
. When OS is high, OE will function as described above. When OS is low,
OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
DD
is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
STAB
.
The PLL in ICS97U877 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS97U877
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U877 is characterized for operation from 0C to 70C.
3
ICS97U877
0792A--04/15/04
Function Table
s
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I
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O
L
L
P
D
D
V
A
E
O
S
O
T
N
I
_
K
L
C
T
N
I
_
K
L
C
T
K
L
C
C
K
L
C
T
T
U
O
_
B
F
C
T
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O
_
B
F
D
N
G
H
X
L
H
L
H
L
H
f
f
O
/
d
e
s
s
a
p
y
B
D
N
G
H
X
H
L
H
L
H
L
f
f
O
/
d
e
s
s
a
p
y
B
D
N
G
L
H
L
H
)
Z
(
L
*
)
Z
(
L
*
L
H
f
f
O
/
d
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s
s
a
p
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B
D
N
G
L
L
H
L
,
)
Z
(
L
*
7
T
K
L
C
e
v
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t
c
a
,
)
Z
(
L
*
7
C
K
L
C
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L
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f
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/
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B
)
m
o
n
(
V
8
.
1
L
H
L
H
)
Z
(
L
*
)
Z
(
L
*
L
H
n
O
)
m
o
n
(
V
8
.
1
L
L
H
L
,
)
Z
(
L
*
7
T
K
L
C
e
v
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t
c
a
,
)
Z
(
L
*
7
C
K
L
C
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v
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t
c
a
H
L
n
O
)
m
o
n
(
V
8
.
1
H
X
L
H
L
H
L
H
n
O
)
m
o
n
(
V
8
.
1
H
X
H
L
H
L
H
L
n
O
)
m
o
n
(
V
8
.
1
X
X
L
L
)
Z
(
L
*
)
Z
(
L
*
)
Z
(
L
*
)
Z
(
L
*
f
f
O
)
m
o
n
(
V
8
.
1
X
X
H
H
d
e
v
r
e
s
e
R
*L(Z) means the outputs are disabled to a low stated meeting the I
ODL
limit.
4
ICS97U877
0792A--04/15/04
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . . -0.5V to 2.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.5V to V
DDQ
+ 0.5V
Ambient Operating Temperature . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Current
(CLK_INT, CLK_INC)
I
IH
V
I
= V
DDQ
or GND
250
A
Input Low Current (OE,
OS, FB_INT, FB_INC)
I
IL
V
I
= V
DDQ
or GND
10
A
Output Disabled Low
Current
I
ODL
OE = L, V
ODL
= 100mV
100
A
I
DD1.8
C
L
= 0pf @ 270MHz
300
mA
I
DDLD
C
L
= 0pf
500
A
Input Clamp Voltage
V
IK
V
DDQ
= 1.7V Iin = -18mA
-1.2
V
I
OH
= -100
A
V
DDQ
- 0.2
V
I
OH
= -9 mA
1.1
1.45
V
I
OL
=100
A
0.25
0.10
V
I
OL
=9 mA
0.6
V
Input Capacitance
1
C
IN
V
I
= GND or V
DDQ
2
3
pF
Output Capacitance
1
C
OUT
V
OUT
= GND or V
DDQ
2
3
pF
1
Guaranteed by design, not 100% tested in production.
Operating Supply
Current
High-level output voltage
V
OH
Low-level output voltage
V
OL
5
ICS97U877
0792A--04/15/04
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4.
Differential cross-point voltage is expected to track variations of V
DDQ
and is the
voltage at which the differential signal must be crossing.
Recommended Operating Condition (see note1)
T
A
= 0 - 70C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
V
DDQ
, A
VDD
1.7
1.8
1.9
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.35 x V
DDQ
V
OE, OS
0.35 x V
DDQ
V
CLK_INT, CLK_INC, FB_INC,
FB_INT
0.65 x V
DDQ
V
OE, OS
0.65 x V
DDQ
V
DC input signal voltage (note
2)
V
IN
-0.3
V
DDQ
+ 0.3
V
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
V
DDQ
+ 0.4
V
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.6
V
DDQ
+ 0.4
V
Output differential cross-
voltage (note 4)
V
OX
V
DDQ
/2 - 0.10
V
DDQ
/2 + 0.10
V
Input differential cross-
voltage (note 4)
V
IX
V
DDQ
/2 - 0.15
V
DD
/2
V
DDQ
2 + 0.15
V
High level output current
I
OH
-9
mA
Low level output current
I
OL
9
mA
Operating free-air
temperature
T
A
0
70
C
Differential input signal
voltage (note 3)
V
ID
Low level input voltage
V
IL
High level input voltage
V
IH
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