M2006-02/-12 PB Rev 2.2
Revised 06Jul2004
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
N e t w o r k i n g & C o m m u n i c a t i o n s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M2006-02/-12
VCSO B
ASED
FEC C
LOCK
PLL / H
ITLESS
S
WITCHING
O
PTION
Integrated
Circuit
Systems, Inc.
P r o d u c t B r i e f
G
ENERAL
D
ESCRIPTION
The M2006-02 and -12 are VCSO (Voltage Controlled
SAW Oscillator) based clock generator PLLs designed
for clock frequency translation and jitter attenuation.
They support both forward and inverse FEC (Forward
Error Correction) clock multiplication ratios, which are
pin-selected from pre-programming look-up tables.
The M2006-12 adds Hitless Switching and Phase
Build-out to enable SONET (GR-253) / SDH (G.813)
MTIE and TDEV compliance during reference clock
reselection. Hitless Switching (HS) engages when a
4ns or greater clock phase change is detected.
This phase-change triggered implementation of HS
is not recommended when using an unstable
reference (more than 1ns jitter pk-to-pk) or when the
resulting phase detector frequency is less than
5MHz. Refer to full product data sheet for more
information.
F
EATURES
Pin-selectable PLL divider ratios support forward
and inverse FEC ratio translation, including:
255/238 (OTU1) Mapping and 238/255 De-mapping
255/237 (OTU2) Mapping and 237/255 De-mapping
255/236 (OTU3) Mapping and 236/255 De-mapping
Supports input reference and VCSO frequencies up
to 700MHz, supports loop timing modes
(Specify VCSO frequency at time of order)
Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
M2006-12 includes
APC
pin for Phase Build-out
function (for absorption of the input phase change)
Commercial and Industrial temperature grades
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
S
IMPLIFIED
B
LOCK
D
IAGRAM
Example I/O Clock Frequency Combinations
Using
M2006-02/-12-622.0800 and
Inverse FEC Ratios
FEC PLL Ratio
Mfec / Rfec
Base Input Rate
1
(MHz)
Note 1: Input reference clock can be the base frequency shown
divided by "Mfin", as shown in the following table.
Output Clock
(either output)
MHz
1/1
622.0800
622.08
or
155.52
238/255
666.5143
237/255
669.3266
236/255
672.1627
Mfin Divider and Example Input Frequencies
FIN_SEL1:0
Mfin Value
For Base Input Rate of 622.0800
Sample Ref. Freq. (MHz)
1
1
1
622.08
1
0
4
155.52
0
1
8
77.76
0
0
32
19.44
M 2 0 0 6 - 0 2
M 2 0 0 6 - 1 2
( T o p V i e w )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
F
I
N
_
SEL
1
GN
D
NC
or
AP
C
DI
F
_RE
F
0
n
D
I
F
_RE
F
0
RE
F
_
S
E
L
DI
F
_RE
F
1
n
D
I
F
_RE
F
1
VC
C
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
nOP
_
I
N
O
P
_O
UT
VC
nV
C
nOP
_
OU
T
OP
_
I
N
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
Rfec Div
Mfec Div
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
FIN_SEL1:0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
P0_SEL
P1_SEL
VCSO
0
1
M2006-02 / M2006-12
FOUT0
nFOUT0
FOUT1
nFOUT1
FEC_SEL3:0
4
2
APC
M2006-12 only
P0 Div
(1 or 4)
Mfin Div
(1, 4, 8, or 32)
P1 Div
(1 or 4)
Loop
Filter
M2006-02/-12 VCSO Based FEC Clock PLL / Hitless Switching
PDF 
ZIP