ICS557-05A
MDS 557-05A E
1
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
Quad Differential PCI-Express Clock Source
Description
The ICS557-05A is a spread-spectrum clock generator
that supports PCI-Express requirements. It is used in
PC or embedded systems to substantially reduce
electro-magnetic interference (EMI). The device
provides four differential HCSL or LVDS high-frequency
outputs with spread spectrum capability. The output
frequency and spread type are selectable using
external pins.
Features
Packaged in 20-pin TSSOP
Available in Pb (lead) free package
Supports PCI-Express applications
Four differential spread spectrum clock outputs
Spread spectrum for EMI reduction
Uses external 25 MHz clock or crystal input
Power down pin turns off chip
OE control tri-states outputs
Spread and frequency selection via external pins
Spread Bypass option available
Industrial temperature range available
Block Diagram
Spread
Spectrum/
Output
clock
selection
CLKOUTA
CLKOUTA
Rr(IREF)
PLL Clock
Synthesis
3
GND
VDD
Clock
Oscillator
X1
SEL[2:0]
Spread
Spectrum
Circuitry
2
2
CLKOUTB
CLKOUTD
X2
25 MHz
crystal or
clock
OE
PD
Optional tuning crystal
capacitors
CLKOUTD
CLKOUTC
CLKOUTC
CLKOUTB
Quad Differential PCI-Express Clock Source
MDS 557-05A E
2
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Pin Assignment
Spread Spectrum Selection Table
13
4
12
5
11
X1
8
9
10
GNDODA
OE
CLKC
CLKD
GNDXD
CLKD
17
16
IREF
3
S1
S2
CLKB
18
CLKB
1
VDDXD
S0
CLKA
20
CLKA
19
14
2
7
X2
PD
VDDODA
CLKC
15
6
20-pin (173 mil) TSSOP
S2
S1
S0
Spread%
Spread Type
Output
Frequency (MHz)
0
0
0
-0.5
Down
100
0
0
1
-1.0
Down
100
0
1
0
-1.5
Down
100
0
1
1
No Spread Not Applicable
100
1
0
0
-0.5
Down
200
1
0
1
-1.0
Down
200
1
1
0
-1.5
Down
200
1
1
1
No Spread Not Applicable
200
Quad Differential PCI-Express Clock Source
MDS 557-05A E
3
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Pin Descriptions
Pin
Pin
Name
Pin
Type
Pin Description
1
VDDXD
Power
Connect to +3.3 V digital supply.
2
S0
Input
Spread spectrum select pin #0. See table above. Internal pull-up resistor.
3
S1
Input
Spread spectrum select pin #1. See table above Internal pull-up resistor.
4
S2
Input
Spread spectrum select pin #2. See table above. Internal pull-up resistor.
5
X1
Input
Crystal connection. Connect to a fundamental mode crystal or clock input.
6
X2
Output
Crystal connection. Connect to a fundamental mode crystal or leave open.
7
PD
Input
Powers down all PLL's and tri-states outputs when low. Internal pull-up resistor.
8
OE
Input
Provides output on, tri-states output (High = enable outputs; Low = disable outputs).
Internal pull-up resistor.
9
GND
Power
Connect to digital ground.
10
IREF
Output
Precision resistor attached to this pin is connected to the internal current reference.
11
CLKD
Output
Selectable 100/200 MHz spread spectrum differential Compliment output clock D.
12
CLKD
Output
Selectable 100/200 MHz spread spectrum differential True output clock D.
13
CLKC
Output
Selectable 100/200 MHz spread spectrum differential Compliment output clock C.
14
CLKC
Output
Selectable 100/200 MHz spread spectrum differential True output clock C.
15
VDDODA
Power
Connect to +3.3 V analog supply.
16
GND
Power
Connect to analog ground.
17
CLKB
Output
Selectable 100/200 MHz spread spectrum differential Compliment output clock B.
18
CLKB
Output
Selectable 100/200 MHz spread spectrum differential True output clock B.
19
CLKA
Output
Selectable 100/200 MHz spread spectrum differential Compliment output clock A.
20
CLKA
Output
Selectable 100/200 MHz spread spectrum differential True output clock A.
Quad Differential PCI-Express Clock Source
MDS 557-05A E
4
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-05A must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Each 0.01F decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via. Distance of the ferrite
bead and bulk decoupling from the device is less
critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS557-05A.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
External Components
A minimum number of external components are
required for proper operation. Decoupling capacitors of
0.01
F should be connected between VDD and GND
pairs (1,9 and 15,16) as close to the device as possible.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (C
L
-12)*2 in this equation,
C
L
=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Current Reference Source R
r
(Iref)
If board target trace impedance (Z) is 50
, then Rr =
475
(1%), providing IREF of 2.32 mA, output current
(I
OH
) is equal to 6*IREF.
Load Resistors R
L
Since the clock outputs are open source outputs, 50
ohm external resistors to ground are to be connected at
each clock output.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-05A are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-05A can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
Quad Differential PCI-Express Clock Source
MDS 557-05A E
5
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1. Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
2. No vias should be used between decoupling
capacitor and VDD pin.
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the
ICS557-05A.This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5
Quad Differential PCI-Express Clock Source
MDS 557-05A E
6
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
PCI-Express Layout Guidelines
PCI-Express Device Routing
Typical PCI-Express (HCSL)
Waveform
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
S
33
ohm
R
T
49.9
ohm
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express Connector
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max inch
R
S
R
S
R
T
R
T
PCI-Express
Load or
Connector
L1
L2
L3'
L4
L1'
L2'
L3
L4'
ICS557-05A
Output
Clock
0.175 V
0.52 V
0.175 V
0.52 V
t
OR
t
OF
500 ps
500 ps
700 mV
0
Quad Differential PCI-Express Clock Source
MDS 557-05A E
7
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
LVDS Compatible Layout Guidelines
LVDS Device Routing
Typical LVDS Waveform
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
P
100
ohm
R
Q
100
ohm
R
T
150
ohm
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
L1
L2'
L3
L1'
L2
L3'
R
Q
R
P
LVDS
Device
Load
ICS557-05A
Clock
Output
R
T
R
T
1150 mV
1250 mV
t
OR
t
OF
500 ps
500 ps
1325 mV
1000 mV
1150 mV
1250 mV
Quad Differential PCI-Express Clock Source
MDS 557-05A E
8
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-05A. These ratings
are stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85
C
1
Single edge is monotonic when transitioning through region.
2
Inputs with pull-ups/-downs are not included.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70
C
Ambient Operating Temperature (industrial)
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
125
C
Soldering Temperature
260
C
ESD Protection (Input)
2000 V min. (HBM)
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Supply Voltage
V
3.135
3.465
Input High Voltage
1
V
IH
2.0
VDD +0.3
V
Input Low Voltage
1
V
IL
VSS-0.3
0.8
V
Input Leakage Current
2
I
IL
0 < Vin < VDD
-5
5
A
Operating Supply Current
I
DD
50
, 2pF load@ 100MHz
105
mA
I
DDOE
OE =Low
40
mA
I
DDPD
No load, PD =Low
500
A
Input Capacitance
C
IN
Input pin capacitance
7
pF
Output Capacitance
C
OUT
Output pin capacitance
6
pF
Pin Inductance
L
PIN
5
nH
Output Resistance
Rout
CLK outputs
3.0
k
Pull-up Resistance
R
PUP
OE, SEL, PD pins
110
k
Quad Differential PCI-Express Clock Source
MDS 557-05A E
9
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
AC Electrical Characteristics - CLKOUTA/CLKOUTB
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85
C
1
Test setup is R
L
=50 ohms with 2 pF, Rr = 475
(1%).
2
Measurement taken from a single-ended waveform.
3
Measurement taken from a differential waveform.
4
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5
CLKOUT pins are tri-stated when OE is low. asserted. CLKOUT is driven differential when OE is high unless its
PD= low.
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
25
MHz
Output Frequency
HCSL termination
200
MHz
LVDS termination
100
MHz
Output High Voltage
1,2
V
OH
660
700
850
mV
Output Low Voltage
1,2
V
OL
-150
0
mV
Crossing Point
Voltage
1,2
Absolute
250
350
550
mV
Crossing Point
Voltage
1,2,4
Variation over all edges
140
mV
Jitter, Cycle-to-Cycle
1,3
60
ps
Modulation Frequency
Spread spectrum
30
31.5
33
kHz
Rise Time
1,2
t
OR
From 0.175 V to 0.525 V
175
332
700
ps
Fall Time
1,2
t
OF
From 0.525 V to 0.175 V
175
344
700
ps
Skew between outputs
At crossing point Voltage
50
ps
Duty Cycle
1,3
45
55
%
Output Enable Time
5
All outputs
10
us
Output Disable Time
5
All outputs
10
us
Power-up Time
t
STABLE
From power-up VDD=3.3 V
3.0
ms
Spread Change Time
t
SPREAD
Settling period after spread change
3.0
ms
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
JA
Still air
93
C/W
JA
1 m/s air flow
78
C/W
JA
3 m/s air flow
65
C/W
Thermal Resistance Junction to Case
JC
20
C/W
Quad Differential PCI-Express Clock Source
MDS 557-05A E
10
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
PCI-Express Layout Guidelines
PCI-Express Device Routing
Typical PCI-Express (HCSL) Waveform
Common Recommendations for Differential Routing
Dimension or Value
Unit
L1 length, Route as non-coupled 50 ohm trace.
0.5 max
inch
L2 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
L3 length, Route as non-coupled 50 ohm trace.
0.2 max
inch
R
S
33
ohm
R
T
49.9
ohm
Differential Routing on a Single PCB
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
2 min to 16 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
1.8 min to 14.4 max
inch
Differential Routing to a PCI Express Connector
Dimension or Value
Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
0.25 to 14 max
inch
L4 length, Route as coupled stripline 100 ohm differential trace.
0.225 min to 12.6 max inch
R
S
R
S
R
T
R
T
PCI-Express
Load or
Connector
L1
L2
L3'
L4
L1'
L2'
L3
L4'
ICS557-03
Output
Clock
0.175 V
0.52 V
0.175 V
0.52 V
t
OR
t
OF
500 ps
500 ps
700 mV
0
Quad Differential PCI-Express Clock Source
MDS 557-05A E
11
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Package Outline and Package Dimensions
(20-pin TSSOP, 173 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
INDEX
AREA
1 2
20
D
E1
E
SEATING
PLANE
A1
A
A2
e
- C -
b
aaa
C
c
L
*For reference only. Controlling dimensions in mm.
Millimeters
Inches*
Symbol
Min
Max
Min
Max
A
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
c
0.09
0.20
0.0035
0.008
D
6.40
6.60
0.252
0.260
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
0
8
0
8
aaa
--
0.10
--
0.004
Quad Differential PCI-Express Clock Source
MDS 557-05A E
12
Revision 011606
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
www.icst.com
ICS557-05A
Ordering Information
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
ICS557G-05A
ICS557G-05A
Tubes
20-pin TSSOP
0 to +70
C
ICS557G-05ATR
ICS557G-05A
Tape and Reel
20-pin TSSOP
0 to +70
C
ICS557G-05ALF
557G-05ALF
Tubes
20-pin TSSOP
0 to +70
C
ICS557G-05ALFTR
557G-05ALF
Tape and Reel
20-pin TSSOP
0 to +70
C
ICS557GI-05A
557GI-05A
Tubes
20-pin TSSOP
-40 to +85
C
ICS557GI-05ATR
557GI-05A
Tape and Reel
20-pin TSSOP
-40 to +85
C
ICS557GI-05ALF
557GI05ALF
Tubes
20-pin TSSOP
-40 to +85
C
ICS557GI-05ALFTR
557GI05ALF
Tape and Reel
20-pin TSSOP
-40 to +85
C
PDF 
ZIP