8344BY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 19, 2002
1
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8344 is a low voltage, low skew, 1-to-24
Differential-to-LVCMOS Fanout Buffer and a mem-
ber of the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS8344 is designed
to translate any differential signal levels to LVCMOS
levels. The low impedance LVCMOS outputs are designed to
drive 50
series or parallel terminated transmission lines. The
effective fanout can be increased to 48 by utilizing the ability of
the outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual clock
inputs also facilitate board level testing. ICS8344 is character-
ized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output
operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS8344 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
F
EATURES
24 LVCMOS outputs, 7
typical output impedance
Selectable differential clock input pairs for redundant
clock applications
CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 167MHz
Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS without external bias networks
Translates any single-ended input signal to LVCMOS
with resistor bias on nCLK input
Multiple output enable pins for disabling unused outputs
in reduced fanout applications
Output skew: 275ps (maximum)
Part-to-part skew: 600ps (maximum)
Bank skew: 150ps (maximum)
Propagation Delay: 4.3ns (maximum)
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
OE1
OE2
OE3
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
Q8
Q9
VDDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
CLK0
nCLK0
OE1
OE2
OE3
Q0 - Q7
O8 - Q15
O16 - Q23
CLK_SEL
CLK1
nCLK1
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8344
HiPerClockSTM
,&6
0
1
8344BY
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 19, 2002
4
Integrated
Circuit
Systems, Inc.
ICS8344
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
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