Document Outline
- General Description
- Features
- Frequency Select Function Table
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Frequency Select Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V Core DC Characteristics
- Power Supply 2.5V DC Characteristics
- LVCMOS DC Characteristics
- Crystal Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Typical Phase Noise at 53.125MHz @ 3.3V
- Typical Phase Noise at 212.5MHz @ 3.3V
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- 3.3V/2.5V Output Load AC Test Circuit Diagram
- 2.5V Output Load AC Test Circuit Diagram
- RMS Phase Jitter Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- Output Duty Cycle/Pulse Width/Period Diagram
- Application Information
- Power Supply Filtering Techniques
- Crystal Input Interface
- Layout Guideline
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
1
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS840002I is a 2 output LVCMOS/LVTTL
Synthesizer optimized to generate Fibre Channel
reference clock frequencies and is a member of
the HiPerClocks
TM
family of high performance
clock solutions from ICS. Using a 26.5625MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
212.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, and
53.125MHz. The ICS840002I uses ICS' 3
rd
generation low phase
noise VCO technology and can achieve 1ps or lower typical
rms phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS840002I is packaged in a 16-pin TSSOP package.
HiPerClockSTM
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
ICS840002I
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
F
EATURES
Two LVCMOS outputs @ 3.3V, 17
typical output impedance
Selectable crystal oscillator interface
or LVCMOS single-ended input
Output frequency range: 46.66MHz - 233.33MHz
VCO range: 560MHz - 700MHz
Supports the following output frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
RMS phase jitter @ 212.5MHz (637KHz - 10MHz):
0.83ps (typical)
Typical phase noise at 212.5MHz:
Offset
Noise Power
100Hz ............... -91.3 dBc/Hz
1KHz .............. -114.3 dBc/Hz
10KHz .............. -120.7 dBc/Hz
100KHz .............. -120.2 dBc/Hz
Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40C to 85C ambient operating temperature
Lead-Free package RoHS compliant
Q0
Q1
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
XTAL_IN
XTAL_OUT
TEST_CLK
MR
OSC
Phase
Detector
VCO
M = 24 (fixed)
F_SEL1:0
0 0 3
0 1 4
1 0 6
1 1 12
(default)
0
1
1
0
2
N
26.5625MHz
Pullup
Pulldown
Pulldown
Pulldown
Pullup:Pullup
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REQUENCY
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1
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
2
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
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IN
D
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Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
3
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
+ 0.5V
Package Thermal Impedance,
JA
89C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
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S
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DC C
HARACTERISTICS
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OR
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TO
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5
A
m
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
4
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
5. C
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C
HARACTERISTICS
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4C. LVCMOS/LVTTL DC C
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OR
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OR
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DD
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= 3.3V5%, V
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= 2.5V5%, T
A
= -40C
TO
85C
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
5
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= -40C
TO
85C
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V5%, V
DDO
= 2.5V5%, T
A
= -40C
TO
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:
3
E
T
O
N
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
6
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
6C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V5%, T
A
= -40C
TO
85C
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T
O
N
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
7
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE
AT
53.125MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
53.125MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.68ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel Filter to raw data
Raw Phase Noise Data
Fibre Channel Filter
100
1k
10k
100k
1M
10M
100M
T
YPICAL
P
HASE
N
OISE
AT
212.5MH
Z
@3.3V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
212.5MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.83ps (typical)
O
FFSET
F
REQUENCY
(H
Z
)
N
OISE
P
O
WER
dBc
Hz
Phase Noise Result by adding
Fibre Channel to raw data
Raw Phase Noise Data
Fibre Channel Filter
100
1k
10k
100k
1M
10M
100M
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
8
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
Q0, Q1
RMS P
HASE
J
ITTER
O
UTPUT
S
KEW
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
DD
,
V
DDA
, V
DDO
GND
Phase Noise Mask
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise P
o
w
er
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
O
UTPUT
R
ISE
/F
ALL
T
IME
SCOPE
Qx
LVCMOS
2.05V5%
-1.25V5%
V
DD
,
V
DDA
GND
1.25V5%
V
DDO
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
V
DD
,
V
DDA
, V
DDO
GND
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
9
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
A
PPLICATION
I
NFORMATION
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS840002I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1 illustrates how
a 10
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA
.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
1. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V or 2.5V
.01
F
V
DD
C
RYSTAL
I
NPUT
I
NTERFACE
The ICS840002I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2
Figure 2. C
RYSTAL
I
NPU
t I
NTERFACE
below were determined using a 26.5625MHz 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
ICS840002I
C1
22p
X1
18pF Parallel Crystal
C2
22p
XTAL_OUT
XTAL_IN
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
10
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
L
AYOUT
G
UIDELINE
Figure 3 shows a schematic example of the ICS840002I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used. The C1=22pF
F
IGURE
3. ICS840002I S
CHEMATIC
E
XAMPLE
and C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1K
pullup or pulldown re-
sistors can be used for the logic control input pins.
XTAL1
Optional Termination
RD1
Not Install
RU1
1K
VDD
C4
0.01u
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Zo = 50 Ohm
LVCMOS
Set Logic
Input to
'0'
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
R1
10
R4
100
To Logic
Input
pins
Set Logic
Input to
'1'
Logic Control Input Examples
R2
33
C6
0.1u
VDDA
C2
22pF
To Logic
Input
pins
Zo = 50 Ohm
X1
VDD
RD2
1K
C5
0.1u
C3
10uF
VDD
R3
100
VDD
LVCMOS
XTAL2
U1
ICS840002i
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
XTAL_OUT
XTAL_IN
VDDO
Q1
Q0
GND
GND
FSEL1
RU2
Not Install
VDD
C1
22pF
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
11
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS840002I is: 3085
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
16 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
137.1C/W
118.2C/W
106.8C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0C/W
81.8C/W
78.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
12
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
16 L
EAD
TSSOP
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MO-153
L
O
B
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Y
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1
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-
-
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2
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1
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0
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1
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0
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4
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0
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7
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0
0
8
a
a
a
-
-
0
1
.
0
Integrated
Circuit
Systems, Inc.
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
13
ICS840002I
F
EMTO
C
LOCKS
TM C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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The aforementioned trademarks, HiPerClockSTM and F
EMTO
C
LOCKS
TM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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