Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Functional Description
- Parallel & Serial Load Operations Diagram
- Pin Descriptions
- Pin Characteristics
- Parallel & Serial Mode Function Table
- Programmable VCO Frequency Function Table
- Programmable Output Divider Function Table
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- LVPECL DC Characteristics
- Input Frequency Characteristics
- AC Characteristics
- Parameter Measurement Information
- 3.3V Output Load AC Test Circuit Diagram
- Differential Input Level Diagram
- Period Jitter Diagram
- Cycle-to-Cycle Jitter Diagram
- Output Skew Diagram
- Output Rise/Fall Time Diagram
- odc & tPeriod Diagram
- Application Information
- Storage Area Networks
- Common SANs Application Frequencies Table
- Configuration Details for SANs Applications Table
- Power Supply Filtering Techniques
- Power Supply Filtering Diagram
- Wiring the Differential Input to Accept Single Ended Levels
- Single Ended Signal Driving Differential Input Diagram
- Termination for LVPECL Outputs
- LVPECL Output Termination Diagrams
- Layout Guideline
- Schematic of Recommended Layout
- Power & Grounding
- Clock Traces & Termination
- PCB BOard Layout
- Power Considerations
- Power Dissipation
- Junction Temperature
- Thermal Resistance
- Calculations & Equations
- LVPECL Driver Circuit & Termination Diagram
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
8432DY-101
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 13, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS8432-101 is a general purpose, dual out-
put Differential-to-3.3V LVPECL high frequency
synthesizer and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8432-101 has a selectable
TEST_CLK or CLK, nCLK inputs. The TEST_CLK input accepts
LVCMOS or LVTTL input levels and translates them to 3.3V
LVPECL levels. The CLK, nCLK pair can accept most standard
differential input levels. The VCO operates at a frequency range
of 200MHz to 700MHz. The VCO frequency is programmed in
steps equal to the value of the input differential or single ended
reference frequency. The VCO and output frequency can be
programmed using the serial or parallel interfaces to the con-
figuration logic. The low phase noise characteristics of the
ICS8432-101 makes it an ideal clock source for Gigabit Ethernet
and SONET applications.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
F
EATURES
Dual differential 3.3V LVPECL outputs
Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK
TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL
CLK, nCLK or TEST_CLK maximum input frequency: 40MHz
Output frequency range: 25MHz to 700MHz
VCO range: 200MHz to 700MHz
Accepts any single-ended input signal on CLK input
with resistor bias on nCLK input
Parallel interface for programming counter
and output dividers
RMS period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
0C to 70C ambient operating temperature
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CLK
TEST_CLK
CLK_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
M5
M6
M7
M8
N 0
N 1
nc
V
EE
V
EE
nFOUT0
FOUT0
V
CCO
nFOUT1
FOUT1
V
CC
TEST
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8432-101
VCO_SEL
CLK_SEL
TEST_CLK
CLK
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
VCO
PLL
FOUT0
nFOUT0
FOUT1
nFOUT1
TEST
CONFIGURATION
INTERFACE
LOGIC
M
0
1
0
1
PHASE DETECTOR
1
2
4
8
MR
nCLK
HiPerClockSTM
,&6
8432DY-101
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 13, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz clock input. Valid PLL loop divider values
for different input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-101 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A differential clock input is used as the input to the ICS8432-101. This input is fed into the phase detector.
A 25MHz clock input provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of
200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO
control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8432-101 support two input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial.
Figure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and
N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded
until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set
the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship between the VCO frequency, the input frequency and the
M divider is defined as follows:
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8
M
28. The frequency out is
defined as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each
rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal
registers T0 and T1 determine the state of the TEST output as follows:
fVCO = fIN x M
T1
T0
TEST Output
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
t
S
t
H
t
S
t
H
t
S
T1
T0
*NULL
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
*NOTE: The NULL timing slot must be observed.
fOUT = fVCO = fIN x M
N
N
8432DY-101
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 13, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
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8432DY-101
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 13, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. P
ARALLEL
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8432DY-101
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 13, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8432-101
700MH
Z
,
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V5%, T
A
= 0C
TO
70C
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V
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5 V
Outputs, V
O
-0.5V to V
CCO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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